[net-next-2.6.git] / arch / sh / drivers / pci / pcie-sh7786.c

/*
 * Low-Level PCI Express Support for the SH7786
 *
 *  Copyright (C) 2009 - 2010  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include "pcie-sh7786.h"
#include <asm/sizes.h>

struct sh7786_pcie_port {
	struct pci_channel	*hose;
	unsigned int		index;
	int			endpoint;
	int			link;
};

static struct sh7786_pcie_port *sh7786_pcie_ports;
static unsigned int nr_ports;

static struct sh7786_pcie_hwops {
	int (*core_init)(void);
	int (*port_init_hw)(struct sh7786_pcie_port *port);
} *sh7786_pcie_hwops;

static struct resource sh7786_pci0_resources[] = {
	{
		.name	= "PCIe0 IO",
		.start	= 0xfd000000,
		.end	= 0xfd000000 + SZ_8M - 1,
		.flags	= IORESOURCE_IO,
	}, {
		.name	= "PCIe0 MEM 0",
		.start	= 0xc0000000,
		.end	= 0xc0000000 + SZ_512M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe0 MEM 1",
		.start	= 0x10000000,
		.end	= 0x10000000 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "PCIe0 MEM 2",
		.start	= 0xfe100000,
		.end	= 0xfe100000 + SZ_1M - 1,
	},
};

static struct resource sh7786_pci1_resources[] = {
	{
		.name	= "PCIe1 IO",
		.start	= 0xfd800000,
		.end	= 0xfd800000 + SZ_8M - 1,
		.flags	= IORESOURCE_IO,
	}, {
		.name	= "PCIe1 MEM 0",
		.start	= 0xa0000000,
		.end	= 0xa0000000 + SZ_512M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe1 MEM 1",
		.start	= 0x30000000,
		.end	= 0x30000000 + SZ_256M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe1 MEM 2",
		.start	= 0xfe300000,
		.end	= 0xfe300000 + SZ_1M - 1,
	},
};

static struct resource sh7786_pci2_resources[] = {
	{
		.name	= "PCIe2 IO",
		.start	= 0xfc800000,
		.end	= 0xfc800000 + SZ_4M - 1,
	}, {
		.name	= "PCIe2 MEM 0",
		.start	= 0x80000000,
		.end	= 0x80000000 + SZ_512M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe2 MEM 1",
		.start	= 0x20000000,
		.end	= 0x20000000 + SZ_256M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe2 MEM 2",
		.start	= 0xfcd00000,
		.end	= 0xfcd00000 + SZ_1M - 1,
	},
};

extern struct pci_ops sh7786_pci_ops;

#define DEFINE_CONTROLLER(start, idx)					\
{									\
	.pci_ops	= &sh7786_pci_ops,				\
	.resources	= sh7786_pci##idx##_resources,			\
	.nr_resources	= ARRAY_SIZE(sh7786_pci##idx##_resources),	\
	.reg_base	= start,					\
	.mem_offset	= 0,						\
	.io_offset	= 0,						\
}

static struct pci_channel sh7786_pci_channels[] = {
	DEFINE_CONTROLLER(0xfe000000, 0),
	DEFINE_CONTROLLER(0xfe200000, 1),
	DEFINE_CONTROLLER(0xfcc00000, 2),
};

static int phy_wait_for_ack(struct pci_channel *chan)
{
	unsigned int timeout = 100;

	while (timeout--) {
		if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
			return 0;

		udelay(100);
	}

	return -ETIMEDOUT;
}

static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
{
	unsigned int timeout = 100;

	while (timeout--) {
		if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
			return 0;

		udelay(100);
	}

	return -ETIMEDOUT;
}

static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
			  unsigned int lane, unsigned int data)
{
	unsigned long phyaddr;

	phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
			((addr & 0xff) << BITS_ADR);

	/* Set write data */
	pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
	pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);

	phy_wait_for_ack(chan);

	/* Clear command */
	pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
	pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);

	phy_wait_for_ack(chan);
}

static int phy_init(struct pci_channel *chan)
{
	unsigned long ctrl;
	unsigned int timeout = 100;

	/* Enable clock */
	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	ctrl |= (1 << BITS_CKE);
	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);

	/* Initialize the phy */
	phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
	phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
	phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
	phy_write_reg(chan, 0x65, 0xf, 0x09070907);
	phy_write_reg(chan, 0x66, 0xf, 0x00000010);
	phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
	phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
	phy_write_reg(chan, 0xb0, 0xf, 0x00000610);

	/* Deassert Standby */
	phy_write_reg(chan, 0x67, 0x1, 0x00000400);

	/* Disable clock */
	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	ctrl &= ~(1 << BITS_CKE);
	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);

	while (timeout--) {
		if (pci_read_reg(chan, SH4A_PCIEPHYSR))
			return 0;

		udelay(100);
	}

	return -ETIMEDOUT;
}

static void pcie_reset(struct sh7786_pcie_port *port)
{
	struct pci_channel *chan = port->hose;

	pci_write_reg(chan, 1, SH4A_PCIESRSTR);
	pci_write_reg(chan, 0, SH4A_PCIETCTLR);
	pci_write_reg(chan, 0, SH4A_PCIESRSTR);
	pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
}

static int pcie_init(struct sh7786_pcie_port *port)
{
	struct pci_channel *chan = port->hose;
	unsigned int data;
	phys_addr_t memphys;
	size_t memsize;
	int ret, i, win;

	/* Begin initialization */
	pcie_reset(port);

	/* Initialize as type1. */
	data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
	data &= ~(0x7f << 16);
	data |= PCI_HEADER_TYPE_BRIDGE << 16;
	pci_write_reg(chan, data, SH4A_PCIEPCICONF3);

	/* Initialize default capabilities. */
	data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
	data &= ~(PCI_EXP_FLAGS_TYPE << 16);

	if (port->endpoint)
		data |= PCI_EXP_TYPE_ENDPOINT << 20;
	else
		data |= PCI_EXP_TYPE_ROOT_PORT << 20;

	data |= PCI_CAP_ID_EXP;
	pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);

	/* Enable data link layer active state reporting */
	pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);

	/* Enable extended sync and ASPM L0s support */
	data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
	data &= ~PCI_EXP_LNKCTL_ASPMC;
	data |= PCI_EXP_LNKCTL_ES | 1;
	pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);

	/* Write out the physical slot number */
	data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
	data &= ~PCI_EXP_SLTCAP_PSN;
	data |= (port->index + 1) << 19;
	pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);

	/* Set the completion timer timeout to the maximum 32ms. */
	data = pci_read_reg(chan, SH4A_PCIETLCTLR);
	data &= ~0x3f00;
	data |= 0x32 << 8;
	pci_write_reg(chan, data, SH4A_PCIETLCTLR);

	/*
	 * Set fast training sequences to the maximum 255,
	 * and enable MAC data scrambling.
	 */
	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	data &= ~PCIEMACCTLR_SCR_DIS;
	data |= (0xff << 16);
	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);

	memphys = __pa(memory_start);
	memsize = roundup_pow_of_two(memory_end - memory_start);

	/*
	 * If there's more than 512MB of memory, we need to roll over to
	 * LAR1/LAMR1.
	 */
	if (memsize > SZ_512M) {
		__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
		__raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
			     chan->reg_base + SH4A_PCIELAMR1);
		memsize = SZ_512M;
	} else {
		/*
		 * Otherwise just zero it out and disable it.
		 */
		__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
		__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
	}

	/*
	 * LAR0/LAMR0 covers up to the first 512MB, which is enough to
	 * cover all of lowmem on most platforms.
	 */
	__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
	__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);

	__raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
	__raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);

	/* Finish initialization */
	data = pci_read_reg(chan, SH4A_PCIETCTLR);
	data |= 0x1;
	pci_write_reg(chan, data, SH4A_PCIETCTLR);

	/* Enable DL_Active Interrupt generation */
	data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
	data |= PCIEDLINTENR_DLL_ACT_ENABLE;
	pci_write_reg(chan, data, SH4A_PCIEDLINTENR);

	/* Disable MAC data scrambling. */
	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);

	ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
	if (unlikely(ret != 0))
		return -ENODEV;

	data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
	data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
	data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
		(PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
	pci_write_reg(chan, data, SH4A_PCIEPCICONF1);

	pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
	pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);

	wmb();

	data = pci_read_reg(chan, SH4A_PCIEMACSR);
	printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
	       port->index, (data >> 20) & 0x3f);

	for (i = win = 0; i < chan->nr_resources; i++) {
		struct resource *res = chan->resources + i;
		resource_size_t size;
		u32 enable_mask;

		/*
		 * We can't use the 32-bit mode windows in legacy 29-bit
		 * mode, so just skip them entirely.
		 */
		if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
			continue;

		pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));

		size = resource_size(res);

		/*
		 * The PAMR mask is calculated in units of 256kB, which
		 * keeps things pretty simple.
		 */
		__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
			     chan->reg_base + SH4A_PCIEPAMR(win));

		pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
		pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));

		enable_mask = MASK_PARE;
		if (res->flags & IORESOURCE_IO)
			enable_mask |= MASK_SPC;

		pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));

		win++;
	}

	return 0;
}

int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
        return 71;
}

static int sh7786_pcie_core_init(void)
{
	/* Return the number of ports */
	return test_mode_pin(MODE_PIN12) ? 3 : 2;
}

static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
{
	int ret;

	ret = phy_init(port->hose);
	if (unlikely(ret < 0))
		return ret;

	/*
	 * Check if we are configured in endpoint or root complex mode,
	 * this is a fixed pin setting that applies to all PCIe ports.
	 */
	port->endpoint = test_mode_pin(MODE_PIN11);

	ret = pcie_init(port);
	if (unlikely(ret < 0))
		return ret;

	return register_pci_controller(port->hose);
}

static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
	.core_init	= sh7786_pcie_core_init,
	.port_init_hw	= sh7786_pcie_init_hw,
};

static int __init sh7786_pcie_init(void)
{
	int ret = 0, i;

	printk(KERN_NOTICE "PCI: Starting intialization.\n");

	sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;

	nr_ports = sh7786_pcie_hwops->core_init();
	BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));

	if (unlikely(nr_ports == 0))
		return -ENODEV;

	sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
				    GFP_KERNEL);
	if (unlikely(!sh7786_pcie_ports))
		return -ENOMEM;

	printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);

	for (i = 0; i < nr_ports; i++) {
		struct sh7786_pcie_port *port = sh7786_pcie_ports + i;

		port->index		= i;
		port->hose		= sh7786_pci_channels + i;
		port->hose->io_map_base	= port->hose->resources[0].start;

		ret |= sh7786_pcie_hwops->port_init_hw(port);
	}

	if (unlikely(ret))
		return ret;

	return 0;
}
arch_initcall(sh7786_pcie_init);
Commit	Line	Data
5713e602 PM	1	/*
	2	* Low-Level PCI Express Support for the SH7786
	3	*
7561f2dd	4	* Copyright (C) 2009 - 2010 Paul Mundt
5713e602 PM	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/pci.h>
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/io.h>
	14	#include <linux/delay.h>
5a0e3ad6	15	#include <linux/slab.h>
5713e602 PM	16	#include "pcie-sh7786.h"
	17	#include <asm/sizes.h>
	18
	19	struct sh7786_pcie_port {
	20	struct pci_channel *hose;
	21	unsigned int index;
	22	int endpoint;
	23	int link;
	24	};
	25
	26	static struct sh7786_pcie_port *sh7786_pcie_ports;
	27	static unsigned int nr_ports;
	28
	29	static struct sh7786_pcie_hwops {
	30	int (*core_init)(void);
	31	int (port_init_hw)(struct sh7786_pcie_port port);
	32	} *sh7786_pcie_hwops;
	33
7561f2dd	34	static struct resource sh7786_pci0_resources[] = {
5713e602	35	{
7561f2dd PM	36	.name = "PCIe0 IO",
	37	.start = 0xfd000000,
	38	.end = 0xfd000000 + SZ_8M - 1,
	39	.flags = IORESOURCE_IO,
5713e602	40	}, {
7561f2dd PM	41	.name = "PCIe0 MEM 0",
	42	.start = 0xc0000000,
	43	.end = 0xc0000000 + SZ_512M - 1,
	44	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
5713e602	45	}, {
7561f2dd PM	46	.name = "PCIe0 MEM 1",
	47	.start = 0x10000000,
	48	.end = 0x10000000 + SZ_64M - 1,
5713e602	49	.flags = IORESOURCE_MEM,
7561f2dd PM	50	}, {
	51	.name = "PCIe0 MEM 2",
	52	.start = 0xfe100000,
	53	.end = 0xfe100000 + SZ_1M - 1,
5713e602 PM	54	},
	55	};
	56
7561f2dd PM	57	static struct resource sh7786_pci1_resources[] = {
	58	{
	59	.name = "PCIe1 IO",
	60	.start = 0xfd800000,
	61	.end = 0xfd800000 + SZ_8M - 1,
	62	.flags = IORESOURCE_IO,
	63	}, {
	64	.name = "PCIe1 MEM 0",
	65	.start = 0xa0000000,
	66	.end = 0xa0000000 + SZ_512M - 1,
	67	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	68	}, {
	69	.name = "PCIe1 MEM 1",
	70	.start = 0x30000000,
	71	.end = 0x30000000 + SZ_256M - 1,
	72	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	73	}, {
	74	.name = "PCIe1 MEM 2",
	75	.start = 0xfe300000,
	76	.end = 0xfe300000 + SZ_1M - 1,
	77	},
5713e602 PM	78	};
5713e602 PM	79
7561f2dd	80	static struct resource sh7786_pci2_resources[] = {
5713e602	81	{
7561f2dd PM	82	.name = "PCIe2 IO",
	83	.start = 0xfc800000,
	84	.end = 0xfc800000 + SZ_4M - 1,
5713e602	85	}, {
7561f2dd PM	86	.name = "PCIe2 MEM 0",
	87	.start = 0x80000000,
	88	.end = 0x80000000 + SZ_512M - 1,
	89	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
5713e602	90	}, {
7561f2dd PM	91	.name = "PCIe2 MEM 1",
	92	.start = 0x20000000,
	93	.end = 0x20000000 + SZ_256M - 1,
	94	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	95	}, {
	96	.name = "PCIe2 MEM 2",
	97	.start = 0xfcd00000,
	98	.end = 0xfcd00000 + SZ_1M - 1,
5713e602 PM	99	},
	100	};
	101
	102	extern struct pci_ops sh7786_pci_ops;
	103
7561f2dd PM	104	#define DEFINE_CONTROLLER(start, idx) \
	105	{ \
	106	.pci_ops = &sh7786_pci_ops, \
	107	.resources = sh7786_pci##idx##_resources, \
	108	.nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
	109	.reg_base = start, \
	110	.mem_offset = 0, \
	111	.io_offset = 0, \
5713e602 PM	112	}
	113
	114	static struct pci_channel sh7786_pci_channels[] = {
	115	DEFINE_CONTROLLER(0xfe000000, 0),
	116	DEFINE_CONTROLLER(0xfe200000, 1),
	117	DEFINE_CONTROLLER(0xfcc00000, 2),
	118	};
	119
	120	static int phy_wait_for_ack(struct pci_channel *chan)
	121	{
	122	unsigned int timeout = 100;
	123
	124	while (timeout--) {
	125	if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
	126	return 0;
	127
	128	udelay(100);
	129	}
	130
	131	return -ETIMEDOUT;
	132	}
	133
	134	static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
	135	{
	136	unsigned int timeout = 100;
	137
	138	while (timeout--) {
	139	if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
	140	return 0;
	141
	142	udelay(100);
	143	}
	144
	145	return -ETIMEDOUT;
	146	}
	147
	148	static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
	149	unsigned int lane, unsigned int data)
	150	{
53178d71	151	unsigned long phyaddr;
5713e602 PM	152
	153	phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
	154	((addr & 0xff) << BITS_ADR);
	155
5713e602 PM	156	/* Set write data */
	157	pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
	158	pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
	159
	160	phy_wait_for_ack(chan);
	161
	162	/* Clear command */
53178d71	163	pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
5713e602 PM	164	pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
	165
	166	phy_wait_for_ack(chan);
5713e602 PM	167	}
	168
	169	static int phy_init(struct pci_channel *chan)
	170	{
53178d71	171	unsigned long ctrl;
5713e602 PM	172	unsigned int timeout = 100;
5713e602 PM	173
53178d71 PM	174	/* Enable clock */
	175	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	176	ctrl \|= (1 << BITS_CKE);
	177	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
	178
5713e602 PM	179	/* Initialize the phy */
	180	phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
	181	phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
	182	phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
	183	phy_write_reg(chan, 0x65, 0xf, 0x09070907);
	184	phy_write_reg(chan, 0x66, 0xf, 0x00000010);
	185	phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
	186	phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
53178d71	187	phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
5713e602 PM	188
5713e602 PM	189	/* Deassert Standby */
53178d71 PM	190	phy_write_reg(chan, 0x67, 0x1, 0x00000400);
	191
	192	/* Disable clock */
	193	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	194	ctrl &= ~(1 << BITS_CKE);
	195	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
5713e602 PM	196
	197	while (timeout--) {
	198	if (pci_read_reg(chan, SH4A_PCIEPHYSR))
	199	return 0;
	200
	201	udelay(100);
	202	}
	203
	204	return -ETIMEDOUT;
	205	}
	206
2dbfa1e3 PM	207	static void pcie_reset(struct sh7786_pcie_port *port)
	208	{
	209	struct pci_channel *chan = port->hose;
	210
	211	pci_write_reg(chan, 1, SH4A_PCIESRSTR);
	212	pci_write_reg(chan, 0, SH4A_PCIETCTLR);
	213	pci_write_reg(chan, 0, SH4A_PCIESRSTR);
	214	pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
	215	}
	216
5713e602 PM	217	static int pcie_init(struct sh7786_pcie_port *port)
	218	{
	219	struct pci_channel *chan = port->hose;
	220	unsigned int data;
7578a4c6 PM	221	phys_addr_t memphys;
7578a4c6 PM	222	size_t memsize;
da03a63a	223	int ret, i, win;
5713e602 PM	224
5713e602 PM	225	/* Begin initialization */
2dbfa1e3	226	pcie_reset(port);
5713e602 PM	227
	228	/* Initialize as type1. */
	229	data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
	230	data &= ~(0x7f << 16);
	231	data \|= PCI_HEADER_TYPE_BRIDGE << 16;
	232	pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
	233
	234	/* Initialize default capabilities. */
	235	data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
	236	data &= ~(PCI_EXP_FLAGS_TYPE << 16);
	237
	238	if (port->endpoint)
	239	data \|= PCI_EXP_TYPE_ENDPOINT << 20;
	240	else
	241	data \|= PCI_EXP_TYPE_ROOT_PORT << 20;
	242
	243	data \|= PCI_CAP_ID_EXP;
	244	pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
	245
7578a4c6 PM	246	/* Enable data link layer active state reporting */
	247	pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
	248
	249	/* Enable extended sync and ASPM L0s support */
5713e602	250	data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
7578a4c6 PM	251	data &= ~PCI_EXP_LNKCTL_ASPMC;
7578a4c6 PM	252	data \|= PCI_EXP_LNKCTL_ES \| 1;
5713e602 PM	253	pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
5713e602 PM	254
7578a4c6 PM	255	/* Write out the physical slot number */
	256	data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
	257	data &= ~PCI_EXP_SLTCAP_PSN;
	258	data \|= (port->index + 1) << 19;
	259	pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
	260
5713e602 PM	261	/* Set the completion timer timeout to the maximum 32ms. */
5713e602 PM	262	data = pci_read_reg(chan, SH4A_PCIETLCTLR);
7578a4c6	263	data &= ~0x3f00;
5713e602 PM	264	data \|= 0x32 << 8;
	265	pci_write_reg(chan, data, SH4A_PCIETLCTLR);
	266
	267	/*
	268	* Set fast training sequences to the maximum 255,
	269	* and enable MAC data scrambling.
	270	*/
	271	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	272	data &= ~PCIEMACCTLR_SCR_DIS;
	273	data \|= (0xff << 16);
	274	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
	275
7578a4c6 PM	276	memphys = __pa(memory_start);
	277	memsize = roundup_pow_of_two(memory_end - memory_start);
	278
	279	/*
	280	* If there's more than 512MB of memory, we need to roll over to
	281	* LAR1/LAMR1.
	282	*/
	283	if (memsize > SZ_512M) {
	284	__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
	285	__raw_writel(((memsize - SZ_512M) - SZ_256) \| 1,
	286	chan->reg_base + SH4A_PCIELAMR1);
	287	memsize = SZ_512M;
	288	} else {
	289	/*
	290	* Otherwise just zero it out and disable it.
	291	*/
	292	__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
	293	__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
	294	}
	295
	296	/*
	297	* LAR0/LAMR0 covers up to the first 512MB, which is enough to
	298	* cover all of lowmem on most platforms.
	299	*/
	300	__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
	301	__raw_writel((memsize - SZ_256) \| 1, chan->reg_base + SH4A_PCIELAMR0);
	302
53178d71 PM	303	__raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
	304	__raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);
	305
5713e602 PM	306	/* Finish initialization */
	307	data = pci_read_reg(chan, SH4A_PCIETCTLR);
	308	data \|= 0x1;
	309	pci_write_reg(chan, data, SH4A_PCIETCTLR);
	310
	311	/* Enable DL_Active Interrupt generation */
	312	data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
	313	data \|= PCIEDLINTENR_DLL_ACT_ENABLE;
	314	pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
	315
	316	/* Disable MAC data scrambling. */
	317	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	318	data \|= PCIEMACCTLR_SCR_DIS \| (0xff << 16);
	319	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
	320
	321	ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
	322	if (unlikely(ret != 0))
	323	return -ENODEV;
	324
7578a4c6 PM	325	data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
	326	data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
	327	data \|= PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \|
	328	(PCI_STATUS_CAP_LIST \| PCI_STATUS_DEVSEL_FAST) << 16;
	329	pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
	330
5713e602 PM	331	pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
5713e602 PM	332	pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
5713e602 PM	333
	334	wmb();
	335
	336	data = pci_read_reg(chan, SH4A_PCIEMACSR);
	337	printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
	338	port->index, (data >> 20) & 0x3f);
	339
da03a63a	340	for (i = win = 0; i < chan->nr_resources; i++) {
7578a4c6 PM	341	struct resource *res = chan->resources + i;
	342	resource_size_t size;
	343	u32 enable_mask;
	344
da03a63a PM	345	/*
	346	* We can't use the 32-bit mode windows in legacy 29-bit
	347	* mode, so just skip them entirely.
	348	*/
	349	if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
	350	continue;
	351
	352	pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
7578a4c6 PM	353
	354	size = resource_size(res);
	355
	356	/*
	357	* The PAMR mask is calculated in units of 256kB, which
	358	* keeps things pretty simple.
	359	*/
	360	__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
da03a63a	361	chan->reg_base + SH4A_PCIEPAMR(win));
7578a4c6	362
da03a63a PM	363	pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
da03a63a PM	364	pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
7578a4c6 PM	365
	366	enable_mask = MASK_PARE;
	367	if (res->flags & IORESOURCE_IO)
	368	enable_mask \|= MASK_SPC;
	369
da03a63a PM	370	pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
	371
	372	win++;
7578a4c6	373	}
5713e602 PM	374
	375	return 0;
	376	}
	377
	378	int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
	379	{
	380	return 71;
	381	}
	382
	383	static int sh7786_pcie_core_init(void)
	384	{
	385	/* Return the number of ports */
	386	return test_mode_pin(MODE_PIN12) ? 3 : 2;
	387	}
	388
	389	static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
	390	{
	391	int ret;
	392
	393	ret = phy_init(port->hose);
	394	if (unlikely(ret < 0))
	395	return ret;
	396
	397	/*
	398	* Check if we are configured in endpoint or root complex mode,
	399	* this is a fixed pin setting that applies to all PCIe ports.
	400	*/
	401	port->endpoint = test_mode_pin(MODE_PIN11);
	402
	403	ret = pcie_init(port);
	404	if (unlikely(ret < 0))
	405	return ret;
	406
bcf39352	407	return register_pci_controller(port->hose);
5713e602 PM	408	}
	409
	410	static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
	411	.core_init = sh7786_pcie_core_init,
	412	.port_init_hw = sh7786_pcie_init_hw,
	413	};
	414
	415	static int __init sh7786_pcie_init(void)
	416	{
	417	int ret = 0, i;
	418
	419	printk(KERN_NOTICE "PCI: Starting intialization.\n");
	420
	421	sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
	422
	423	nr_ports = sh7786_pcie_hwops->core_init();
	424	BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));
	425
	426	if (unlikely(nr_ports == 0))
	427	return -ENODEV;
	428
	429	sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
	430	GFP_KERNEL);
	431	if (unlikely(!sh7786_pcie_ports))
	432	return -ENOMEM;
	433
	434	printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
	435
	436	for (i = 0; i < nr_ports; i++) {
	437	struct sh7786_pcie_port *port = sh7786_pcie_ports + i;
	438
	439	port->index = i;
	440	port->hose = sh7786_pci_channels + i;
7561f2dd	441	port->hose->io_map_base = port->hose->resources[0].start;
5713e602 PM	442
	443	ret \|= sh7786_pcie_hwops->port_init_hw(port);
	444	}
	445
	446	if (unlikely(ret))
	447	return ret;
	448
	449	return 0;
	450	}
	451	arch_initcall(sh7786_pcie_init);