[net-next-2.6.git] / arch / sh / drivers / pci / pci.c

/*
 * New-style PCI core.
 *
 * Copyright (c) 2004 - 2009  Paul Mundt
 * Copyright (c) 2002  M. R. Brown
 *
 * Modelled after arch/mips/pci/pci.c:
 *  Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/dma-debug.h>
#include <linux/io.h>
#include <linux/mutex.h>

unsigned long PCIBIOS_MIN_IO = 0x0000;
unsigned long PCIBIOS_MIN_MEM = 0;

/*
 * The PCI controller list.
 */
static struct pci_channel *hose_head, **hose_tail = &hose_head;

static int pci_initialized;

static void __devinit pcibios_scanbus(struct pci_channel *hose)
{
	static int next_busno;
	static int need_domain_info;
	struct pci_bus *bus;

	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
	hose->bus = bus;

	need_domain_info = need_domain_info || hose->index;
	hose->need_domain_info = need_domain_info;
	if (bus) {
		next_busno = bus->subordinate + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}

		pci_bus_size_bridges(bus);
		pci_bus_assign_resources(bus);
		pci_enable_bridges(bus);
	}
}

static DEFINE_MUTEX(pci_scan_mutex);

int __devinit register_pci_controller(struct pci_channel *hose)
{
	int i;

	for (i = 0; i < hose->nr_resources; i++) {
		struct resource *res = hose->resources + i;

		if (res->flags & IORESOURCE_IO) {
			if (request_resource(&ioport_resource, res) < 0)
				goto out;
		} else {
			if (request_resource(&iomem_resource, res) < 0)
				goto out;
		}
	}

	*hose_tail = hose;
	hose_tail = &hose->next;

	/*
	 * Do not panic here but later - this might hapen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}

	/*
	 * Setup the ERR/PERR and SERR timers, if available.
	 */
	pcibios_enable_timers(hose);

	/*
	 * Scan the bus if it is register after the PCI subsystem
	 * initialization.
	 */
	if (pci_initialized) {
		mutex_lock(&pci_scan_mutex);
		pcibios_scanbus(hose);
		mutex_unlock(&pci_scan_mutex);
	}

	return 0;

out:
	for (--i; i >= 0; i--)
		release_resource(&hose->resources[i]);

	printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
	return -1;
}

static int __init pcibios_init(void)
{
	struct pci_channel *hose;

	/* Scan all of the recorded PCI controllers.  */
	for (hose = hose_head; hose; hose = hose->next)
		pcibios_scanbus(hose);

	pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);

	dma_debug_add_bus(&pci_bus_type);

	pci_initialized = 1;

	return 0;
}
subsys_initcall(pcibios_init);

static void pcibios_fixup_device_resources(struct pci_dev *dev,
	struct pci_bus *bus)
{
	/* Update device resources.  */
	struct pci_channel *hose = bus->sysdata;
	unsigned long offset = 0;
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!dev->resource[i].start)
			continue;
		if (dev->resource[i].flags & IORESOURCE_IO)
			offset = hose->io_offset;
		else if (dev->resource[i].flags & IORESOURCE_MEM)
			offset = hose->mem_offset;

		dev->resource[i].start += offset;
		dev->resource[i].end += offset;
	}
}

/*
 *  Called after each bus is probed, but before its children
 *  are examined.
 */
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;
	struct list_head *ln;
	struct pci_channel *hose = bus->sysdata;

	if (!dev) {
		int i;

		for (i = 0; i < hose->nr_resources; i++)
			bus->resource[i] = hose->resources + i;
	}

	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
		dev = pci_dev_b(ln);

		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
			pcibios_fixup_device_resources(dev, bus);
	}
}

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 */
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
				resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_channel *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
			start = PCIBIOS_MIN_IO + hose->resources[0].start;

		/*
                 * Put everything into 0x00-0xff region modulo 0x400.
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}

	return start;
}

void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			     struct resource *res)
{
	struct pci_channel *hose = dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	region->start = res->start - offset;
	region->end = res->end - offset;
}

void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			     struct pci_bus_region *region)
{
	struct pci_channel *hose = dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	res->start = region->start + offset;
	res->end = region->end + offset;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1<<idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available "
			       "because of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

/*
 *  If we set up a device for bus mastering, we need to check and set
 *  the latency timer as it may not be properly set.
 */
static unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

char * __devinit pcibios_setup(char *str)
{
	return str;
}

static void __init
pcibios_bus_report_status_early(struct pci_channel *hose,
				int top_bus, int current_bus,
				unsigned int status_mask, int warn)
{
	unsigned int pci_devfn;
	u16 status;
	int ret;

	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
		if (PCI_FUNC(pci_devfn))
			continue;
		ret = early_read_config_word(hose, top_bus, current_bus,
					     pci_devfn, PCI_STATUS, &status);
		if (ret != PCIBIOS_SUCCESSFUL)
			continue;
		if (status == 0xffff)
			continue;

		early_write_config_word(hose, top_bus, current_bus,
					pci_devfn, PCI_STATUS,
					status & status_mask);
		if (warn)
			printk("(%02x:%02x: %04X) ", current_bus,
			       pci_devfn, status);
	}
}

/*
 * We can't use pci_find_device() here since we are
 * called from interrupt context.
 */
static void __init_refok
pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
			  int warn)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 status;

		/*
		 * ignore host bridge - we handle
		 * that separately
		 */
		if (dev->bus->number == 0 && dev->devfn == 0)
			continue;

		pci_read_config_word(dev, PCI_STATUS, &status);
		if (status == 0xffff)
			continue;

		if ((status & status_mask) == 0)
			continue;

		/* clear the status errors */
		pci_write_config_word(dev, PCI_STATUS, status & status_mask);

		if (warn)
			printk("(%s: %04X) ", pci_name(dev), status);
	}

	list_for_each_entry(dev, &bus->devices, bus_list)
		if (dev->subordinate)
			pcibios_bus_report_status(dev->subordinate, status_mask, warn);
}

void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
{
	struct pci_channel *hose;

	for (hose = hose_head; hose; hose = hose->next) {
		if (unlikely(!hose->bus))
			pcibios_bus_report_status_early(hose, hose_head->index,
					hose->index, status_mask, warn);
		else
			pcibios_bus_report_status(hose->bus, status_mask, warn);
	}
}

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	/*
	 * I/O space can be accessed via normal processor loads and stores on
	 * this platform but for now we elect not to do this and portable
	 * drivers should not do this anyway.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	/*
	 * Ignore write-combine; for now only return uncached mappings.
	 */
	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);

	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			       vma->vm_end - vma->vm_start,
			       vma->vm_page_prot);
}

#ifndef CONFIG_GENERIC_IOMAP

static void __iomem *ioport_map_pci(struct pci_dev *dev,
				    unsigned long port, unsigned int nr)
{
	struct pci_channel *chan = dev->sysdata;

	if (unlikely(!chan->io_map_base)) {
		chan->io_map_base = generic_io_base;

		if (pci_domains_supported)
			panic("To avoid data corruption io_map_base MUST be "
			      "set with multiple PCI domains.");
	}


	return (void __iomem *)(chan->io_map_base + port);
}

void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
	resource_size_t start = pci_resource_start(dev, bar);
	resource_size_t len = pci_resource_len(dev, bar);
	unsigned long flags = pci_resource_flags(dev, bar);

	if (unlikely(!len || !start))
		return NULL;
	if (maxlen && len > maxlen)
		len = maxlen;

	if (flags & IORESOURCE_IO)
		return ioport_map_pci(dev, start, len);
	if (flags & IORESOURCE_MEM) {
		if (flags & IORESOURCE_CACHEABLE)
			return ioremap(start, len);
		return ioremap_nocache(start, len);
	}

	return NULL;
}
EXPORT_SYMBOL(pci_iomap);

void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
{
	iounmap(addr);
}
EXPORT_SYMBOL(pci_iounmap);

#endif /* CONFIG_GENERIC_IOMAP */

#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
EXPORT_SYMBOL(pcibios_bus_to_resource);
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
#endif
Commit	Line	Data
4c5107e4 PM	1	/*
	2	* New-style PCI core.
	3	*
4c5107e4	4	* Copyright (c) 2004 - 2009 Paul Mundt
35bcfffd PM	5	* Copyright (c) 2002 M. R. Brown
	6	*
	7	* Modelled after arch/mips/pci/pci.c:
	8	* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
4c5107e4 PM	9	*
	10	* This file is subject to the terms and conditions of the GNU General Public
	11	* License. See the file "COPYING" in the main directory of this archive
	12	* for more details.
	13	*/
	14	#include <linux/kernel.h>
35bcfffd	15	#include <linux/mm.h>
4c5107e4 PM	16	#include <linux/pci.h>
4c5107e4 PM	17	#include <linux/init.h>
35bcfffd	18	#include <linux/types.h>
4c5107e4 PM	19	#include <linux/dma-debug.h>
4c5107e4 PM	20	#include <linux/io.h>
e79066a6	21	#include <linux/mutex.h>
4c5107e4	22
35bcfffd PM	23	unsigned long PCIBIOS_MIN_IO = 0x0000;
	24	unsigned long PCIBIOS_MIN_MEM = 0;
	25
e79066a6 PM	26	/*
	27	* The PCI controller list.
	28	*/
	29	static struct pci_channel hose_head, *hose_tail = &hose_head;
	30
	31	static int pci_initialized;
	32
	33	static void __devinit pcibios_scanbus(struct pci_channel *hose)
4c5107e4	34	{
e79066a6	35	static int next_busno;
320e68da	36	static int need_domain_info;
4c5107e4	37	struct pci_bus *bus;
e79066a6	38
e79066a6	39	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
320e68da PM	40	hose->bus = bus;
	41
	42	need_domain_info = need_domain_info \|\| hose->index;
	43	hose->need_domain_info = need_domain_info;
e79066a6 PM	44	if (bus) {
	45	next_busno = bus->subordinate + 1;
	46	/* Don't allow 8-bit bus number overflow inside the hose -
	47	reserve some space for bridges. */
320e68da	48	if (next_busno > 224) {
e79066a6	49	next_busno = 0;
320e68da PM	50	need_domain_info = 1;
320e68da PM	51	}
e79066a6 PM	52
	53	pci_bus_size_bridges(bus);
	54	pci_bus_assign_resources(bus);
	55	pci_enable_bridges(bus);
4c5107e4	56	}
e79066a6	57	}
4c5107e4	58
e79066a6	59	static DEFINE_MUTEX(pci_scan_mutex);
4c5107e4	60
bcf39352	61	int __devinit register_pci_controller(struct pci_channel *hose)
e79066a6	62	{
b6c58b1d PM	63	int i;
	64
	65	for (i = 0; i < hose->nr_resources; i++) {
	66	struct resource *res = hose->resources + i;
	67
	68	if (res->flags & IORESOURCE_IO) {
	69	if (request_resource(&ioport_resource, res) < 0)
	70	goto out;
	71	} else {
	72	if (request_resource(&iomem_resource, res) < 0)
	73	goto out;
	74	}
ac8ab54a	75	}
e79066a6 PM	76
	77	*hose_tail = hose;
	78	hose_tail = &hose->next;
	79
	80	/*
	81	* Do not panic here but later - this might hapen before console init.
	82	*/
	83	if (!hose->io_map_base) {
	84	printk(KERN_WARNING
	85	"registering PCI controller with io_map_base unset\n");
	86	}
	87
ef407bee PM	88	/*
	89	* Setup the ERR/PERR and SERR timers, if available.
	90	*/
	91	pcibios_enable_timers(hose);
	92
e79066a6 PM	93	/*
	94	* Scan the bus if it is register after the PCI subsystem
	95	* initialization.
	96	*/
	97	if (pci_initialized) {
	98	mutex_lock(&pci_scan_mutex);
	99	pcibios_scanbus(hose);
	100	mutex_unlock(&pci_scan_mutex);
4c5107e4	101	}
ac8ab54a	102
bcf39352	103	return 0;
85b59f5b	104
ac8ab54a	105	out:
b6c58b1d PM	106	for (--i; i >= 0; i--)
	107	release_resource(&hose->resources[i]);
	108
ac8ab54a	109	printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
bcf39352	110	return -1;
e79066a6 PM	111	}
	112
	113	static int __init pcibios_init(void)
	114	{
	115	struct pci_channel *hose;
	116
	117	/* Scan all of the recorded PCI controllers. */
	118	for (hose = hose_head; hose; hose = hose->next)
	119	pcibios_scanbus(hose);
	120
4c5107e4 PM	121	pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
	122
	123	dma_debug_add_bus(&pci_bus_type);
	124
e79066a6 PM	125	pci_initialized = 1;
e79066a6 PM	126
4c5107e4 PM	127	return 0;
	128	}
	129	subsys_initcall(pcibios_init);
	130
	131	static void pcibios_fixup_device_resources(struct pci_dev *dev,
	132	struct pci_bus *bus)
	133	{
	134	/* Update device resources. */
09cfeb13	135	struct pci_channel *hose = bus->sysdata;
4c5107e4 PM	136	unsigned long offset = 0;
	137	int i;
	138
	139	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	140	if (!dev->resource[i].start)
	141	continue;
4c5107e4	142	if (dev->resource[i].flags & IORESOURCE_IO)
09cfeb13	143	offset = hose->io_offset;
4c5107e4	144	else if (dev->resource[i].flags & IORESOURCE_MEM)
09cfeb13	145	offset = hose->mem_offset;
4c5107e4 PM	146
	147	dev->resource[i].start += offset;
	148	dev->resource[i].end += offset;
	149	}
	150	}
	151
4c5107e4 PM	152	/*
	153	* Called after each bus is probed, but before its children
	154	* are examined.
	155	*/
35bcfffd	156	void __devinit pcibios_fixup_bus(struct pci_bus *bus)
4c5107e4 PM	157	{
	158	struct pci_dev *dev = bus->self;
	159	struct list_head *ln;
b6c58b1d	160	struct pci_channel *hose = bus->sysdata;
4c5107e4 PM	161
4c5107e4 PM	162	if (!dev) {
b6c58b1d PM	163	int i;
	164
	165	for (i = 0; i < hose->nr_resources; i++)
	166	bus->resource[i] = hose->resources + i;
4c5107e4 PM	167	}
	168
	169	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
	170	dev = pci_dev_b(ln);
	171
	172	if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
	173	pcibios_fixup_device_resources(dev, bus);
	174	}
	175	}
35bcfffd PM	176
	177	/*
	178	* We need to avoid collisions with `mirrored' VGA ports
	179	* and other strange ISA hardware, so we always want the
	180	* addresses to be allocated in the 0x000-0x0ff region
	181	* modulo 0x400.
	182	*/
3b7a17fc	183	resource_size_t pcibios_align_resource(void data, const struct resource res,
b26b2d49	184	resource_size_t size, resource_size_t align)
35bcfffd PM	185	{
35bcfffd PM	186	struct pci_dev *dev = data;
b6c58b1d	187	struct pci_channel *hose = dev->sysdata;
35bcfffd PM	188	resource_size_t start = res->start;
	189
	190	if (res->flags & IORESOURCE_IO) {
b6c58b1d PM	191	if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
b6c58b1d PM	192	start = PCIBIOS_MIN_IO + hose->resources[0].start;
35bcfffd PM	193
	194	/*
	195	* Put everything into 0x00-0xff region modulo 0x400.
	196	*/
84959359	197	if (start & 0x300)
35bcfffd	198	start = (start + 0x3ff) & ~0x3ff;
35bcfffd PM	199	}
35bcfffd PM	200
b26b2d49	201	return start;
35bcfffd PM	202	}
	203
	204	void pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
9ad62ec4	205	struct resource *res)
35bcfffd PM	206	{
	207	struct pci_channel *hose = dev->sysdata;
	208	unsigned long offset = 0;
	209
	210	if (res->flags & IORESOURCE_IO)
	211	offset = hose->io_offset;
	212	else if (res->flags & IORESOURCE_MEM)
	213	offset = hose->mem_offset;
	214
	215	region->start = res->start - offset;
	216	region->end = res->end - offset;
	217	}
	218
9ad62ec4 PM	219	void pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
9ad62ec4 PM	220	struct pci_bus_region *region)
35bcfffd PM	221	{
	222	struct pci_channel *hose = dev->sysdata;
	223	unsigned long offset = 0;
	224
	225	if (res->flags & IORESOURCE_IO)
	226	offset = hose->io_offset;
	227	else if (res->flags & IORESOURCE_MEM)
	228	offset = hose->mem_offset;
	229
	230	res->start = region->start + offset;
	231	res->end = region->end + offset;
	232	}
	233
	234	int pcibios_enable_device(struct pci_dev *dev, int mask)
	235	{
	236	u16 cmd, old_cmd;
	237	int idx;
	238	struct resource *r;
	239
	240	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	241	old_cmd = cmd;
	242	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
	243	/* Only set up the requested stuff */
	244	if (!(mask & (1<<idx)))
	245	continue;
	246
	247	r = &dev->resource[idx];
	248	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	249	continue;
	250	if ((idx == PCI_ROM_RESOURCE) &&
	251	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	252	continue;
	253	if (!r->start && r->end) {
	254	printk(KERN_ERR "PCI: Device %s not available "
	255	"because of resource collisions\n",
	256	pci_name(dev));
	257	return -EINVAL;
	258	}
	259	if (r->flags & IORESOURCE_IO)
	260	cmd \|= PCI_COMMAND_IO;
	261	if (r->flags & IORESOURCE_MEM)
	262	cmd \|= PCI_COMMAND_MEMORY;
	263	}
	264	if (cmd != old_cmd) {
	265	printk("PCI: Enabling device %s (%04x -> %04x)\n",
	266	pci_name(dev), old_cmd, cmd);
	267	pci_write_config_word(dev, PCI_COMMAND, cmd);
	268	}
	269	return 0;
	270	}
	271
	272	/*
	273	* If we set up a device for bus mastering, we need to check and set
	274	* the latency timer as it may not be properly set.
	275	*/
	276	static unsigned int pcibios_max_latency = 255;
	277
	278	void pcibios_set_master(struct pci_dev *dev)
	279	{
	280	u8 lat;
	281	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	282	if (lat < 16)
	283	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	284	else if (lat > pcibios_max_latency)
285	lat = pcibios_max_latency;
286	else
287	return;
288	printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
289	pci_name(dev), lat);
290	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
291	}
292
293	void __init pcibios_update_irq(struct pci_dev *dev, int irq)
294	{
295	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
296	}
297
298	char * __devinit pcibios_setup(char *str)
299	{
300	return str;
301	}
302
9ad62ec4 PM	303	static void __init
	304	pcibios_bus_report_status_early(struct pci_channel *hose,
	305	int top_bus, int current_bus,
	306	unsigned int status_mask, int warn)
	307	{
	308	unsigned int pci_devfn;
	309	u16 status;
	310	int ret;
	311
	312	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
	313	if (PCI_FUNC(pci_devfn))
	314	continue;
	315	ret = early_read_config_word(hose, top_bus, current_bus,
	316	pci_devfn, PCI_STATUS, &status);
	317	if (ret != PCIBIOS_SUCCESSFUL)
	318	continue;
	319	if (status == 0xffff)
	320	continue;
	321
	322	early_write_config_word(hose, top_bus, current_bus,
	323	pci_devfn, PCI_STATUS,
	324	status & status_mask);
	325	if (warn)
	326	printk("(%02x:%02x: %04X) ", current_bus,
	327	pci_devfn, status);
	328	}
	329	}
	330
ef407bee PM	331	/*
	332	* We can't use pci_find_device() here since we are
	333	* called from interrupt context.
	334	*/
9ad62ec4 PM	335	static void __init_refok
	336	pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
	337	int warn)
ef407bee PM	338	{
	339	struct pci_dev *dev;
	340
	341	list_for_each_entry(dev, &bus->devices, bus_list) {
	342	u16 status;
	343
	344	/*
	345	* ignore host bridge - we handle
	346	* that separately
	347	*/
	348	if (dev->bus->number == 0 && dev->devfn == 0)
	349	continue;
	350
	351	pci_read_config_word(dev, PCI_STATUS, &status);
	352	if (status == 0xffff)
	353	continue;
	354
	355	if ((status & status_mask) == 0)
	356	continue;
	357
	358	/* clear the status errors */
	359	pci_write_config_word(dev, PCI_STATUS, status & status_mask);
	360
	361	if (warn)
	362	printk("(%s: %04X) ", pci_name(dev), status);
	363	}
	364
	365	list_for_each_entry(dev, &bus->devices, bus_list)
	366	if (dev->subordinate)
	367	pcibios_bus_report_status(dev->subordinate, status_mask, warn);
	368	}
	369
9ad62ec4	370	void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
ef407bee PM	371	{
	372	struct pci_channel *hose;
	373
9ad62ec4 PM	374	for (hose = hose_head; hose; hose = hose->next) {
	375	if (unlikely(!hose->bus))
	376	pcibios_bus_report_status_early(hose, hose_head->index,
	377	hose->index, status_mask, warn);
	378	else
	379	pcibios_bus_report_status(hose->bus, status_mask, warn);
	380	}
ef407bee PM	381	}
ef407bee PM	382
35bcfffd PM	383	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	384	enum pci_mmap_state mmap_state, int write_combine)
	385	{
	386	/*
	387	* I/O space can be accessed via normal processor loads and stores on
	388	* this platform but for now we elect not to do this and portable
	389	* drivers should not do this anyway.
	390	*/
	391	if (mmap_state == pci_mmap_io)
	392	return -EINVAL;
	393
	394	/*
	395	* Ignore write-combine; for now only return uncached mappings.
	396	*/
	397	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	398
	399	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	400	vma->vm_end - vma->vm_start,
	401	vma->vm_page_prot);
	402	}
	403
15444a89 DM	404	#ifndef CONFIG_GENERIC_IOMAP
15444a89 DM	405
35bcfffd PM	406	static void __iomem ioport_map_pci(struct pci_dev dev,
	407	unsigned long port, unsigned int nr)
	408	{
	409	struct pci_channel *chan = dev->sysdata;
	410
320e68da	411	if (unlikely(!chan->io_map_base)) {
35bcfffd PM	412	chan->io_map_base = generic_io_base;
35bcfffd PM	413
320e68da PM	414	if (pci_domains_supported)
	415	panic("To avoid data corruption io_map_base MUST be "
	416	"set with multiple PCI domains.");
	417	}
	418
	419
35bcfffd PM	420	return (void __iomem *)(chan->io_map_base + port);
	421	}
	422
	423	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen)
	424	{
	425	resource_size_t start = pci_resource_start(dev, bar);
	426	resource_size_t len = pci_resource_len(dev, bar);
	427	unsigned long flags = pci_resource_flags(dev, bar);
	428
	429	if (unlikely(!len \|\| !start))
	430	return NULL;
	431	if (maxlen && len > maxlen)
	432	len = maxlen;
	433
	434	if (flags & IORESOURCE_IO)
	435	return ioport_map_pci(dev, start, len);
35bcfffd PM	436	if (flags & IORESOURCE_MEM) {
	437	if (flags & IORESOURCE_CACHEABLE)
	438	return ioremap(start, len);
35bcfffd PM	439	return ioremap_nocache(start, len);
	440	}
	441
	442	return NULL;
	443	}
	444	EXPORT_SYMBOL(pci_iomap);
	445
	446	void pci_iounmap(struct pci_dev dev, void __iomem addr)
	447	{
	448	iounmap(addr);
	449	}
	450	EXPORT_SYMBOL(pci_iounmap);
	451
15444a89 DM	452	#endif /* CONFIG_GENERIC_IOMAP */
15444a89 DM	453
35bcfffd PM	454	#ifdef CONFIG_HOTPLUG
	455	EXPORT_SYMBOL(pcibios_resource_to_bus);
	456	EXPORT_SYMBOL(pcibios_bus_to_resource);
	457	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
	458	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
	459	#endif