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1da177e4 | 1 | /* |
f30c2269 | 2 | * linux/arch/sh/boards/se/7751/pci.c |
1da177e4 LT |
3 | * |
4 | * Author: Ian DaSilva (idasilva@mvista.com) | |
5 | * | |
6 | * Highly leveraged from pci-bigsur.c, written by Dustin McIntire. | |
7 | * | |
8 | * May be copied or modified under the terms of the GNU General Public | |
9 | * License. See linux/COPYING for more information. | |
10 | * | |
11 | * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01) | |
12 | */ | |
13 | ||
1da177e4 LT |
14 | #include <linux/kernel.h> |
15 | #include <linux/types.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pci.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include "../../../drivers/pci/pci-sh7751.h" | |
22 | ||
23 | #define PCIMCR_MRSET_OFF 0xBFFFFFFF | |
24 | #define PCIMCR_RFSH_OFF 0xFFFFFFFB | |
25 | ||
26 | /* | |
27 | * Only long word accesses of the PCIC's internal local registers and the | |
28 | * configuration registers from the CPU is supported. | |
29 | */ | |
30 | #define PCIC_WRITE(x,v) writel((v), PCI_REG(x)) | |
31 | #define PCIC_READ(x) readl(PCI_REG(x)) | |
32 | ||
33 | /* | |
34 | * Description: This function sets up and initializes the pcic, sets | |
35 | * up the BARS, maps the DRAM into the address space etc, etc. | |
36 | */ | |
37 | int __init pcibios_init_platform(void) | |
38 | { | |
39 | unsigned long bcr1, wcr1, wcr2, wcr3, mcr; | |
40 | unsigned short bcr2; | |
41 | ||
42 | /* | |
43 | * Initialize the slave bus controller on the pcic. The values used | |
44 | * here should not be hardcoded, but they should be taken from the bsc | |
45 | * on the processor, to make this function as generic as possible. | |
46 | * (i.e. Another sbc may usr different SDRAM timing settings -- in order | |
47 | * for the pcic to work, its settings need to be exactly the same.) | |
48 | */ | |
49 | bcr1 = (*(volatile unsigned long*)(SH7751_BCR1)); | |
50 | bcr2 = (*(volatile unsigned short*)(SH7751_BCR2)); | |
51 | wcr1 = (*(volatile unsigned long*)(SH7751_WCR1)); | |
52 | wcr2 = (*(volatile unsigned long*)(SH7751_WCR2)); | |
53 | wcr3 = (*(volatile unsigned long*)(SH7751_WCR3)); | |
54 | mcr = (*(volatile unsigned long*)(SH7751_MCR)); | |
55 | ||
56 | bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ | |
57 | (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1; | |
58 | ||
59 | bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ | |
60 | PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */ | |
61 | PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */ | |
62 | PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */ | |
63 | PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */ | |
64 | PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */ | |
65 | mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; | |
66 | PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */ | |
67 | ||
68 | ||
69 | /* Enable all interrupts, so we know what to fix */ | |
70 | PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); | |
71 | PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); | |
72 | ||
73 | /* Set up standard PCI config registers */ | |
74 | PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ | |
75 | PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ | |
76 | PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */ | |
77 | PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */ | |
78 | PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */ | |
79 | PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */ | |
80 | PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */ | |
81 | PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */ | |
82 | PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */ | |
83 | PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */ | |
84 | ||
85 | /* Now turn it on... */ | |
86 | PCIC_WRITE(SH7751_PCICR, 0xa5000001); | |
87 | ||
88 | /* | |
89 | * Set PCIMBR and PCIIOBR here, assuming a single window | |
90 | * (16M MEM, 256K IO) is enough. If a larger space is | |
91 | * needed, the readx/writex and inx/outx functions will | |
92 | * have to do more (e.g. setting registers for each call). | |
93 | */ | |
94 | ||
95 | /* | |
96 | * Set the MBR so PCI address is one-to-one with window, | |
97 | * meaning all calls go straight through... use BUG_ON to | |
98 | * catch erroneous assumption. | |
99 | */ | |
100 | BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE); | |
101 | ||
102 | PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM); | |
103 | ||
104 | /* Set IOBR for window containing area specified in pci.h */ | |
105 | PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK)); | |
106 | ||
107 | /* All done, may as well say so... */ | |
108 | printk("SH7751 PCI: Finished initialization of the PCI controller\n"); | |
109 | ||
110 | return 1; | |
111 | } | |
112 | ||
113 | int __init pcibios_map_platform_irq(u8 slot, u8 pin) | |
114 | { | |
115 | switch (slot) { | |
116 | case 0: return 13; | |
117 | case 1: return 13; /* AMD Ethernet controller */ | |
118 | case 2: return -1; | |
119 | case 3: return -1; | |
120 | case 4: return -1; | |
121 | default: | |
122 | printk("PCI: Bad IRQ mapping request for slot %d\n", slot); | |
123 | return -1; | |
124 | } | |
125 | } | |
126 | ||
127 | static struct resource sh7751_io_resource = { | |
128 | .name = "SH7751 IO", | |
129 | .start = SH7751_PCI_IO_BASE, | |
130 | .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, | |
131 | .flags = IORESOURCE_IO | |
132 | }; | |
133 | ||
134 | static struct resource sh7751_mem_resource = { | |
135 | .name = "SH7751 mem", | |
136 | .start = SH7751_PCI_MEMORY_BASE, | |
137 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, | |
138 | .flags = IORESOURCE_MEM | |
139 | }; | |
140 | ||
141 | extern struct pci_ops sh7751_pci_ops; | |
142 | ||
143 | struct pci_channel board_pci_channels[] = { | |
144 | { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, | |
145 | { NULL, NULL, NULL, 0, 0 }, | |
146 | }; | |
147 |