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287c1297 KM |
1 | /* |
2 | * linux/arch/sh/boards/se/7724/setup.c | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * | |
6 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/platform_device.h> | |
470ef1a7 | 17 | #include <linux/mfd/sh_mobile_sdhi.h> |
287c1297 KM |
18 | #include <linux/mtd/physmap.h> |
19 | #include <linux/delay.h> | |
20 | #include <linux/smc91x.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/input.h> | |
fc1d003d | 23 | #include <linux/input/sh_keysc.h> |
9731f4a2 | 24 | #include <linux/usb/r8a66597.h> |
287c1297 KM |
25 | #include <video/sh_mobile_lcdc.h> |
26 | #include <media/sh_mobile_ceu.h> | |
3e9ad52b | 27 | #include <sound/sh_fsi.h> |
287c1297 KM |
28 | #include <asm/io.h> |
29 | #include <asm/heartbeat.h> | |
a80cad95 KM |
30 | #include <asm/sh_eth.h> |
31 | #include <asm/clock.h> | |
3b9f2952 | 32 | #include <asm/suspend.h> |
287c1297 KM |
33 | #include <cpu/sh7724.h> |
34 | #include <mach-se/mach/se7724.h> | |
35 | ||
36 | /* | |
37 | * SWx 1234 5678 | |
38 | * ------------------------------------ | |
39 | * SW31 : 1001 1100 : default | |
40 | * SW32 : 0111 1111 : use on board flash | |
41 | * | |
42 | * SW41 : abxx xxxx -> a = 0 : Analog monitor | |
43 | * 1 : Digital monitor | |
44 | * b = 0 : VGA | |
4f324311 KM |
45 | * 1 : 720p |
46 | */ | |
47 | ||
48 | /* | |
49 | * about 720p | |
50 | * | |
51 | * When you use 1280 x 720 lcdc output, | |
52 | * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz, | |
53 | * and change SW41 to use 720p | |
287c1297 KM |
54 | */ |
55 | ||
bec9fb07 KM |
56 | /* |
57 | * about sound | |
58 | * | |
59 | * This setup.c supports FSI slave mode. | |
60 | * Please change J20, J21, J22 pin to 1-2 connection. | |
61 | */ | |
62 | ||
287c1297 | 63 | /* Heartbeat */ |
a09d2831 PM |
64 | static struct resource heartbeat_resource = { |
65 | .start = PA_LED, | |
66 | .end = PA_LED, | |
67 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, | |
287c1297 KM |
68 | }; |
69 | ||
70 | static struct platform_device heartbeat_device = { | |
71 | .name = "heartbeat", | |
72 | .id = -1, | |
a09d2831 PM |
73 | .num_resources = 1, |
74 | .resource = &heartbeat_resource, | |
287c1297 KM |
75 | }; |
76 | ||
77 | /* LAN91C111 */ | |
78 | static struct smc91x_platdata smc91x_info = { | |
79 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | |
80 | }; | |
81 | ||
82 | static struct resource smc91x_eth_resources[] = { | |
83 | [0] = { | |
84 | .name = "SMC91C111" , | |
85 | .start = 0x1a300300, | |
86 | .end = 0x1a30030f, | |
87 | .flags = IORESOURCE_MEM, | |
88 | }, | |
89 | [1] = { | |
90 | .start = IRQ0_SMC, | |
91 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
92 | }, | |
93 | }; | |
94 | ||
95 | static struct platform_device smc91x_eth_device = { | |
96 | .name = "smc91x", | |
97 | .num_resources = ARRAY_SIZE(smc91x_eth_resources), | |
98 | .resource = smc91x_eth_resources, | |
99 | .dev = { | |
100 | .platform_data = &smc91x_info, | |
101 | }, | |
102 | }; | |
103 | ||
104 | /* MTD */ | |
105 | static struct mtd_partition nor_flash_partitions[] = { | |
106 | { | |
107 | .name = "uboot", | |
108 | .offset = 0, | |
109 | .size = (1 * 1024 * 1024), | |
110 | .mask_flags = MTD_WRITEABLE, /* Read-only */ | |
111 | }, { | |
112 | .name = "kernel", | |
113 | .offset = MTDPART_OFS_APPEND, | |
114 | .size = (2 * 1024 * 1024), | |
115 | }, { | |
116 | .name = "free-area", | |
117 | .offset = MTDPART_OFS_APPEND, | |
118 | .size = MTDPART_SIZ_FULL, | |
119 | }, | |
120 | }; | |
121 | ||
122 | static struct physmap_flash_data nor_flash_data = { | |
123 | .width = 2, | |
124 | .parts = nor_flash_partitions, | |
125 | .nr_parts = ARRAY_SIZE(nor_flash_partitions), | |
126 | }; | |
127 | ||
128 | static struct resource nor_flash_resources[] = { | |
129 | [0] = { | |
130 | .name = "NOR Flash", | |
131 | .start = 0x00000000, | |
132 | .end = 0x01ffffff, | |
133 | .flags = IORESOURCE_MEM, | |
134 | } | |
135 | }; | |
136 | ||
137 | static struct platform_device nor_flash_device = { | |
138 | .name = "physmap-flash", | |
139 | .resource = nor_flash_resources, | |
140 | .num_resources = ARRAY_SIZE(nor_flash_resources), | |
141 | .dev = { | |
142 | .platform_data = &nor_flash_data, | |
143 | }, | |
144 | }; | |
145 | ||
146 | /* LCDC */ | |
44432407 GL |
147 | const static struct fb_videomode lcdc_720p_modes[] = { |
148 | { | |
149 | .name = "LB070WV1", | |
150 | .sync = 0, /* hsync and vsync are active low */ | |
46f12936 GL |
151 | .xres = 1280, |
152 | .yres = 720, | |
153 | .left_margin = 220, | |
154 | .right_margin = 110, | |
155 | .hsync_len = 40, | |
156 | .upper_margin = 20, | |
157 | .lower_margin = 5, | |
158 | .vsync_len = 5, | |
44432407 GL |
159 | }, |
160 | }; | |
161 | ||
162 | const static struct fb_videomode lcdc_vga_modes[] = { | |
163 | { | |
164 | .name = "LB070WV1", | |
165 | .sync = 0, /* hsync and vsync are active low */ | |
46f12936 GL |
166 | .xres = 640, |
167 | .yres = 480, | |
168 | .left_margin = 105, | |
169 | .right_margin = 50, | |
170 | .hsync_len = 96, | |
171 | .upper_margin = 33, | |
172 | .lower_margin = 10, | |
173 | .vsync_len = 2, | |
44432407 GL |
174 | }, |
175 | }; | |
176 | ||
287c1297 KM |
177 | static struct sh_mobile_lcdc_info lcdc_info = { |
178 | .clock_source = LCDC_CLK_EXTERNAL, | |
179 | .ch[0] = { | |
180 | .chan = LCDC_CHAN_MAINLCD, | |
181 | .bpp = 16, | |
182 | .clock_divider = 1, | |
287c1297 KM |
183 | .lcd_size_cfg = { /* 7.0 inch */ |
184 | .width = 152, | |
185 | .height = 91, | |
186 | }, | |
187 | .board_cfg = { | |
188 | }, | |
189 | } | |
190 | }; | |
191 | ||
192 | static struct resource lcdc_resources[] = { | |
193 | [0] = { | |
194 | .name = "LCDC", | |
195 | .start = 0xfe940000, | |
a6f15ade | 196 | .end = 0xfe942fff, |
287c1297 KM |
197 | .flags = IORESOURCE_MEM, |
198 | }, | |
199 | [1] = { | |
200 | .start = 106, | |
201 | .flags = IORESOURCE_IRQ, | |
202 | }, | |
203 | }; | |
204 | ||
205 | static struct platform_device lcdc_device = { | |
206 | .name = "sh_mobile_lcdc_fb", | |
207 | .num_resources = ARRAY_SIZE(lcdc_resources), | |
208 | .resource = lcdc_resources, | |
209 | .dev = { | |
210 | .platform_data = &lcdc_info, | |
211 | }, | |
df47cd09 MD |
212 | .archdata = { |
213 | .hwblk_id = HWBLK_LCDC, | |
214 | }, | |
287c1297 KM |
215 | }; |
216 | ||
217 | /* CEU0 */ | |
218 | static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { | |
219 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, | |
220 | }; | |
221 | ||
222 | static struct resource ceu0_resources[] = { | |
223 | [0] = { | |
224 | .name = "CEU0", | |
225 | .start = 0xfe910000, | |
226 | .end = 0xfe91009f, | |
227 | .flags = IORESOURCE_MEM, | |
228 | }, | |
229 | [1] = { | |
230 | .start = 52, | |
231 | .flags = IORESOURCE_IRQ, | |
232 | }, | |
233 | [2] = { | |
234 | /* place holder for contiguous memory */ | |
235 | }, | |
236 | }; | |
237 | ||
238 | static struct platform_device ceu0_device = { | |
239 | .name = "sh_mobile_ceu", | |
240 | .id = 0, /* "ceu0" clock */ | |
241 | .num_resources = ARRAY_SIZE(ceu0_resources), | |
242 | .resource = ceu0_resources, | |
243 | .dev = { | |
244 | .platform_data = &sh_mobile_ceu0_info, | |
245 | }, | |
df47cd09 MD |
246 | .archdata = { |
247 | .hwblk_id = HWBLK_CEU0, | |
248 | }, | |
287c1297 KM |
249 | }; |
250 | ||
251 | /* CEU1 */ | |
252 | static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { | |
253 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, | |
254 | }; | |
255 | ||
256 | static struct resource ceu1_resources[] = { | |
257 | [0] = { | |
258 | .name = "CEU1", | |
259 | .start = 0xfe914000, | |
260 | .end = 0xfe91409f, | |
261 | .flags = IORESOURCE_MEM, | |
262 | }, | |
263 | [1] = { | |
264 | .start = 63, | |
265 | .flags = IORESOURCE_IRQ, | |
266 | }, | |
267 | [2] = { | |
268 | /* place holder for contiguous memory */ | |
269 | }, | |
270 | }; | |
271 | ||
272 | static struct platform_device ceu1_device = { | |
273 | .name = "sh_mobile_ceu", | |
274 | .id = 1, /* "ceu1" clock */ | |
275 | .num_resources = ARRAY_SIZE(ceu1_resources), | |
276 | .resource = ceu1_resources, | |
277 | .dev = { | |
278 | .platform_data = &sh_mobile_ceu1_info, | |
279 | }, | |
df47cd09 MD |
280 | .archdata = { |
281 | .hwblk_id = HWBLK_CEU1, | |
282 | }, | |
287c1297 KM |
283 | }; |
284 | ||
3e9ad52b KM |
285 | /* FSI */ |
286 | /* | |
287 | * FSI-A use external clock which came from ak464x. | |
288 | * So, we should change parent of fsi | |
289 | */ | |
290 | #define FCLKACR 0xa4150008 | |
291 | static void fsimck_init(struct clk *clk) | |
292 | { | |
9d56dd3b | 293 | u32 status = __raw_readl(clk->enable_reg); |
3e9ad52b KM |
294 | |
295 | /* use external clock */ | |
296 | status &= ~0x000000ff; | |
297 | status |= 0x00000080; | |
9d56dd3b | 298 | __raw_writel(status, clk->enable_reg); |
3e9ad52b KM |
299 | } |
300 | ||
301 | static struct clk_ops fsimck_clk_ops = { | |
302 | .init = fsimck_init, | |
303 | }; | |
304 | ||
305 | static struct clk fsimcka_clk = { | |
3e9ad52b KM |
306 | .ops = &fsimck_clk_ops, |
307 | .enable_reg = (void __iomem *)FCLKACR, | |
308 | .rate = 0, /* unknown */ | |
309 | }; | |
310 | ||
bec9fb07 | 311 | /* change J20, J21, J22 pin to 1-2 connection to use slave mode */ |
560526f1 | 312 | static struct sh_fsi_platform_info fsi_info = { |
3e9ad52b KM |
313 | .porta_flags = SH_FSI_BRS_INV | |
314 | SH_FSI_OUT_SLAVE_MODE | | |
315 | SH_FSI_IN_SLAVE_MODE | | |
316 | SH_FSI_OFMT(PCM) | | |
317 | SH_FSI_IFMT(PCM), | |
318 | }; | |
319 | ||
320 | static struct resource fsi_resources[] = { | |
321 | [0] = { | |
322 | .name = "FSI", | |
323 | .start = 0xFE3C0000, | |
324 | .end = 0xFE3C021d, | |
325 | .flags = IORESOURCE_MEM, | |
326 | }, | |
327 | [1] = { | |
328 | .start = 108, | |
329 | .flags = IORESOURCE_IRQ, | |
330 | }, | |
331 | }; | |
332 | ||
333 | static struct platform_device fsi_device = { | |
334 | .name = "sh_fsi", | |
335 | .id = 0, | |
336 | .num_resources = ARRAY_SIZE(fsi_resources), | |
337 | .resource = fsi_resources, | |
338 | .dev = { | |
339 | .platform_data = &fsi_info, | |
340 | }, | |
d53bd80c KM |
341 | .archdata = { |
342 | .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */ | |
343 | }, | |
3e9ad52b KM |
344 | }; |
345 | ||
9747e78b | 346 | /* KEYSC in SoC (Needs SW33-2 set to ON) */ |
287c1297 KM |
347 | static struct sh_keysc_info keysc_info = { |
348 | .mode = SH_KEYSC_MODE_1, | |
29463c28 | 349 | .scan_timing = 3, |
287c1297 KM |
350 | .delay = 50, |
351 | .keycodes = { | |
352 | KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, | |
353 | KEY_6, KEY_7, KEY_8, KEY_9, KEY_A, | |
354 | KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, | |
355 | KEY_G, KEY_H, KEY_I, KEY_K, KEY_L, | |
356 | KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q, | |
357 | KEY_R, KEY_S, KEY_T, KEY_U, KEY_V, | |
358 | }, | |
359 | }; | |
360 | ||
361 | static struct resource keysc_resources[] = { | |
362 | [0] = { | |
9747e78b MD |
363 | .name = "KEYSC", |
364 | .start = 0x044b0000, | |
365 | .end = 0x044b000f, | |
287c1297 KM |
366 | .flags = IORESOURCE_MEM, |
367 | }, | |
368 | [1] = { | |
9747e78b | 369 | .start = 79, |
287c1297 KM |
370 | .flags = IORESOURCE_IRQ, |
371 | }, | |
372 | }; | |
373 | ||
374 | static struct platform_device keysc_device = { | |
375 | .name = "sh_keysc", | |
376 | .id = 0, /* "keysc0" clock */ | |
377 | .num_resources = ARRAY_SIZE(keysc_resources), | |
378 | .resource = keysc_resources, | |
379 | .dev = { | |
380 | .platform_data = &keysc_info, | |
381 | }, | |
df47cd09 MD |
382 | .archdata = { |
383 | .hwblk_id = HWBLK_KEYSC, | |
384 | }, | |
287c1297 KM |
385 | }; |
386 | ||
a80cad95 KM |
387 | /* SH Eth */ |
388 | static struct resource sh_eth_resources[] = { | |
389 | [0] = { | |
390 | .start = SH_ETH_ADDR, | |
391 | .end = SH_ETH_ADDR + 0x1FC, | |
392 | .flags = IORESOURCE_MEM, | |
393 | }, | |
394 | [1] = { | |
395 | .start = 91, | |
396 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
397 | }, | |
398 | }; | |
399 | ||
560526f1 | 400 | static struct sh_eth_plat_data sh_eth_plat = { |
a80cad95 KM |
401 | .phy = 0x1f, /* SMSC LAN8187 */ |
402 | .edmac_endian = EDMAC_LITTLE_ENDIAN, | |
403 | }; | |
404 | ||
405 | static struct platform_device sh_eth_device = { | |
406 | .name = "sh-eth", | |
407 | .id = 0, | |
408 | .dev = { | |
409 | .platform_data = &sh_eth_plat, | |
410 | }, | |
411 | .num_resources = ARRAY_SIZE(sh_eth_resources), | |
412 | .resource = sh_eth_resources, | |
df47cd09 MD |
413 | .archdata = { |
414 | .hwblk_id = HWBLK_ETHER, | |
415 | }, | |
a80cad95 KM |
416 | }; |
417 | ||
9731f4a2 | 418 | static struct r8a66597_platdata sh7724_usb0_host_data = { |
719a72b7 | 419 | .on_chip = 1, |
9731f4a2 MD |
420 | }; |
421 | ||
422 | static struct resource sh7724_usb0_host_resources[] = { | |
423 | [0] = { | |
424 | .start = 0xa4d80000, | |
1bc265d0 | 425 | .end = 0xa4d80124 - 1, |
9731f4a2 MD |
426 | .flags = IORESOURCE_MEM, |
427 | }, | |
428 | [1] = { | |
429 | .start = 65, | |
430 | .end = 65, | |
431 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | |
432 | }, | |
433 | }; | |
434 | ||
435 | static struct platform_device sh7724_usb0_host_device = { | |
436 | .name = "r8a66597_hcd", | |
437 | .id = 0, | |
438 | .dev = { | |
439 | .dma_mask = NULL, /* not use dma */ | |
440 | .coherent_dma_mask = 0xffffffff, | |
441 | .platform_data = &sh7724_usb0_host_data, | |
442 | }, | |
443 | .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), | |
444 | .resource = sh7724_usb0_host_resources, | |
df47cd09 MD |
445 | .archdata = { |
446 | .hwblk_id = HWBLK_USB0, | |
447 | }, | |
9731f4a2 MD |
448 | }; |
449 | ||
f8f8c079 MD |
450 | static struct r8a66597_platdata sh7724_usb1_gadget_data = { |
451 | .on_chip = 1, | |
452 | }; | |
453 | ||
454 | static struct resource sh7724_usb1_gadget_resources[] = { | |
455 | [0] = { | |
456 | .start = 0xa4d90000, | |
457 | .end = 0xa4d90123, | |
458 | .flags = IORESOURCE_MEM, | |
459 | }, | |
460 | [1] = { | |
461 | .start = 66, | |
462 | .end = 66, | |
463 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | |
464 | }, | |
465 | }; | |
466 | ||
467 | static struct platform_device sh7724_usb1_gadget_device = { | |
468 | .name = "r8a66597_udc", | |
469 | .id = 1, /* USB1 */ | |
470 | .dev = { | |
471 | .dma_mask = NULL, /* not use dma */ | |
472 | .coherent_dma_mask = 0xffffffff, | |
473 | .platform_data = &sh7724_usb1_gadget_data, | |
474 | }, | |
475 | .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources), | |
476 | .resource = sh7724_usb1_gadget_resources, | |
477 | }; | |
478 | ||
0f79af60 MD |
479 | static struct resource sdhi0_cn7_resources[] = { |
480 | [0] = { | |
481 | .name = "SDHI0", | |
482 | .start = 0x04ce0000, | |
483 | .end = 0x04ce01ff, | |
484 | .flags = IORESOURCE_MEM, | |
485 | }, | |
486 | [1] = { | |
3844eadc | 487 | .start = 100, |
0f79af60 MD |
488 | .flags = IORESOURCE_IRQ, |
489 | }, | |
490 | }; | |
491 | ||
470ef1a7 GL |
492 | static struct sh_mobile_sdhi_info sh7724_sdhi0_data = { |
493 | .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, | |
494 | .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, | |
495 | }; | |
496 | ||
0f79af60 MD |
497 | static struct platform_device sdhi0_cn7_device = { |
498 | .name = "sh_mobile_sdhi", | |
5b380ec1 | 499 | .id = 0, |
0f79af60 MD |
500 | .num_resources = ARRAY_SIZE(sdhi0_cn7_resources), |
501 | .resource = sdhi0_cn7_resources, | |
470ef1a7 GL |
502 | .dev = { |
503 | .platform_data = &sh7724_sdhi0_data, | |
504 | }, | |
0f79af60 MD |
505 | .archdata = { |
506 | .hwblk_id = HWBLK_SDHI0, | |
507 | }, | |
508 | }; | |
509 | ||
5b380ec1 MD |
510 | static struct resource sdhi1_cn8_resources[] = { |
511 | [0] = { | |
512 | .name = "SDHI1", | |
513 | .start = 0x04cf0000, | |
514 | .end = 0x04cf01ff, | |
515 | .flags = IORESOURCE_MEM, | |
516 | }, | |
517 | [1] = { | |
3844eadc | 518 | .start = 23, |
5b380ec1 MD |
519 | .flags = IORESOURCE_IRQ, |
520 | }, | |
521 | }; | |
522 | ||
470ef1a7 GL |
523 | static struct sh_mobile_sdhi_info sh7724_sdhi1_data = { |
524 | .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, | |
525 | .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, | |
526 | }; | |
527 | ||
5b380ec1 MD |
528 | static struct platform_device sdhi1_cn8_device = { |
529 | .name = "sh_mobile_sdhi", | |
530 | .id = 1, | |
531 | .num_resources = ARRAY_SIZE(sdhi1_cn8_resources), | |
532 | .resource = sdhi1_cn8_resources, | |
470ef1a7 GL |
533 | .dev = { |
534 | .platform_data = &sh7724_sdhi1_data, | |
535 | }, | |
5b380ec1 MD |
536 | .archdata = { |
537 | .hwblk_id = HWBLK_SDHI1, | |
538 | }, | |
539 | }; | |
540 | ||
bbb892aa KM |
541 | /* IrDA */ |
542 | static struct resource irda_resources[] = { | |
543 | [0] = { | |
544 | .name = "IrDA", | |
545 | .start = 0xA45D0000, | |
546 | .end = 0xA45D0049, | |
547 | .flags = IORESOURCE_MEM, | |
548 | }, | |
549 | [1] = { | |
550 | .start = 20, | |
551 | .flags = IORESOURCE_IRQ, | |
552 | }, | |
553 | }; | |
554 | ||
555 | static struct platform_device irda_device = { | |
556 | .name = "sh_sir", | |
557 | .num_resources = ARRAY_SIZE(irda_resources), | |
558 | .resource = irda_resources, | |
559 | }; | |
560 | ||
2d151248 GL |
561 | #include <media/ak881x.h> |
562 | #include <media/sh_vou.h> | |
563 | ||
560526f1 | 564 | static struct ak881x_pdata ak881x_pdata = { |
2d151248 GL |
565 | .flags = AK881X_IF_MODE_SLAVE, |
566 | }; | |
567 | ||
568 | static struct i2c_board_info ak8813 = { | |
569 | /* With open J18 jumper address is 0x21 */ | |
570 | I2C_BOARD_INFO("ak8813", 0x20), | |
571 | .platform_data = &ak881x_pdata, | |
572 | }; | |
573 | ||
560526f1 | 574 | static struct sh_vou_pdata sh_vou_pdata = { |
2d151248 GL |
575 | .bus_fmt = SH_VOU_BUS_8BIT, |
576 | .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, | |
577 | .board_info = &ak8813, | |
578 | .i2c_adap = 0, | |
2d151248 GL |
579 | }; |
580 | ||
581 | static struct resource sh_vou_resources[] = { | |
582 | [0] = { | |
583 | .start = 0xfe960000, | |
584 | .end = 0xfe962043, | |
585 | .flags = IORESOURCE_MEM, | |
586 | }, | |
587 | [1] = { | |
588 | .start = 55, | |
589 | .flags = IORESOURCE_IRQ, | |
590 | }, | |
591 | }; | |
592 | ||
593 | static struct platform_device vou_device = { | |
594 | .name = "sh-vou", | |
595 | .id = -1, | |
596 | .num_resources = ARRAY_SIZE(sh_vou_resources), | |
597 | .resource = sh_vou_resources, | |
598 | .dev = { | |
599 | .platform_data = &sh_vou_pdata, | |
600 | }, | |
601 | .archdata = { | |
602 | .hwblk_id = HWBLK_VOU, | |
603 | }, | |
604 | }; | |
605 | ||
287c1297 KM |
606 | static struct platform_device *ms7724se_devices[] __initdata = { |
607 | &heartbeat_device, | |
608 | &smc91x_eth_device, | |
609 | &lcdc_device, | |
610 | &nor_flash_device, | |
611 | &ceu0_device, | |
612 | &ceu1_device, | |
613 | &keysc_device, | |
a80cad95 | 614 | &sh_eth_device, |
9731f4a2 | 615 | &sh7724_usb0_host_device, |
f8f8c079 | 616 | &sh7724_usb1_gadget_device, |
3e9ad52b | 617 | &fsi_device, |
0f79af60 | 618 | &sdhi0_cn7_device, |
5b380ec1 | 619 | &sdhi1_cn8_device, |
bbb892aa | 620 | &irda_device, |
2d151248 | 621 | &vou_device, |
287c1297 KM |
622 | }; |
623 | ||
9f815a17 KM |
624 | /* I2C device */ |
625 | static struct i2c_board_info i2c0_devices[] = { | |
626 | { | |
627 | I2C_BOARD_INFO("ak4642", 0x12), | |
628 | }, | |
629 | }; | |
630 | ||
a80cad95 KM |
631 | #define EEPROM_OP 0xBA206000 |
632 | #define EEPROM_ADR 0xBA206004 | |
633 | #define EEPROM_DATA 0xBA20600C | |
634 | #define EEPROM_STAT 0xBA206010 | |
635 | #define EEPROM_STRT 0xBA206014 | |
636 | static int __init sh_eth_is_eeprom_ready(void) | |
637 | { | |
638 | int t = 10000; | |
639 | ||
640 | while (t--) { | |
9d56dd3b | 641 | if (!__raw_readw(EEPROM_STAT)) |
a80cad95 | 642 | return 1; |
c718aff2 | 643 | udelay(1); |
a80cad95 KM |
644 | } |
645 | ||
646 | printk(KERN_ERR "ms7724se can not access to eeprom\n"); | |
647 | return 0; | |
648 | } | |
649 | ||
650 | static void __init sh_eth_init(void) | |
651 | { | |
652 | int i; | |
8013cc9a | 653 | u16 mac; |
a80cad95 KM |
654 | |
655 | /* check EEPROM status */ | |
656 | if (!sh_eth_is_eeprom_ready()) | |
657 | return; | |
658 | ||
659 | /* read MAC addr from EEPROM */ | |
660 | for (i = 0 ; i < 3 ; i++) { | |
9d56dd3b PM |
661 | __raw_writew(0x0, EEPROM_OP); /* read */ |
662 | __raw_writew(i*2, EEPROM_ADR); | |
663 | __raw_writew(0x1, EEPROM_STRT); | |
a80cad95 KM |
664 | if (!sh_eth_is_eeprom_ready()) |
665 | return; | |
666 | ||
9d56dd3b | 667 | mac = __raw_readw(EEPROM_DATA); |
8013cc9a MD |
668 | sh_eth_plat.mac_addr[i << 1] = mac & 0xff; |
669 | sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8; | |
a80cad95 | 670 | } |
a80cad95 KM |
671 | } |
672 | ||
287c1297 KM |
673 | #define SW4140 0xBA201000 |
674 | #define FPGA_OUT 0xBA200400 | |
675 | #define PORT_HIZA 0xA4050158 | |
9731f4a2 | 676 | #define PORT_MSELCRB 0xA4050182 |
287c1297 KM |
677 | |
678 | #define SW41_A 0x0100 | |
679 | #define SW41_B 0x0200 | |
680 | #define SW41_C 0x0400 | |
681 | #define SW41_D 0x0800 | |
682 | #define SW41_E 0x1000 | |
683 | #define SW41_F 0x2000 | |
684 | #define SW41_G 0x4000 | |
685 | #define SW41_H 0x8000 | |
9731f4a2 | 686 | |
3b9f2952 MD |
687 | extern char ms7724se_sdram_enter_start; |
688 | extern char ms7724se_sdram_enter_end; | |
689 | extern char ms7724se_sdram_leave_start; | |
690 | extern char ms7724se_sdram_leave_end; | |
691 | ||
9f815a17 KM |
692 | |
693 | static int __init arch_setup(void) | |
694 | { | |
695 | /* enable I2C device */ | |
696 | i2c_register_board_info(0, i2c0_devices, | |
697 | ARRAY_SIZE(i2c0_devices)); | |
698 | return 0; | |
699 | } | |
700 | arch_initcall(arch_setup); | |
701 | ||
287c1297 KM |
702 | static int __init devices_setup(void) |
703 | { | |
9d56dd3b | 704 | u16 sw = __raw_readw(SW4140); /* select camera, monitor */ |
16afc9fb | 705 | struct clk *clk; |
2d151248 | 706 | u16 fpga_out; |
287c1297 | 707 | |
3b9f2952 | 708 | /* register board specific self-refresh code */ |
b67cf284 MD |
709 | sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | |
710 | SUSP_SH_RSTANDBY, | |
3b9f2952 MD |
711 | &ms7724se_sdram_enter_start, |
712 | &ms7724se_sdram_enter_end, | |
713 | &ms7724se_sdram_leave_start, | |
714 | &ms7724se_sdram_leave_end); | |
287c1297 | 715 | /* Reset Release */ |
2d151248 GL |
716 | fpga_out = __raw_readw(FPGA_OUT); |
717 | /* bit4: NTSC_PDN, bit5: NTSC_RESET */ | |
718 | fpga_out &= ~((1 << 1) | /* LAN */ | |
719 | (1 << 4) | /* AK8813 PDN */ | |
720 | (1 << 5) | /* AK8813 RESET */ | |
721 | (1 << 6) | /* VIDEO DAC */ | |
722 | (1 << 7) | /* AK4643 */ | |
723 | (1 << 8) | /* IrDA */ | |
724 | (1 << 12) | /* USB0 */ | |
725 | (1 << 14)); /* RMII */ | |
726 | __raw_writew(fpga_out | (1 << 4), FPGA_OUT); | |
727 | ||
728 | udelay(10); | |
729 | ||
730 | /* AK8813 RESET */ | |
731 | __raw_writew(fpga_out | (1 << 5), FPGA_OUT); | |
732 | ||
733 | udelay(10); | |
734 | ||
735 | __raw_writew(fpga_out, FPGA_OUT); | |
287c1297 | 736 | |
9731f4a2 | 737 | /* turn on USB clocks, use external clock */ |
9d56dd3b | 738 | __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); |
9731f4a2 | 739 | |
7766e16b MD |
740 | /* Let LED9 show STATUS2 */ |
741 | gpio_request(GPIO_FN_STATUS2, NULL); | |
742 | ||
743 | /* Lit LED10 show STATUS0 */ | |
744 | gpio_request(GPIO_FN_STATUS0, NULL); | |
745 | ||
746 | /* Lit LED11 show PDSTATUS */ | |
747 | gpio_request(GPIO_FN_PDSTATUS, NULL); | |
7766e16b | 748 | |
9731f4a2 | 749 | /* enable USB0 port */ |
9d56dd3b | 750 | __raw_writew(0x0600, 0xa40501d4); |
9731f4a2 | 751 | |
f8f8c079 | 752 | /* enable USB1 port */ |
9d56dd3b | 753 | __raw_writew(0x0600, 0xa4050192); |
f8f8c079 | 754 | |
287c1297 KM |
755 | /* enable IRQ 0,1,2 */ |
756 | gpio_request(GPIO_FN_INTC_IRQ0, NULL); | |
757 | gpio_request(GPIO_FN_INTC_IRQ1, NULL); | |
758 | gpio_request(GPIO_FN_INTC_IRQ2, NULL); | |
759 | ||
760 | /* enable SCIFA3 */ | |
761 | gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); | |
762 | gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); | |
763 | gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); | |
764 | gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); | |
765 | gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); | |
766 | ||
767 | /* enable LCDC */ | |
768 | gpio_request(GPIO_FN_LCDD23, NULL); | |
769 | gpio_request(GPIO_FN_LCDD22, NULL); | |
770 | gpio_request(GPIO_FN_LCDD21, NULL); | |
771 | gpio_request(GPIO_FN_LCDD20, NULL); | |
772 | gpio_request(GPIO_FN_LCDD19, NULL); | |
773 | gpio_request(GPIO_FN_LCDD18, NULL); | |
774 | gpio_request(GPIO_FN_LCDD17, NULL); | |
775 | gpio_request(GPIO_FN_LCDD16, NULL); | |
776 | gpio_request(GPIO_FN_LCDD15, NULL); | |
777 | gpio_request(GPIO_FN_LCDD14, NULL); | |
778 | gpio_request(GPIO_FN_LCDD13, NULL); | |
779 | gpio_request(GPIO_FN_LCDD12, NULL); | |
780 | gpio_request(GPIO_FN_LCDD11, NULL); | |
781 | gpio_request(GPIO_FN_LCDD10, NULL); | |
782 | gpio_request(GPIO_FN_LCDD9, NULL); | |
783 | gpio_request(GPIO_FN_LCDD8, NULL); | |
784 | gpio_request(GPIO_FN_LCDD7, NULL); | |
785 | gpio_request(GPIO_FN_LCDD6, NULL); | |
786 | gpio_request(GPIO_FN_LCDD5, NULL); | |
787 | gpio_request(GPIO_FN_LCDD4, NULL); | |
788 | gpio_request(GPIO_FN_LCDD3, NULL); | |
789 | gpio_request(GPIO_FN_LCDD2, NULL); | |
790 | gpio_request(GPIO_FN_LCDD1, NULL); | |
791 | gpio_request(GPIO_FN_LCDD0, NULL); | |
792 | gpio_request(GPIO_FN_LCDDISP, NULL); | |
793 | gpio_request(GPIO_FN_LCDHSYN, NULL); | |
794 | gpio_request(GPIO_FN_LCDDCK, NULL); | |
795 | gpio_request(GPIO_FN_LCDVSYN, NULL); | |
796 | gpio_request(GPIO_FN_LCDDON, NULL); | |
797 | gpio_request(GPIO_FN_LCDVEPWC, NULL); | |
798 | gpio_request(GPIO_FN_LCDVCPWC, NULL); | |
799 | gpio_request(GPIO_FN_LCDRD, NULL); | |
800 | gpio_request(GPIO_FN_LCDLCLK, NULL); | |
9d56dd3b | 801 | __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); |
287c1297 KM |
802 | |
803 | /* enable CEU0 */ | |
804 | gpio_request(GPIO_FN_VIO0_D15, NULL); | |
805 | gpio_request(GPIO_FN_VIO0_D14, NULL); | |
806 | gpio_request(GPIO_FN_VIO0_D13, NULL); | |
807 | gpio_request(GPIO_FN_VIO0_D12, NULL); | |
808 | gpio_request(GPIO_FN_VIO0_D11, NULL); | |
809 | gpio_request(GPIO_FN_VIO0_D10, NULL); | |
810 | gpio_request(GPIO_FN_VIO0_D9, NULL); | |
811 | gpio_request(GPIO_FN_VIO0_D8, NULL); | |
812 | gpio_request(GPIO_FN_VIO0_D7, NULL); | |
813 | gpio_request(GPIO_FN_VIO0_D6, NULL); | |
814 | gpio_request(GPIO_FN_VIO0_D5, NULL); | |
815 | gpio_request(GPIO_FN_VIO0_D4, NULL); | |
816 | gpio_request(GPIO_FN_VIO0_D3, NULL); | |
817 | gpio_request(GPIO_FN_VIO0_D2, NULL); | |
818 | gpio_request(GPIO_FN_VIO0_D1, NULL); | |
819 | gpio_request(GPIO_FN_VIO0_D0, NULL); | |
820 | gpio_request(GPIO_FN_VIO0_VD, NULL); | |
821 | gpio_request(GPIO_FN_VIO0_CLK, NULL); | |
822 | gpio_request(GPIO_FN_VIO0_FLD, NULL); | |
823 | gpio_request(GPIO_FN_VIO0_HD, NULL); | |
84f7597c | 824 | platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); |
287c1297 KM |
825 | |
826 | /* enable CEU1 */ | |
827 | gpio_request(GPIO_FN_VIO1_D7, NULL); | |
828 | gpio_request(GPIO_FN_VIO1_D6, NULL); | |
829 | gpio_request(GPIO_FN_VIO1_D5, NULL); | |
830 | gpio_request(GPIO_FN_VIO1_D4, NULL); | |
831 | gpio_request(GPIO_FN_VIO1_D3, NULL); | |
832 | gpio_request(GPIO_FN_VIO1_D2, NULL); | |
833 | gpio_request(GPIO_FN_VIO1_D1, NULL); | |
834 | gpio_request(GPIO_FN_VIO1_D0, NULL); | |
835 | gpio_request(GPIO_FN_VIO1_FLD, NULL); | |
836 | gpio_request(GPIO_FN_VIO1_HD, NULL); | |
837 | gpio_request(GPIO_FN_VIO1_VD, NULL); | |
838 | gpio_request(GPIO_FN_VIO1_CLK, NULL); | |
84f7597c | 839 | platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); |
287c1297 KM |
840 | |
841 | /* KEYSC */ | |
842 | gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); | |
843 | gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); | |
844 | gpio_request(GPIO_FN_KEYIN4, NULL); | |
845 | gpio_request(GPIO_FN_KEYIN3, NULL); | |
846 | gpio_request(GPIO_FN_KEYIN2, NULL); | |
847 | gpio_request(GPIO_FN_KEYIN1, NULL); | |
848 | gpio_request(GPIO_FN_KEYIN0, NULL); | |
849 | gpio_request(GPIO_FN_KEYOUT3, NULL); | |
850 | gpio_request(GPIO_FN_KEYOUT2, NULL); | |
851 | gpio_request(GPIO_FN_KEYOUT1, NULL); | |
852 | gpio_request(GPIO_FN_KEYOUT0, NULL); | |
853 | ||
3e9ad52b KM |
854 | /* enable FSI */ |
855 | gpio_request(GPIO_FN_FSIMCKB, NULL); | |
856 | gpio_request(GPIO_FN_FSIMCKA, NULL); | |
857 | gpio_request(GPIO_FN_FSIOASD, NULL); | |
858 | gpio_request(GPIO_FN_FSIIABCK, NULL); | |
859 | gpio_request(GPIO_FN_FSIIALRCK, NULL); | |
860 | gpio_request(GPIO_FN_FSIOABCK, NULL); | |
861 | gpio_request(GPIO_FN_FSIOALRCK, NULL); | |
862 | gpio_request(GPIO_FN_CLKAUDIOAO, NULL); | |
863 | gpio_request(GPIO_FN_FSIIBSD, NULL); | |
864 | gpio_request(GPIO_FN_FSIOBSD, NULL); | |
865 | gpio_request(GPIO_FN_FSIIBBCK, NULL); | |
866 | gpio_request(GPIO_FN_FSIIBLRCK, NULL); | |
867 | gpio_request(GPIO_FN_FSIOBBCK, NULL); | |
868 | gpio_request(GPIO_FN_FSIOBLRCK, NULL); | |
869 | gpio_request(GPIO_FN_CLKAUDIOBO, NULL); | |
870 | gpio_request(GPIO_FN_FSIIASD, NULL); | |
871 | ||
16afc9fb KM |
872 | /* set SPU2 clock to 83.4 MHz */ |
873 | clk = clk_get(NULL, "spu_clk"); | |
03c5ecd1 KM |
874 | if (clk) { |
875 | clk_set_rate(clk, clk_round_rate(clk, 83333333)); | |
876 | clk_put(clk); | |
877 | } | |
16afc9fb | 878 | |
3e9ad52b | 879 | /* change parent of FSI A */ |
16afc9fb | 880 | clk = clk_get(NULL, "fsia_clk"); |
03c5ecd1 KM |
881 | if (clk) { |
882 | clk_register(&fsimcka_clk); | |
883 | clk_set_parent(clk, &fsimcka_clk); | |
884 | clk_set_rate(clk, 11000); | |
885 | clk_set_rate(&fsimcka_clk, 11000); | |
886 | clk_put(clk); | |
887 | } | |
3e9ad52b | 888 | |
0f79af60 MD |
889 | /* SDHI0 connected to cn7 */ |
890 | gpio_request(GPIO_FN_SDHI0CD, NULL); | |
891 | gpio_request(GPIO_FN_SDHI0WP, NULL); | |
892 | gpio_request(GPIO_FN_SDHI0D3, NULL); | |
893 | gpio_request(GPIO_FN_SDHI0D2, NULL); | |
894 | gpio_request(GPIO_FN_SDHI0D1, NULL); | |
895 | gpio_request(GPIO_FN_SDHI0D0, NULL); | |
896 | gpio_request(GPIO_FN_SDHI0CMD, NULL); | |
897 | gpio_request(GPIO_FN_SDHI0CLK, NULL); | |
898 | ||
5b380ec1 MD |
899 | /* SDHI1 connected to cn8 */ |
900 | gpio_request(GPIO_FN_SDHI1CD, NULL); | |
901 | gpio_request(GPIO_FN_SDHI1WP, NULL); | |
902 | gpio_request(GPIO_FN_SDHI1D3, NULL); | |
903 | gpio_request(GPIO_FN_SDHI1D2, NULL); | |
904 | gpio_request(GPIO_FN_SDHI1D1, NULL); | |
905 | gpio_request(GPIO_FN_SDHI1D0, NULL); | |
906 | gpio_request(GPIO_FN_SDHI1CMD, NULL); | |
907 | gpio_request(GPIO_FN_SDHI1CLK, NULL); | |
908 | ||
bbb892aa KM |
909 | /* enable IrDA */ |
910 | gpio_request(GPIO_FN_IRDA_OUT, NULL); | |
911 | gpio_request(GPIO_FN_IRDA_IN, NULL); | |
912 | ||
a80cad95 KM |
913 | /* |
914 | * enable SH-Eth | |
915 | * | |
916 | * please remove J33 pin from your board !! | |
917 | * | |
918 | * ms7724 board should not use GPIO_FN_LNKSTA pin | |
919 | * So, This time PTX5 is set to input pin | |
920 | */ | |
921 | gpio_request(GPIO_FN_RMII_RXD0, NULL); | |
922 | gpio_request(GPIO_FN_RMII_RXD1, NULL); | |
923 | gpio_request(GPIO_FN_RMII_TXD0, NULL); | |
924 | gpio_request(GPIO_FN_RMII_TXD1, NULL); | |
925 | gpio_request(GPIO_FN_RMII_REF_CLK, NULL); | |
926 | gpio_request(GPIO_FN_RMII_TX_EN, NULL); | |
927 | gpio_request(GPIO_FN_RMII_RX_ER, NULL); | |
928 | gpio_request(GPIO_FN_RMII_CRS_DV, NULL); | |
929 | gpio_request(GPIO_FN_MDIO, NULL); | |
930 | gpio_request(GPIO_FN_MDC, NULL); | |
931 | gpio_request(GPIO_PTX5, NULL); | |
932 | gpio_direction_input(GPIO_PTX5); | |
933 | sh_eth_init(); | |
934 | ||
287c1297 | 935 | if (sw & SW41_B) { |
4f324311 | 936 | /* 720p */ |
44432407 GL |
937 | lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes; |
938 | lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes); | |
287c1297 KM |
939 | } else { |
940 | /* VGA */ | |
44432407 GL |
941 | lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes; |
942 | lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes); | |
287c1297 KM |
943 | } |
944 | ||
945 | if (sw & SW41_A) { | |
946 | /* Digital monitor */ | |
947 | lcdc_info.ch[0].interface_type = RGB18; | |
948 | lcdc_info.ch[0].flags = 0; | |
949 | } else { | |
950 | /* Analog monitor */ | |
951 | lcdc_info.ch[0].interface_type = RGB24; | |
952 | lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; | |
953 | } | |
954 | ||
2d151248 GL |
955 | /* VOU */ |
956 | gpio_request(GPIO_FN_DV_D15, NULL); | |
957 | gpio_request(GPIO_FN_DV_D14, NULL); | |
958 | gpio_request(GPIO_FN_DV_D13, NULL); | |
959 | gpio_request(GPIO_FN_DV_D12, NULL); | |
960 | gpio_request(GPIO_FN_DV_D11, NULL); | |
961 | gpio_request(GPIO_FN_DV_D10, NULL); | |
962 | gpio_request(GPIO_FN_DV_D9, NULL); | |
963 | gpio_request(GPIO_FN_DV_D8, NULL); | |
964 | gpio_request(GPIO_FN_DV_CLKI, NULL); | |
965 | gpio_request(GPIO_FN_DV_CLK, NULL); | |
966 | gpio_request(GPIO_FN_DV_VSYNC, NULL); | |
967 | gpio_request(GPIO_FN_DV_HSYNC, NULL); | |
968 | ||
287c1297 | 969 | return platform_add_devices(ms7724se_devices, |
a80cad95 | 970 | ARRAY_SIZE(ms7724se_devices)); |
287c1297 KM |
971 | } |
972 | device_initcall(devices_setup); | |
973 | ||
974 | static struct sh_machine_vector mv_ms7724se __initmv = { | |
975 | .mv_name = "ms7724se", | |
976 | .mv_init_irq = init_se7724_IRQ, | |
977 | .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR, | |
978 | }; |