[net-next-2.6.git] / arch / sh / boards / mach-migor / setup.c

/*
 * Renesas System Solutions Asia Pte. Ltd - Migo-R
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/mfd/sh_mobile_sdhi.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/i2c.h>
#include <linux/smc91x.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <media/ov772x.h>
#include <media/tw9910.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/suspend.h>
#include <mach/migor.h>
#include <cpu/sh7722.h>

/* Address     IRQ  Size  Bus  Description
 * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
 * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
 * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
 * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
 * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
 */

static struct smc91x_platdata smc91x_info = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct resource smc91x_eth_resources[] = {
	[0] = {
		.name   = "SMC91C111" ,
		.start  = 0x10000300,
		.end    = 0x1000030f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 32, /* IRQ0 */
		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct platform_device smc91x_eth_device = {
	.name           = "smc91x",
	.num_resources  = ARRAY_SIZE(smc91x_eth_resources),
	.resource       = smc91x_eth_resources,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
};

static struct sh_keysc_info sh_keysc_info = {
	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	.scan_timing = 3,
	.delay = 5,
	.keycodes = {
		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	},
};

static struct resource sh_keysc_resources[] = {
	[0] = {
		.start  = 0x044b0000,
		.end    = 0x044b000f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 79,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device sh_keysc_device = {
	.name           = "sh_keysc",
	.id             = 0, /* "keysc0" clock */
	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
	.resource       = sh_keysc_resources,
	.dev	= {
		.platform_data	= &sh_keysc_info,
	},
	.archdata = {
		.hwblk_id = HWBLK_KEYSC,
	},
};

static struct mtd_partition migor_nor_flash_partitions[] =
{
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	},
	{
		.name = "rootfs",
		.offset = MTDPART_OFS_APPEND,
		.size = (15 * 1024 * 1024),
	},
	{
		.name = "other",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data migor_nor_flash_data = {
	.width		= 2,
	.parts		= migor_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
};

static struct resource migor_nor_flash_resources[] = {
	[0] = {
		.name		= "NOR Flash",
		.start		= 0x00000000,
		.end		= 0x03ffffff,
		.flags		= IORESOURCE_MEM,
	}
};

static struct platform_device migor_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= migor_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
	.dev		= {
		.platform_data = &migor_nor_flash_data,
	},
};

static struct mtd_partition migor_nand_flash_partitions[] = {
	{
		.name		= "nanddata1",
		.offset		= 0x0,
		.size		= 512 * 1024 * 1024,
	},
	{
		.name		= "nanddata2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 512 * 1024 * 1024,
	},
};

static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
				     unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;

	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	else if (ctrl & NAND_ALE)
		writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	else
		writeb(cmd, chip->IO_ADDR_W);
}

static int migor_nand_flash_ready(struct mtd_info *mtd)
{
	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
}

static struct platform_nand_data migor_nand_flash_data = {
	.chip = {
		.nr_chips = 1,
		.partitions = migor_nand_flash_partitions,
		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
		.chip_delay = 20,
		.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	},
	.ctrl = {
		.dev_ready = migor_nand_flash_ready,
		.cmd_ctrl = migor_nand_flash_cmd_ctl,
	},
};

static struct resource migor_nand_flash_resources[] = {
	[0] = {
		.name		= "NAND Flash",
		.start		= 0x18000000,
		.end		= 0x18ffffff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device migor_nand_flash_device = {
	.name		= "gen_nand",
	.resource	= migor_nand_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
	.dev		= {
		.platform_data = &migor_nand_flash_data,
	}
};

static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	.clock_source = LCDC_CLK_BUS,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = RGB16,
		.clock_divider = 2,
		.lcd_cfg = {
			.name = "LB070WV1",
			.xres = 800,
			.yres = 480,
			.left_margin = 64,
			.right_margin = 16,
			.hsync_len = 120,
			.upper_margin = 1,
			.lower_margin = 17,
			.vsync_len = 2,
			.sync = 0,
		},
		.lcd_size_cfg = { /* 7.0 inch */
			.width = 152,
			.height = 91,
		},
	}
#endif
#ifdef CONFIG_SH_MIGOR_QVGA
	.clock_source = LCDC_CLK_PERIPHERAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = SYS16A,
		.clock_divider = 10,
		.lcd_cfg = {
			.name = "PH240320T",
			.xres = 320,
			.yres = 240,
			.left_margin = 0,
			.right_margin = 16,
			.hsync_len = 8,
			.upper_margin = 1,
			.lower_margin = 17,
			.vsync_len = 2,
			.sync = FB_SYNC_HOR_HIGH_ACT,
		},
		.lcd_size_cfg = { /* 2.4 inch */
			.width = 49,
			.height = 37,
		},
		.board_cfg = {
			.setup_sys = migor_lcd_qvga_setup,
		},
		.sys_bus_cfg = {
			.ldmt2r = 0x06000a09,
			.ldmt3r = 0x180e3418,
			/* set 1s delay to encourage fsync() */
			.deferred_io_msec = 1000,
		},
	}
#endif
};

static struct resource migor_lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe942fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device migor_lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(migor_lcdc_resources),
	.resource	= migor_lcdc_resources,
	.dev	= {
		.platform_data	= &sh_mobile_lcdc_info,
	},
	.archdata = {
		.hwblk_id = HWBLK_LCDC,
	},
};

static struct clk *camera_clk;
static DEFINE_MUTEX(camera_lock);

static void camera_power_on(int is_tw)
{
	mutex_lock(&camera_lock);

	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	 * around signal quality issues on Panel Board V2.1.
	 */
	camera_clk = clk_get(NULL, "video_clk");
	clk_set_rate(camera_clk, 10000000);
	clk_enable(camera_clk);	/* start VIO_CKO */

	/* use VIO_RST to take camera out of reset */
	mdelay(10);
	if (is_tw) {
		gpio_set_value(GPIO_PTT2, 0);
		gpio_set_value(GPIO_PTT0, 0);
	} else {
		gpio_set_value(GPIO_PTT0, 1);
	}
	gpio_set_value(GPIO_PTT3, 0);
	mdelay(10);
	gpio_set_value(GPIO_PTT3, 1);
	mdelay(10); /* wait to let chip come out of reset */
}

static void camera_power_off(void)
{
	clk_disable(camera_clk); /* stop VIO_CKO */
	clk_put(camera_clk);

	gpio_set_value(GPIO_PTT3, 0);
	mutex_unlock(&camera_lock);
}

static int ov7725_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(0);
	else
		camera_power_off();

	return 0;
}

static int tw9910_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(1);
	else
		camera_power_off();

	return 0;
}

static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};

static struct resource migor_ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = 52,
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device migor_ceu_device = {
	.name		= "sh_mobile_ceu",
	.id             = 0, /* "ceu0" clock */
	.num_resources	= ARRAY_SIZE(migor_ceu_resources),
	.resource	= migor_ceu_resources,
	.dev	= {
		.platform_data	= &sh_mobile_ceu_info,
	},
	.archdata = {
		.hwblk_id = HWBLK_CEU,
	},
};

static struct resource sdhi_cn9_resources[] = {
	[0] = {
		.name	= "SDHI",
		.start	= 0x04ce0000,
		.end	= 0x04ce01ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 100,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
};

static struct platform_device sdhi_cn9_device = {
	.name		= "sh_mobile_sdhi",
	.num_resources	= ARRAY_SIZE(sdhi_cn9_resources),
	.resource	= sdhi_cn9_resources,
	.dev = {
		.platform_data	= &sh7724_sdhi_data,
	},
	.archdata = {
		.hwblk_id = HWBLK_SDHI,
	},
};

static struct i2c_board_info migor_i2c_devices[] = {
	{
		I2C_BOARD_INFO("rs5c372b", 0x32),
	},
	{
		I2C_BOARD_INFO("migor_ts", 0x51),
		.irq = 38, /* IRQ6 */
	},
	{
		I2C_BOARD_INFO("wm8978", 0x1a),
	},
};

static struct i2c_board_info migor_i2c_camera[] = {
	{
		I2C_BOARD_INFO("ov772x", 0x21),
	},
	{
		I2C_BOARD_INFO("tw9910", 0x45),
	},
};

static struct ov772x_camera_info ov7725_info = {
	.flags		= OV772X_FLAG_8BIT,
};

static struct soc_camera_link ov7725_link = {
	.power		= ov7725_power,
	.board_info	= &migor_i2c_camera[0],
	.i2c_adapter_id	= 0,
	.priv		= &ov7725_info,
};

static struct tw9910_video_info tw9910_info = {
	.buswidth	= SOCAM_DATAWIDTH_8,
	.mpout		= TW9910_MPO_FIELD,
};

static struct soc_camera_link tw9910_link = {
	.power		= tw9910_power,
	.board_info	= &migor_i2c_camera[1],
	.i2c_adapter_id	= 0,
	.priv		= &tw9910_info,
};

static struct platform_device migor_camera[] = {
	{
		.name	= "soc-camera-pdrv",
		.id	= 0,
		.dev	= {
			.platform_data = &ov7725_link,
		},
	}, {
		.name	= "soc-camera-pdrv",
		.id	= 1,
		.dev	= {
			.platform_data = &tw9910_link,
		},
	},
};

static struct platform_device *migor_devices[] __initdata = {
	&smc91x_eth_device,
	&sh_keysc_device,
	&migor_lcdc_device,
	&migor_ceu_device,
	&migor_nor_flash_device,
	&migor_nand_flash_device,
	&sdhi_cn9_device,
	&migor_camera[0],
	&migor_camera[1],
};

extern char migor_sdram_enter_start;
extern char migor_sdram_enter_end;
extern char migor_sdram_leave_start;
extern char migor_sdram_leave_end;

static int __init migor_devices_setup(void)
{
	/* register board specific self-refresh code */
	sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
					&migor_sdram_enter_start,
					&migor_sdram_enter_end,
					&migor_sdram_leave_start,
					&migor_sdram_leave_end);
	/* Let D11 LED show STATUS0 */
	gpio_request(GPIO_FN_STATUS0, NULL);

	/* Lit D12 LED show PDSTATUS */
	gpio_request(GPIO_FN_PDSTATUS, NULL);

	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
	gpio_request(GPIO_FN_IRQ0, NULL);
	__raw_writel(0x00003400, BSC_CS4BCR);
	__raw_writel(0x00110080, BSC_CS4WCR);

	/* KEYSC */
	gpio_request(GPIO_FN_KEYOUT0, NULL);
	gpio_request(GPIO_FN_KEYOUT1, NULL);
	gpio_request(GPIO_FN_KEYOUT2, NULL);
	gpio_request(GPIO_FN_KEYOUT3, NULL);
	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	gpio_request(GPIO_FN_KEYIN1, NULL);
	gpio_request(GPIO_FN_KEYIN2, NULL);
	gpio_request(GPIO_FN_KEYIN3, NULL);
	gpio_request(GPIO_FN_KEYIN4, NULL);
	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);

	/* NAND Flash */
	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
	gpio_request(GPIO_PTA1, NULL);
	gpio_direction_input(GPIO_PTA1);

	/* SDHI */
	gpio_request(GPIO_FN_SDHICD, NULL);
	gpio_request(GPIO_FN_SDHIWP, NULL);
	gpio_request(GPIO_FN_SDHID3, NULL);
	gpio_request(GPIO_FN_SDHID2, NULL);
	gpio_request(GPIO_FN_SDHID1, NULL);
	gpio_request(GPIO_FN_SDHID0, NULL);
	gpio_request(GPIO_FN_SDHICMD, NULL);
	gpio_request(GPIO_FN_SDHICLK, NULL);

	/* Touch Panel */
	gpio_request(GPIO_FN_IRQ6, NULL);

	/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	gpio_request(GPIO_FN_LCDD17, NULL);
	gpio_request(GPIO_FN_LCDD16, NULL);
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDRS, NULL);
	gpio_request(GPIO_FN_LCDCS, NULL);
	gpio_request(GPIO_FN_LCDRD, NULL);
	gpio_request(GPIO_FN_LCDWR, NULL);
	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);
#endif

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	gpio_direction_output(GPIO_PTT3, 0);
	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	gpio_direction_output(GPIO_PTT2, 1);
	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	gpio_direction_output(GPIO_PTT0, 0);
#else
	gpio_direction_output(GPIO_PTT0, 1);
#endif
	__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */

	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);

	/* SIU: Port B */
	gpio_request(GPIO_FN_SIUBOLR, NULL);
	gpio_request(GPIO_FN_SIUBOBT, NULL);
	gpio_request(GPIO_FN_SIUBISLD, NULL);
	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	gpio_request(GPIO_FN_SIUMCKB, NULL);

	/*
	 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	 * output. Need only SIUB, set to output for master mode (table 34.2)
	 */
	__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);

	i2c_register_board_info(0, migor_i2c_devices,
				ARRAY_SIZE(migor_i2c_devices));

	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
arch_initcall(migor_devices_setup);

/* Return the board specific boot mode pin configuration */
static int migor_mode_pins(void)
{
	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	 * MD3=0: 16-bit Area0 Bus Width
	 * MD5=1: Little Endian
	 * TSTMD=1, MD8=0: Test Mode Disabled
	 */
	return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
}

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_migor __initmv = {
	.mv_name		= "Migo-R",
	.mv_mode_pins		= migor_mode_pins,
};
Commit	Line	Data
70f784ec MD	1	/*
	2	* Renesas System Solutions Asia Pte. Ltd - Migo-R
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
92cfeb61	13	#include <linux/input.h>
fc1d003d	14	#include <linux/input/sh_keysc.h>
65a1b034	15	#include <linux/mfd/sh_mobile_sdhi.h>
b8808786	16	#include <linux/mtd/physmap.h>
3c803a9a	17	#include <linux/mtd/nand.h>
0c6111ec	18	#include <linux/i2c.h>
8a3ee0fc	19	#include <linux/smc91x.h>
1765534c MD	20	#include <linux/delay.h>
1765534c MD	21	#include <linux/clk.h>
91b6f3c5	22	#include <linux/gpio.h>
70e5c4f0	23	#include <video/sh_mobile_lcdc.h>
1765534c	24	#include <media/sh_mobile_ceu.h>
ff04ea40	25	#include <media/ov772x.h>
deae7b86	26	#include <media/tw9910.h>
6c7d826c	27	#include <asm/clock.h>
70f784ec MD	28	#include <asm/machvec.h>
70f784ec MD	29	#include <asm/io.h>
13fa551b	30	#include <asm/suspend.h>
7639a454	31	#include <mach/migor.h>
f7275650	32	#include <cpu/sh7722.h>
70f784ec MD	33
	34	/* Address IRQ Size Bus Description
	35	* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
	36	* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
	37	* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
	38	* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
	39	* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
	40	*/
	41
8a3ee0fc	42	static struct smc91x_platdata smc91x_info = {
a30c89ad	43	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
8a3ee0fc MD	44	};
8a3ee0fc MD	45
70f784ec MD	46	static struct resource smc91x_eth_resources[] = {
70f784ec MD	47	[0] = {
b026a23c MD	48	.name = "SMC91C111" ,
	49	.start = 0x10000300,
	50	.end = 0x1000030f,
70f784ec MD	51	.flags = IORESOURCE_MEM,
	52	},
	53	[1] = {
	54	.start = 32, /* IRQ0 */
d280eadc	55	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
70f784ec MD	56	},
	57	};
	58
	59	static struct platform_device smc91x_eth_device = {
	60	.name = "smc91x",
	61	.num_resources = ARRAY_SIZE(smc91x_eth_resources),
	62	.resource = smc91x_eth_resources,
8a3ee0fc MD	63	.dev = {
	64	.platform_data = &smc91x_info,
	65	},
70f784ec MD	66	};
70f784ec MD	67
92cfeb61 MD	68	static struct sh_keysc_info sh_keysc_info = {
	69	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	70	.scan_timing = 3,
	71	.delay = 5,
	72	.keycodes = {
	73	0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
	74	0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
	75	0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
	76	0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
	77	0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	78	},
	79	};
	80
	81	static struct resource sh_keysc_resources[] = {
	82	[0] = {
	83	.start = 0x044b0000,
	84	.end = 0x044b000f,
	85	.flags = IORESOURCE_MEM,
	86	},
	87	[1] = {
	88	.start = 79,
	89	.flags = IORESOURCE_IRQ,
	90	},
	91	};
	92
	93	static struct platform_device sh_keysc_device = {
	94	.name = "sh_keysc",
090d951b	95	.id = 0, /* "keysc0" clock */
92cfeb61 MD	96	.num_resources = ARRAY_SIZE(sh_keysc_resources),
	97	.resource = sh_keysc_resources,
	98	.dev = {
	99	.platform_data = &sh_keysc_info,
	100	},
2de63cf3 MD	101	.archdata = {
	102	.hwblk_id = HWBLK_KEYSC,
	103	},
92cfeb61 MD	104	};
92cfeb61 MD	105
b8808786 MD	106	static struct mtd_partition migor_nor_flash_partitions[] =
	107	{
	108	{
	109	.name = "uboot",
	110	.offset = 0,
	111	.size = (1 * 1024 * 1024),
	112	.mask_flags = MTD_WRITEABLE, /* Read-only */
	113	},
	114	{
	115	.name = "rootfs",
	116	.offset = MTDPART_OFS_APPEND,
	117	.size = (15 * 1024 * 1024),
	118	},
	119	{
	120	.name = "other",
	121	.offset = MTDPART_OFS_APPEND,
	122	.size = MTDPART_SIZ_FULL,
	123	},
	124	};
	125
	126	static struct physmap_flash_data migor_nor_flash_data = {
	127	.width = 2,
	128	.parts = migor_nor_flash_partitions,
	129	.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
	130	};
	131
	132	static struct resource migor_nor_flash_resources[] = {
	133	[0] = {
	134	.name = "NOR Flash",
	135	.start = 0x00000000,
	136	.end = 0x03ffffff,
	137	.flags = IORESOURCE_MEM,
	138	}
	139	};
	140
	141	static struct platform_device migor_nor_flash_device = {
	142	.name = "physmap-flash",
	143	.resource = migor_nor_flash_resources,
	144	.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
	145	.dev = {
	146	.platform_data = &migor_nor_flash_data,
	147	},
	148	};
	149
3c803a9a MD	150	static struct mtd_partition migor_nand_flash_partitions[] = {
	151	{
	152	.name = "nanddata1",
	153	.offset = 0x0,
	154	.size = 512 * 1024 * 1024,
	155	},
	156	{
	157	.name = "nanddata2",
	158	.offset = MTDPART_OFS_APPEND,
	159	.size = 512 * 1024 * 1024,
	160	},
	161	};
	162
	163	static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
	164	unsigned int ctrl)
	165	{
	166	struct nand_chip *chip = mtd->priv;
	167
	168	if (cmd == NAND_CMD_NONE)
	169	return;
	170
	171	if (ctrl & NAND_CLE)
	172	writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	173	else if (ctrl & NAND_ALE)
	174	writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	175	else
	176	writeb(cmd, chip->IO_ADDR_W);
	177	}
	178
	179	static int migor_nand_flash_ready(struct mtd_info *mtd)
	180	{
91b6f3c5	181	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
3c803a9a MD	182	}
3c803a9a MD	183
30e0cc1a	184	static struct platform_nand_data migor_nand_flash_data = {
3c803a9a MD	185	.chip = {
	186	.nr_chips = 1,
	187	.partitions = migor_nand_flash_partitions,
	188	.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
	189	.chip_delay = 20,
	190	.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	191	},
	192	.ctrl = {
	193	.dev_ready = migor_nand_flash_ready,
	194	.cmd_ctrl = migor_nand_flash_cmd_ctl,
	195	},
	196	};
	197
	198	static struct resource migor_nand_flash_resources[] = {
	199	[0] = {
	200	.name = "NAND Flash",
	201	.start = 0x18000000,
	202	.end = 0x18ffffff,
	203	.flags = IORESOURCE_MEM,
	204	},
	205	};
	206
	207	static struct platform_device migor_nand_flash_device = {
	208	.name = "gen_nand",
	209	.resource = migor_nand_flash_resources,
	210	.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
	211	.dev = {
	212	.platform_data = &migor_nand_flash_data,
	213	}
	214	};
	215
8b1285f1 MD	216	static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
	217	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	218	.clock_source = LCDC_CLK_BUS,
	219	.ch[0] = {
	220	.chan = LCDC_CHAN_MAINLCD,
	221	.bpp = 16,
	222	.interface_type = RGB16,
	223	.clock_divider = 2,
	224	.lcd_cfg = {
	225	.name = "LB070WV1",
	226	.xres = 800,
	227	.yres = 480,
	228	.left_margin = 64,
	229	.right_margin = 16,
	230	.hsync_len = 120,
	231	.upper_margin = 1,
	232	.lower_margin = 17,
	233	.vsync_len = 2,
	234	.sync = 0,
	235	},
ce9c008c MD	236	.lcd_size_cfg = { /* 7.0 inch */
	237	.width = 152,
	238	.height = 91,
	239	},
8b1285f1 MD	240	}
	241	#endif
	242	#ifdef CONFIG_SH_MIGOR_QVGA
	243	.clock_source = LCDC_CLK_PERIPHERAL,
	244	.ch[0] = {
	245	.chan = LCDC_CHAN_MAINLCD,
	246	.bpp = 16,
	247	.interface_type = SYS16A,
	248	.clock_divider = 10,
	249	.lcd_cfg = {
	250	.name = "PH240320T",
	251	.xres = 320,
	252	.yres = 240,
	253	.left_margin = 0,
	254	.right_margin = 16,
	255	.hsync_len = 8,
	256	.upper_margin = 1,
	257	.lower_margin = 17,
	258	.vsync_len = 2,
	259	.sync = FB_SYNC_HOR_HIGH_ACT,
	260	},
ce9c008c MD	261	.lcd_size_cfg = { /* 2.4 inch */
	262	.width = 49,
	263	.height = 37,
	264	},
8b1285f1 MD	265	.board_cfg = {
	266	.setup_sys = migor_lcd_qvga_setup,
	267	},
	268	.sys_bus_cfg = {
	269	.ldmt2r = 0x06000a09,
	270	.ldmt3r = 0x180e3418,
b5868e8c MD	271	/* set 1s delay to encourage fsync() */
b5868e8c MD	272	.deferred_io_msec = 1000,
8b1285f1 MD	273	},
	274	}
	275	#endif
	276	};
	277
	278	static struct resource migor_lcdc_resources[] = {
	279	[0] = {
	280	.name = "LCDC",
	281	.start = 0xfe940000, /* P4-only space */
a6f15ade	282	.end = 0xfe942fff,
8b1285f1 MD	283	.flags = IORESOURCE_MEM,
8b1285f1 MD	284	},
07905554 MD	285	[1] = {
	286	.start = 28,
	287	.flags = IORESOURCE_IRQ,
	288	},
8b1285f1 MD	289	};
	290
	291	static struct platform_device migor_lcdc_device = {
	292	.name = "sh_mobile_lcdc_fb",
	293	.num_resources = ARRAY_SIZE(migor_lcdc_resources),
	294	.resource = migor_lcdc_resources,
	295	.dev = {
	296	.platform_data = &sh_mobile_lcdc_info,
	297	},
2de63cf3 MD	298	.archdata = {
	299	.hwblk_id = HWBLK_LCDC,
	300	},
8b1285f1 MD	301	};
8b1285f1 MD	302
1765534c	303	static struct clk *camera_clk;
deae7b86	304	static DEFINE_MUTEX(camera_lock);
1765534c	305
deae7b86	306	static void camera_power_on(int is_tw)
1765534c	307	{
deae7b86 KM	308	mutex_lock(&camera_lock);
deae7b86 KM	309
22ee3ba6 MD	310	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	311	* around signal quality issues on Panel Board V2.1.
	312	*/
1765534c	313	camera_clk = clk_get(NULL, "video_clk");
22ee3ba6	314	clk_set_rate(camera_clk, 10000000);
1765534c MD	315	clk_enable(camera_clk); /* start VIO_CKO */
1765534c MD	316
91b6f3c5	317	/* use VIO_RST to take camera out of reset */
1765534c	318	mdelay(10);
deae7b86 KM	319	if (is_tw) {
	320	gpio_set_value(GPIO_PTT2, 0);
	321	gpio_set_value(GPIO_PTT0, 0);
	322	} else {
	323	gpio_set_value(GPIO_PTT0, 1);
	324	}
91b6f3c5	325	gpio_set_value(GPIO_PTT3, 0);
1765534c	326	mdelay(10);
91b6f3c5	327	gpio_set_value(GPIO_PTT3, 1);
4545bfa0	328	mdelay(10); /* wait to let chip come out of reset */
1765534c MD	329	}
	330
	331	static void camera_power_off(void)
	332	{
	333	clk_disable(camera_clk); /* stop VIO_CKO */
	334	clk_put(camera_clk);
	335
91b6f3c5	336	gpio_set_value(GPIO_PTT3, 0);
deae7b86	337	mutex_unlock(&camera_lock);
1765534c MD	338	}
1765534c MD	339
ff04ea40 KM	340	static int ov7725_power(struct device *dev, int mode)
	341	{
	342	if (mode)
deae7b86 KM	343	camera_power_on(0);
	344	else
	345	camera_power_off();
	346
	347	return 0;
	348	}
	349
	350	static int tw9910_power(struct device *dev, int mode)
	351	{
	352	if (mode)
	353	camera_power_on(1);
ff04ea40 KM	354	else
	355	camera_power_off();
	356
	357	return 0;
	358	}
	359
1765534c	360	static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
64935056	361	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
1765534c MD	362	};
	363
	364	static struct resource migor_ceu_resources[] = {
	365	[0] = {
	366	.name = "CEU",
	367	.start = 0xfe910000,
	368	.end = 0xfe91009f,
	369	.flags = IORESOURCE_MEM,
	370	},
	371	[1] = {
	372	.start = 52,
	373	.flags = IORESOURCE_IRQ,
	374	},
	375	[2] = {
	376	/* place holder for contiguous memory */
	377	},
	378	};
	379
	380	static struct platform_device migor_ceu_device = {
	381	.name = "sh_mobile_ceu",
a42b6dd6	382	.id = 0, /* "ceu0" clock */
1765534c MD	383	.num_resources = ARRAY_SIZE(migor_ceu_resources),
	384	.resource = migor_ceu_resources,
	385	.dev = {
	386	.platform_data = &sh_mobile_ceu_info,
	387	},
2de63cf3 MD	388	.archdata = {
	389	.hwblk_id = HWBLK_CEU,
	390	},
1765534c MD	391	};
1765534c MD	392
2e3fc56c MD	393	static struct resource sdhi_cn9_resources[] = {
	394	[0] = {
	395	.name = "SDHI",
	396	.start = 0x04ce0000,
	397	.end = 0x04ce01ff,
	398	.flags = IORESOURCE_MEM,
	399	},
	400	[1] = {
8d9adaba	401	.start = 100,
2e3fc56c MD	402	.flags = IORESOURCE_IRQ,
2e3fc56c MD	403	},
70e5c4f0 MD	404	};
70e5c4f0 MD	405
65a1b034 GL	406	static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
	407	.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
	408	.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
	409	};
	410
2e3fc56c MD	411	static struct platform_device sdhi_cn9_device = {
	412	.name = "sh_mobile_sdhi",
	413	.num_resources = ARRAY_SIZE(sdhi_cn9_resources),
	414	.resource = sdhi_cn9_resources,
65a1b034 GL	415	.dev = {
	416	.platform_data = &sh7724_sdhi_data,
	417	},
2e3fc56c MD	418	.archdata = {
2e3fc56c MD	419	.hwblk_id = HWBLK_SDHI,
70e5c4f0 MD	420	},
	421	};
	422
1765534c	423	static struct i2c_board_info migor_i2c_devices[] = {
57795867	424	{
3760f736	425	I2C_BOARD_INFO("rs5c372b", 0x32),
57795867	426	},
67908abf MD	427	{
	428	I2C_BOARD_INFO("migor_ts", 0x51),
	429	.irq = 38, /* IRQ6 */
	430	},
920925f9 GL	431	{
	432	I2C_BOARD_INFO("wm8978", 0x1a),
	433	},
2cb582ca GL	434	};
	435
	436	static struct i2c_board_info migor_i2c_camera[] = {
ff04ea40 KM	437	{
ff04ea40 KM	438	I2C_BOARD_INFO("ov772x", 0x21),
ff04ea40	439	},
deae7b86 KM	440	{
deae7b86 KM	441	I2C_BOARD_INFO("tw9910", 0x45),
deae7b86	442	},
0c6111ec MD	443	};
0c6111ec MD	444
2cb582ca	445	static struct ov772x_camera_info ov7725_info = {
3675c750	446	.flags = OV772X_FLAG_8BIT,
0f448294 GL	447	};
	448
	449	static struct soc_camera_link ov7725_link = {
	450	.power = ov7725_power,
	451	.board_info = &migor_i2c_camera[0],
	452	.i2c_adapter_id = 0,
0f448294	453	.priv = &ov7725_info,
2cb582ca GL	454	};
	455
	456	static struct tw9910_video_info tw9910_info = {
	457	.buswidth = SOCAM_DATAWIDTH_8,
	458	.mpout = TW9910_MPO_FIELD,
0f448294 GL	459	};
	460
	461	static struct soc_camera_link tw9910_link = {
	462	.power = tw9910_power,
	463	.board_info = &migor_i2c_camera[1],
	464	.i2c_adapter_id = 0,
0f448294	465	.priv = &tw9910_info,
2cb582ca GL	466	};
	467
	468	static struct platform_device migor_camera[] = {
	469	{
	470	.name = "soc-camera-pdrv",
	471	.id = 0,
	472	.dev = {
0f448294	473	.platform_data = &ov7725_link,
2cb582ca GL	474	},
	475	}, {
	476	.name = "soc-camera-pdrv",
	477	.id = 1,
	478	.dev = {
0f448294	479	.platform_data = &tw9910_link,
2cb582ca GL	480	},
	481	},
	482	};
	483
	484	static struct platform_device *migor_devices[] __initdata = {
	485	&smc91x_eth_device,
	486	&sh_keysc_device,
	487	&migor_lcdc_device,
	488	&migor_ceu_device,
	489	&migor_nor_flash_device,
	490	&migor_nand_flash_device,
2e3fc56c	491	&sdhi_cn9_device,
2cb582ca GL	492	&migor_camera[0],
	493	&migor_camera[1],
	494	};
	495
13fa551b MD	496	extern char migor_sdram_enter_start;
	497	extern char migor_sdram_enter_end;
	498	extern char migor_sdram_leave_start;
	499	extern char migor_sdram_leave_end;
	500
70f784ec MD	501	static int __init migor_devices_setup(void)
70f784ec MD	502	{
13fa551b MD	503	/* register board specific self-refresh code */
	504	sh_mobile_register_self_refresh(SUSP_SH_STANDBY \| SUSP_SH_SF,
	505	&migor_sdram_enter_start,
	506	&migor_sdram_enter_end,
	507	&migor_sdram_leave_start,
	508	&migor_sdram_leave_end);
50840714 MD	509	/* Let D11 LED show STATUS0 */
	510	gpio_request(GPIO_FN_STATUS0, NULL);
	511
	512	/* Lit D12 LED show PDSTATUS */
	513	gpio_request(GPIO_FN_PDSTATUS, NULL);
91b6f3c5	514
a30c89ad	515	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
91b6f3c5	516	gpio_request(GPIO_FN_IRQ0, NULL);
9d56dd3b PM	517	__raw_writel(0x00003400, BSC_CS4BCR);
9d56dd3b PM	518	__raw_writel(0x00110080, BSC_CS4WCR);
91b6f3c5 MD	519
91b6f3c5 MD	520	/* KEYSC */
91b6f3c5 MD	521	gpio_request(GPIO_FN_KEYOUT0, NULL);
	522	gpio_request(GPIO_FN_KEYOUT1, NULL);
	523	gpio_request(GPIO_FN_KEYOUT2, NULL);
	524	gpio_request(GPIO_FN_KEYOUT3, NULL);
	525	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	526	gpio_request(GPIO_FN_KEYIN1, NULL);
	527	gpio_request(GPIO_FN_KEYIN2, NULL);
	528	gpio_request(GPIO_FN_KEYIN3, NULL);
	529	gpio_request(GPIO_FN_KEYIN4, NULL);
	530	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
	531
	532	/* NAND Flash */
	533	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
9d56dd3b	534	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) \| 0x0200, BSC_CS6ABCR);
91b6f3c5 MD	535	gpio_request(GPIO_PTA1, NULL);
	536	gpio_direction_input(GPIO_PTA1);
	537
2e3fc56c MD	538	/* SDHI */
	539	gpio_request(GPIO_FN_SDHICD, NULL);
	540	gpio_request(GPIO_FN_SDHIWP, NULL);
	541	gpio_request(GPIO_FN_SDHID3, NULL);
	542	gpio_request(GPIO_FN_SDHID2, NULL);
	543	gpio_request(GPIO_FN_SDHID1, NULL);
	544	gpio_request(GPIO_FN_SDHID0, NULL);
	545	gpio_request(GPIO_FN_SDHICMD, NULL);
	546	gpio_request(GPIO_FN_SDHICLK, NULL);
	547
91b6f3c5 MD	548	/* Touch Panel */
	549	gpio_request(GPIO_FN_IRQ6, NULL);
	550
	551	/* LCD Panel */
91b6f3c5 MD	552	#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	553	gpio_request(GPIO_FN_LCDD17, NULL);
	554	gpio_request(GPIO_FN_LCDD16, NULL);
	555	gpio_request(GPIO_FN_LCDD15, NULL);
	556	gpio_request(GPIO_FN_LCDD14, NULL);
	557	gpio_request(GPIO_FN_LCDD13, NULL);
	558	gpio_request(GPIO_FN_LCDD12, NULL);
	559	gpio_request(GPIO_FN_LCDD11, NULL);
	560	gpio_request(GPIO_FN_LCDD10, NULL);
	561	gpio_request(GPIO_FN_LCDD8, NULL);
	562	gpio_request(GPIO_FN_LCDD7, NULL);
	563	gpio_request(GPIO_FN_LCDD6, NULL);
	564	gpio_request(GPIO_FN_LCDD5, NULL);
	565	gpio_request(GPIO_FN_LCDD4, NULL);
	566	gpio_request(GPIO_FN_LCDD3, NULL);
	567	gpio_request(GPIO_FN_LCDD2, NULL);
	568	gpio_request(GPIO_FN_LCDD1, NULL);
	569	gpio_request(GPIO_FN_LCDRS, NULL);
	570	gpio_request(GPIO_FN_LCDCS, NULL);
	571	gpio_request(GPIO_FN_LCDRD, NULL);
	572	gpio_request(GPIO_FN_LCDWR, NULL);
	573	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	574	gpio_direction_output(GPIO_PTH2, 1);
	575	#endif
	576	#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	577	gpio_request(GPIO_FN_LCDD15, NULL);
	578	gpio_request(GPIO_FN_LCDD14, NULL);
	579	gpio_request(GPIO_FN_LCDD13, NULL);
	580	gpio_request(GPIO_FN_LCDD12, NULL);
	581	gpio_request(GPIO_FN_LCDD11, NULL);
	582	gpio_request(GPIO_FN_LCDD10, NULL);
	583	gpio_request(GPIO_FN_LCDD9, NULL);
	584	gpio_request(GPIO_FN_LCDD8, NULL);
	585	gpio_request(GPIO_FN_LCDD7, NULL);
	586	gpio_request(GPIO_FN_LCDD6, NULL);
	587	gpio_request(GPIO_FN_LCDD5, NULL);
	588	gpio_request(GPIO_FN_LCDD4, NULL);
	589	gpio_request(GPIO_FN_LCDD3, NULL);
	590	gpio_request(GPIO_FN_LCDD2, NULL);
	591	gpio_request(GPIO_FN_LCDD1, NULL);
	592	gpio_request(GPIO_FN_LCDD0, NULL);
	593	gpio_request(GPIO_FN_LCDLCLK, NULL);
	594	gpio_request(GPIO_FN_LCDDCK, NULL);
	595	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	596	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	597	gpio_request(GPIO_FN_LCDVSYN, NULL);
	598	gpio_request(GPIO_FN_LCDHSYN, NULL);
	599	gpio_request(GPIO_FN_LCDDISP, NULL);
	600	gpio_request(GPIO_FN_LCDDON, NULL);
	601	#endif
	602
	603	/* CEU */
91b6f3c5 MD	604	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	605	gpio_request(GPIO_FN_VIO_VD2, NULL);
	606	gpio_request(GPIO_FN_VIO_HD2, NULL);
	607	gpio_request(GPIO_FN_VIO_FLD, NULL);
	608	gpio_request(GPIO_FN_VIO_CKO, NULL);
	609	gpio_request(GPIO_FN_VIO_D15, NULL);
	610	gpio_request(GPIO_FN_VIO_D14, NULL);
	611	gpio_request(GPIO_FN_VIO_D13, NULL);
	612	gpio_request(GPIO_FN_VIO_D12, NULL);
	613	gpio_request(GPIO_FN_VIO_D11, NULL);
	614	gpio_request(GPIO_FN_VIO_D10, NULL);
	615	gpio_request(GPIO_FN_VIO_D9, NULL);
	616	gpio_request(GPIO_FN_VIO_D8, NULL);
	617
	618	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	619	gpio_direction_output(GPIO_PTT3, 0);
	620	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	621	gpio_direction_output(GPIO_PTT2, 1);
	622	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
	623	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	624	gpio_direction_output(GPIO_PTT0, 0);
	625	#else
	626	gpio_direction_output(GPIO_PTT0, 1);
	627	#endif
9d56dd3b	628	__raw_writew(__raw_readw(PORT_MSELCRB) \| 0x2000, PORT_MSELCRB); /* D15->D8 */
1765534c MD	629
1765534c MD	630	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
6c7d826c	631
920925f9 GL	632	/* SIU: Port B */
	633	gpio_request(GPIO_FN_SIUBOLR, NULL);
	634	gpio_request(GPIO_FN_SIUBOBT, NULL);
	635	gpio_request(GPIO_FN_SIUBISLD, NULL);
	636	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	637	gpio_request(GPIO_FN_SIUMCKB, NULL);
	638
	639	/*
	640	* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	641	* output. Need only SIUB, set to output for master mode (table 34.2)
	642	*/
7d0b0a44	643	__raw_writew(__raw_readw(PORT_MSELCRA) \| 1, PORT_MSELCRA);
920925f9	644
0c6111ec MD	645	i2c_register_board_info(0, migor_i2c_devices,
0c6111ec MD	646	ARRAY_SIZE(migor_i2c_devices));
91b6f3c5	647
70f784ec MD	648	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
70f784ec MD	649	}
ba3a1701	650	arch_initcall(migor_devices_setup);
0ec80fdd MD	651
	652	/* Return the board specific boot mode pin configuration */
	653	static int migor_mode_pins(void)
	654	{
	655	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	656	* MD3=0: 16-bit Area0 Bus Width
	657	* MD5=1: Little Endian
	658	* TSTMD=1, MD8=0: Test Mode Disabled
	659	*/
	660	return MODE_PIN0 \| MODE_PIN1 \| MODE_PIN5;
	661	}
	662
	663	/*
	664	* The Machine Vector
	665	*/
	666	static struct sh_machine_vector mv_migor __initmv = {
	667	.mv_name = "Migo-R",
	668	.mv_mode_pins = migor_mode_pins,
	669	};