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CommitLineData
1da177e4
LT
1/*
2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
4 *
5 * S390 version
d2fec595 6 * Copyright IBM Corp. 1999, 2008
1da177e4
LT
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 *
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 */
14
feab6501
MS
15#define KMSG_COMPONENT "time"
16#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
17
1da177e4
LT
18#include <linux/errno.h>
19#include <linux/module.h>
20#include <linux/sched.h>
21#include <linux/kernel.h>
22#include <linux/param.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/interrupt.h>
750887de
HC
26#include <linux/cpu.h>
27#include <linux/stop_machine.h>
1da177e4 28#include <linux/time.h>
3367b994 29#include <linux/sysdev.h>
1da177e4
LT
30#include <linux/delay.h>
31#include <linux/init.h>
32#include <linux/smp.h>
33#include <linux/types.h>
34#include <linux/profile.h>
35#include <linux/timex.h>
36#include <linux/notifier.h>
dc64bef5 37#include <linux/clocksource.h>
5a62b192 38#include <linux/clockchips.h>
5a0e3ad6 39#include <linux/gfp.h>
1da177e4
LT
40#include <asm/uaccess.h>
41#include <asm/delay.h>
42#include <asm/s390_ext.h>
43#include <asm/div64.h>
b020632e 44#include <asm/vdso.h>
1da177e4 45#include <asm/irq.h>
5a489b98 46#include <asm/irq_regs.h>
1da177e4 47#include <asm/timer.h>
d54853ef 48#include <asm/etr.h>
a806170e 49#include <asm/cio.h>
1da177e4
LT
50
51/* change this if you have some constant time drift */
52#define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
53#define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
54
b6112ccb 55u64 sched_clock_base_cc = -1; /* Force to data section. */
05e7ff7d 56EXPORT_SYMBOL_GPL(sched_clock_base_cc);
b6112ccb 57
5a62b192 58static DEFINE_PER_CPU(struct clock_event_device, comparators);
1da177e4 59
1da177e4
LT
60/*
61 * Scheduler clock - returns current time in nanosec units.
62 */
88dbd203 63unsigned long long notrace sched_clock(void)
1da177e4 64{
05e7ff7d 65 return (get_clock_monotonic() * 125) >> 9;
1da177e4
LT
66}
67
32f65f27
JG
68/*
69 * Monotonic_clock - returns # of nanoseconds passed since time_init()
70 */
71unsigned long long monotonic_clock(void)
72{
73 return sched_clock();
74}
75EXPORT_SYMBOL(monotonic_clock);
76
b1e2ba8d 77void tod_to_timeval(__u64 todval, struct timespec *xt)
1da177e4
LT
78{
79 unsigned long long sec;
80
81 sec = todval >> 12;
82 do_div(sec, 1000000);
b1e2ba8d 83 xt->tv_sec = sec;
1da177e4 84 todval -= (sec * 1000000) << 12;
b1e2ba8d 85 xt->tv_nsec = ((todval * 1000) >> 12);
1da177e4 86}
b592e89a 87EXPORT_SYMBOL(tod_to_timeval);
1da177e4 88
5a62b192 89void clock_comparator_work(void)
1da177e4 90{
5a62b192 91 struct clock_event_device *cd;
1da177e4 92
5a62b192
HC
93 S390_lowcore.clock_comparator = -1ULL;
94 set_clock_comparator(S390_lowcore.clock_comparator);
95 cd = &__get_cpu_var(comparators);
96 cd->event_handler(cd);
1da177e4
LT
97}
98
1da177e4 99/*
5a62b192 100 * Fixup the clock comparator.
1da177e4 101 */
5a62b192 102static void fixup_clock_comparator(unsigned long long delta)
1da177e4 103{
5a62b192
HC
104 /* If nobody is waiting there's nothing to fix. */
105 if (S390_lowcore.clock_comparator == -1ULL)
1da177e4 106 return;
5a62b192
HC
107 S390_lowcore.clock_comparator += delta;
108 set_clock_comparator(S390_lowcore.clock_comparator);
1da177e4
LT
109}
110
5a62b192
HC
111static int s390_next_event(unsigned long delta,
112 struct clock_event_device *evt)
1da177e4 113{
5a62b192
HC
114 S390_lowcore.clock_comparator = get_clock() + delta;
115 set_clock_comparator(S390_lowcore.clock_comparator);
116 return 0;
1da177e4
LT
117}
118
5a62b192
HC
119static void s390_set_mode(enum clock_event_mode mode,
120 struct clock_event_device *evt)
1da177e4 121{
d54853ef
MS
122}
123
124/*
125 * Set up lowcore and control register of the current cpu to
126 * enable TOD clock and clock comparator interrupts.
1da177e4
LT
127 */
128void init_cpu_timer(void)
129{
5a62b192
HC
130 struct clock_event_device *cd;
131 int cpu;
132
133 S390_lowcore.clock_comparator = -1ULL;
134 set_clock_comparator(S390_lowcore.clock_comparator);
135
136 cpu = smp_processor_id();
137 cd = &per_cpu(comparators, cpu);
138 cd->name = "comparator";
139 cd->features = CLOCK_EVT_FEAT_ONESHOT;
140 cd->mult = 16777;
141 cd->shift = 12;
142 cd->min_delta_ns = 1;
143 cd->max_delta_ns = LONG_MAX;
144 cd->rating = 400;
320ab2b0 145 cd->cpumask = cpumask_of(cpu);
5a62b192
HC
146 cd->set_next_event = s390_next_event;
147 cd->set_mode = s390_set_mode;
148
149 clockevents_register_device(cd);
d54853ef
MS
150
151 /* Enable clock comparator timer interrupt. */
152 __ctl_set_bit(0,11);
153
d2fec595 154 /* Always allow the timing alert external interrupt. */
d54853ef
MS
155 __ctl_set_bit(0, 4);
156}
157
158static void clock_comparator_interrupt(__u16 code)
159{
d3d238c7
HC
160 if (S390_lowcore.clock_comparator == -1ULL)
161 set_clock_comparator(S390_lowcore.clock_comparator);
d54853ef
MS
162}
163
d2fec595
MS
164static void etr_timing_alert(struct etr_irq_parm *);
165static void stp_timing_alert(struct stp_irq_parm *);
166
167static void timing_alert_interrupt(__u16 code)
168{
169 if (S390_lowcore.ext_params & 0x00c40000)
170 etr_timing_alert((struct etr_irq_parm *)
171 &S390_lowcore.ext_params);
172 if (S390_lowcore.ext_params & 0x00038000)
173 stp_timing_alert((struct stp_irq_parm *)
174 &S390_lowcore.ext_params);
175}
176
d54853ef 177static void etr_reset(void);
d2fec595 178static void stp_reset(void);
d54853ef 179
d4f587c6 180void read_persistent_clock(struct timespec *ts)
d54853ef 181{
d4f587c6 182 tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, ts);
1da177e4 183}
d54853ef 184
23970e38
MS
185void read_boot_clock(struct timespec *ts)
186{
187 tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts);
1da177e4
LT
188}
189
8e19608e 190static cycle_t read_tod_clock(struct clocksource *cs)
dc64bef5
MS
191{
192 return get_clock();
193}
194
195static struct clocksource clocksource_tod = {
196 .name = "tod",
d2cb0e6e 197 .rating = 400,
dc64bef5
MS
198 .read = read_tod_clock,
199 .mask = -1ULL,
200 .mult = 1000,
201 .shift = 12,
cc02d809 202 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
dc64bef5
MS
203};
204
f1b82746
MS
205struct clocksource * __init clocksource_default_clock(void)
206{
207 return &clocksource_tod;
208}
dc64bef5 209
0696b711
LM
210void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
211 u32 mult)
b020632e
MS
212{
213 if (clock != &clocksource_tod)
214 return;
215
216 /* Make userspace gettimeofday spin until we're done. */
217 ++vdso_data->tb_update_count;
218 smp_wmb();
219 vdso_data->xtime_tod_stamp = clock->cycle_last;
b1e2ba8d
JS
220 vdso_data->xtime_clock_sec = wall_time->tv_sec;
221 vdso_data->xtime_clock_nsec = wall_time->tv_nsec;
b020632e
MS
222 vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec;
223 vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec;
224 smp_wmb();
225 ++vdso_data->tb_update_count;
226}
227
228extern struct timezone sys_tz;
229
230void update_vsyscall_tz(void)
231{
232 /* Make userspace gettimeofday spin until we're done. */
233 ++vdso_data->tb_update_count;
234 smp_wmb();
235 vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
236 vdso_data->tz_dsttime = sys_tz.tz_dsttime;
237 smp_wmb();
238 ++vdso_data->tb_update_count;
239}
240
1da177e4
LT
241/*
242 * Initialize the TOD clock and the CPU timer of
243 * the boot cpu.
244 */
245void __init time_init(void)
246{
b6112ccb
MS
247 /* Reset time synchronization interfaces. */
248 etr_reset();
249 stp_reset();
1da177e4 250
1da177e4 251 /* request the clock comparator external interrupt */
d7d1104f 252 if (register_external_interrupt(0x1004, clock_comparator_interrupt))
1da177e4
LT
253 panic("Couldn't request external interrupt 0x1004");
254
d2fec595 255 /* request the timing alert external interrupt */
d7d1104f 256 if (register_external_interrupt(0x1406, timing_alert_interrupt))
d54853ef
MS
257 panic("Couldn't request external interrupt 0x1406");
258
ab96e798
MS
259 if (clocksource_register(&clocksource_tod) != 0)
260 panic("Could not register TOD clock source");
261
d54853ef
MS
262 /* Enable TOD clock interrupts on the boot cpu. */
263 init_cpu_timer();
ab96e798 264
c185b783 265 /* Enable cpu timer interrupts on the boot cpu. */
1da177e4 266 vtime_init();
d54853ef
MS
267}
268
d2fec595
MS
269/*
270 * The time is "clock". old is what we think the time is.
271 * Adjust the value by a multiple of jiffies and add the delta to ntp.
272 * "delay" is an approximation how long the synchronization took. If
273 * the time correction is positive, then "delay" is subtracted from
274 * the time difference and only the remaining part is passed to ntp.
275 */
276static unsigned long long adjust_time(unsigned long long old,
277 unsigned long long clock,
278 unsigned long long delay)
279{
280 unsigned long long delta, ticks;
281 struct timex adjust;
282
283 if (clock > old) {
284 /* It is later than we thought. */
285 delta = ticks = clock - old;
286 delta = ticks = (delta < delay) ? 0 : delta - delay;
287 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
288 adjust.offset = ticks * (1000000 / HZ);
289 } else {
290 /* It is earlier than we thought. */
291 delta = ticks = old - clock;
292 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
293 delta = -delta;
294 adjust.offset = -ticks * (1000000 / HZ);
295 }
8107d829 296 sched_clock_base_cc += delta;
d2fec595 297 if (adjust.offset != 0) {
feab6501
MS
298 pr_notice("The ETR interface has adjusted the clock "
299 "by %li microseconds\n", adjust.offset);
d2fec595
MS
300 adjust.modes = ADJ_OFFSET_SINGLESHOT;
301 do_adjtimex(&adjust);
302 }
303 return delta;
304}
305
306static DEFINE_PER_CPU(atomic_t, clock_sync_word);
8283cb43 307static DEFINE_MUTEX(clock_sync_mutex);
d2fec595
MS
308static unsigned long clock_sync_flags;
309
310#define CLOCK_SYNC_HAS_ETR 0
311#define CLOCK_SYNC_HAS_STP 1
312#define CLOCK_SYNC_ETR 2
313#define CLOCK_SYNC_STP 3
314
315/*
316 * The synchronous get_clock function. It will write the current clock
317 * value to the clock pointer and return 0 if the clock is in sync with
318 * the external time source. If the clock mode is local it will return
319 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
320 * reference.
321 */
322int get_sync_clock(unsigned long long *clock)
323{
324 atomic_t *sw_ptr;
325 unsigned int sw0, sw1;
326
327 sw_ptr = &get_cpu_var(clock_sync_word);
328 sw0 = atomic_read(sw_ptr);
329 *clock = get_clock();
330 sw1 = atomic_read(sw_ptr);
bd119ee2 331 put_cpu_var(clock_sync_word);
d2fec595
MS
332 if (sw0 == sw1 && (sw0 & 0x80000000U))
333 /* Success: time is in sync. */
334 return 0;
335 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
336 !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
337 return -ENOSYS;
338 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
339 !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
340 return -EACCES;
341 return -EAGAIN;
342}
343EXPORT_SYMBOL(get_sync_clock);
344
345/*
346 * Make get_sync_clock return -EAGAIN.
347 */
348static void disable_sync_clock(void *dummy)
349{
350 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
351 /*
352 * Clear the in-sync bit 2^31. All get_sync_clock calls will
353 * fail until the sync bit is turned back on. In addition
354 * increase the "sequence" counter to avoid the race of an
355 * etr event and the complete recovery against get_sync_clock.
356 */
357 atomic_clear_mask(0x80000000, sw_ptr);
358 atomic_inc(sw_ptr);
359}
360
361/*
362 * Make get_sync_clock return 0 again.
363 * Needs to be called from a context disabled for preemption.
364 */
365static void enable_sync_clock(void)
366{
367 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
368 atomic_set_mask(0x80000000, sw_ptr);
369}
370
8283cb43
MS
371/*
372 * Function to check if the clock is in sync.
373 */
374static inline int check_sync_clock(void)
375{
376 atomic_t *sw_ptr;
377 int rc;
378
379 sw_ptr = &get_cpu_var(clock_sync_word);
380 rc = (atomic_read(sw_ptr) & 0x80000000U) != 0;
bd119ee2 381 put_cpu_var(clock_sync_word);
8283cb43
MS
382 return rc;
383}
384
750887de
HC
385/* Single threaded workqueue used for etr and stp sync events */
386static struct workqueue_struct *time_sync_wq;
387
388static void __init time_init_wq(void)
389{
179cb81a
HC
390 if (time_sync_wq)
391 return;
392 time_sync_wq = create_singlethread_workqueue("timesync");
750887de
HC
393}
394
d54853ef
MS
395/*
396 * External Time Reference (ETR) code.
397 */
398static int etr_port0_online;
399static int etr_port1_online;
d2fec595 400static int etr_steai_available;
d54853ef
MS
401
402static int __init early_parse_etr(char *p)
403{
404 if (strncmp(p, "off", 3) == 0)
405 etr_port0_online = etr_port1_online = 0;
406 else if (strncmp(p, "port0", 5) == 0)
407 etr_port0_online = 1;
408 else if (strncmp(p, "port1", 5) == 0)
409 etr_port1_online = 1;
410 else if (strncmp(p, "on", 2) == 0)
411 etr_port0_online = etr_port1_online = 1;
412 return 0;
413}
414early_param("etr", early_parse_etr);
415
416enum etr_event {
417 ETR_EVENT_PORT0_CHANGE,
418 ETR_EVENT_PORT1_CHANGE,
419 ETR_EVENT_PORT_ALERT,
420 ETR_EVENT_SYNC_CHECK,
421 ETR_EVENT_SWITCH_LOCAL,
422 ETR_EVENT_UPDATE,
423};
424
d54853ef
MS
425/*
426 * Valid bit combinations of the eacr register are (x = don't care):
427 * e0 e1 dp p0 p1 ea es sl
428 * 0 0 x 0 0 0 0 0 initial, disabled state
429 * 0 0 x 0 1 1 0 0 port 1 online
430 * 0 0 x 1 0 1 0 0 port 0 online
431 * 0 0 x 1 1 1 0 0 both ports online
432 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
433 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
434 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
435 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
436 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
437 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
438 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
439 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
440 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
441 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
442 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
443 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
444 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
445 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
446 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
447 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
448 */
449static struct etr_eacr etr_eacr;
450static u64 etr_tolec; /* time of last eacr update */
d54853ef
MS
451static struct etr_aib etr_port0;
452static int etr_port0_uptodate;
453static struct etr_aib etr_port1;
454static int etr_port1_uptodate;
455static unsigned long etr_events;
456static struct timer_list etr_timer;
d54853ef
MS
457
458static void etr_timeout(unsigned long dummy);
ecdcc023 459static void etr_work_fn(struct work_struct *work);
0b3016b7 460static DEFINE_MUTEX(etr_work_mutex);
ecdcc023 461static DECLARE_WORK(etr_work, etr_work_fn);
d54853ef 462
d54853ef
MS
463/*
464 * Reset ETR attachment.
465 */
466static void etr_reset(void)
467{
468 etr_eacr = (struct etr_eacr) {
469 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
470 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
471 .es = 0, .sl = 0 };
d2fec595 472 if (etr_setr(&etr_eacr) == 0) {
d54853ef 473 etr_tolec = get_clock();
d2fec595 474 set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
8283cb43
MS
475 if (etr_port0_online && etr_port1_online)
476 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d2fec595 477 } else if (etr_port0_online || etr_port1_online) {
feab6501
MS
478 pr_warning("The real or virtual hardware system does "
479 "not provide an ETR interface\n");
d2fec595 480 etr_port0_online = etr_port1_online = 0;
d54853ef
MS
481 }
482}
483
ecdcc023 484static int __init etr_init(void)
d54853ef
MS
485{
486 struct etr_aib aib;
487
d2fec595 488 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
ecdcc023 489 return 0;
750887de 490 time_init_wq();
d54853ef
MS
491 /* Check if this machine has the steai instruction. */
492 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
d2fec595 493 etr_steai_available = 1;
d54853ef 494 setup_timer(&etr_timer, etr_timeout, 0UL);
d54853ef
MS
495 if (etr_port0_online) {
496 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 497 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
498 }
499 if (etr_port1_online) {
500 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 501 queue_work(time_sync_wq, &etr_work);
d54853ef 502 }
ecdcc023 503 return 0;
d54853ef
MS
504}
505
ecdcc023
MS
506arch_initcall(etr_init);
507
d54853ef
MS
508/*
509 * Two sorts of ETR machine checks. The architecture reads:
510 * "When a machine-check niterruption occurs and if a switch-to-local or
511 * ETR-sync-check interrupt request is pending but disabled, this pending
512 * disabled interruption request is indicated and is cleared".
513 * Which means that we can get etr_switch_to_local events from the machine
514 * check handler although the interruption condition is disabled. Lovely..
515 */
516
517/*
518 * Switch to local machine check. This is called when the last usable
519 * ETR port goes inactive. After switch to local the clock is not in sync.
520 */
521void etr_switch_to_local(void)
522{
523 if (!etr_eacr.sl)
524 return;
8283cb43 525 disable_sync_clock(NULL);
d54853ef 526 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
750887de 527 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
528}
529
530/*
531 * ETR sync check machine check. This is called when the ETR OTE and the
532 * local clock OTE are farther apart than the ETR sync check tolerance.
533 * After a ETR sync check the clock is not in sync. The machine check
534 * is broadcasted to all cpus at the same time.
535 */
536void etr_sync_check(void)
537{
538 if (!etr_eacr.es)
539 return;
8283cb43 540 disable_sync_clock(NULL);
d54853ef 541 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
750887de 542 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
543}
544
545/*
d2fec595 546 * ETR timing alert. There are two causes:
d54853ef
MS
547 * 1) port state change, check the usability of the port
548 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
549 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
550 * or ETR-data word 4 (edf4) has changed.
551 */
d2fec595 552static void etr_timing_alert(struct etr_irq_parm *intparm)
d54853ef 553{
d54853ef
MS
554 if (intparm->pc0)
555 /* ETR port 0 state change. */
556 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
557 if (intparm->pc1)
558 /* ETR port 1 state change. */
559 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
560 if (intparm->eai)
561 /*
562 * ETR port alert on either port 0, 1 or both.
563 * Both ports are not up-to-date now.
564 */
565 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
750887de 566 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
567}
568
569static void etr_timeout(unsigned long dummy)
570{
571 set_bit(ETR_EVENT_UPDATE, &etr_events);
750887de 572 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
573}
574
575/*
576 * Check if the etr mode is pss.
577 */
578static inline int etr_mode_is_pps(struct etr_eacr eacr)
579{
580 return eacr.es && !eacr.sl;
581}
582
583/*
584 * Check if the etr mode is etr.
585 */
586static inline int etr_mode_is_etr(struct etr_eacr eacr)
587{
588 return eacr.es && eacr.sl;
589}
590
591/*
592 * Check if the port can be used for TOD synchronization.
593 * For PPS mode the port has to receive OTEs. For ETR mode
594 * the port has to receive OTEs, the ETR stepping bit has to
595 * be zero and the validity bits for data frame 1, 2, and 3
596 * have to be 1.
597 */
598static int etr_port_valid(struct etr_aib *aib, int port)
599{
600 unsigned int psc;
601
602 /* Check that this port is receiving OTEs. */
603 if (aib->tsp == 0)
604 return 0;
605
606 psc = port ? aib->esw.psc1 : aib->esw.psc0;
607 if (psc == etr_lpsc_pps_mode)
608 return 1;
609 if (psc == etr_lpsc_operational_step)
610 return !aib->esw.y && aib->slsw.v1 &&
611 aib->slsw.v2 && aib->slsw.v3;
612 return 0;
613}
614
615/*
616 * Check if two ports are on the same network.
617 */
618static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
619{
620 // FIXME: any other fields we have to compare?
621 return aib1->edf1.net_id == aib2->edf1.net_id;
622}
623
624/*
625 * Wrapper for etr_stei that converts physical port states
626 * to logical port states to be consistent with the output
627 * of stetr (see etr_psc vs. etr_lpsc).
628 */
629static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
630{
631 BUG_ON(etr_steai(aib, func) != 0);
632 /* Convert port state to logical port state. */
633 if (aib->esw.psc0 == 1)
634 aib->esw.psc0 = 2;
635 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
636 aib->esw.psc0 = 1;
637 if (aib->esw.psc1 == 1)
638 aib->esw.psc1 = 2;
639 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
640 aib->esw.psc1 = 1;
641}
642
643/*
644 * Check if the aib a2 is still connected to the same attachment as
645 * aib a1, the etv values differ by one and a2 is valid.
646 */
647static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
648{
649 int state_a1, state_a2;
650
651 /* Paranoia check: e0/e1 should better be the same. */
652 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
653 a1->esw.eacr.e1 != a2->esw.eacr.e1)
654 return 0;
655
656 /* Still connected to the same etr ? */
657 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
658 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
659 if (state_a1 == etr_lpsc_operational_step) {
660 if (state_a2 != etr_lpsc_operational_step ||
661 a1->edf1.net_id != a2->edf1.net_id ||
662 a1->edf1.etr_id != a2->edf1.etr_id ||
663 a1->edf1.etr_pn != a2->edf1.etr_pn)
664 return 0;
665 } else if (state_a2 != etr_lpsc_pps_mode)
666 return 0;
667
668 /* The ETV value of a2 needs to be ETV of a1 + 1. */
669 if (a1->edf2.etv + 1 != a2->edf2.etv)
670 return 0;
671
672 if (!etr_port_valid(a2, p))
673 return 0;
674
675 return 1;
676}
677
d2fec595 678struct clock_sync_data {
750887de 679 atomic_t cpus;
5a62b192
HC
680 int in_sync;
681 unsigned long long fixup_cc;
750887de
HC
682 int etr_port;
683 struct etr_aib *etr_aib;
d2fec595 684};
5a62b192 685
750887de 686static void clock_sync_cpu(struct clock_sync_data *sync)
d54853ef 687{
750887de 688 atomic_dec(&sync->cpus);
d2fec595 689 enable_sync_clock();
d54853ef
MS
690 /*
691 * This looks like a busy wait loop but it isn't. etr_sync_cpus
692 * is called on all other cpus while the TOD clocks is stopped.
693 * __udelay will stop the cpu on an enabled wait psw until the
694 * TOD is running again.
695 */
d2fec595 696 while (sync->in_sync == 0) {
d54853ef 697 __udelay(1);
6c732de2
HC
698 /*
699 * A different cpu changes *in_sync. Therefore use
700 * barrier() to force memory access.
701 */
702 barrier();
703 }
d2fec595 704 if (sync->in_sync != 1)
d54853ef 705 /* Didn't work. Clear per-cpu in sync bit again. */
d2fec595 706 disable_sync_clock(NULL);
d54853ef
MS
707 /*
708 * This round of TOD syncing is done. Set the clock comparator
709 * to the next tick and let the processor continue.
710 */
d2fec595 711 fixup_clock_comparator(sync->fixup_cc);
d54853ef
MS
712}
713
d54853ef
MS
714/*
715 * Sync the TOD clock using the port refered to by aibp. This port
716 * has to be enabled and the other port has to be disabled. The
717 * last eacr update has to be more than 1.6 seconds in the past.
718 */
750887de 719static int etr_sync_clock(void *data)
d54853ef 720{
750887de 721 static int first;
5a62b192 722 unsigned long long clock, old_clock, delay, delta;
750887de
HC
723 struct clock_sync_data *etr_sync;
724 struct etr_aib *sync_port, *aib;
725 int port;
d54853ef
MS
726 int rc;
727
750887de 728 etr_sync = data;
d54853ef 729
750887de
HC
730 if (xchg(&first, 1) == 1) {
731 /* Slave */
732 clock_sync_cpu(etr_sync);
733 return 0;
734 }
735
736 /* Wait until all other cpus entered the sync function. */
737 while (atomic_read(&etr_sync->cpus) != 0)
738 cpu_relax();
739
740 port = etr_sync->etr_port;
741 aib = etr_sync->etr_aib;
742 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
d2fec595 743 enable_sync_clock();
d54853ef
MS
744
745 /* Set clock to next OTE. */
746 __ctl_set_bit(14, 21);
747 __ctl_set_bit(0, 29);
748 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
5a62b192 749 old_clock = get_clock();
d54853ef
MS
750 if (set_clock(clock) == 0) {
751 __udelay(1); /* Wait for the clock to start. */
752 __ctl_clear_bit(0, 29);
753 __ctl_clear_bit(14, 21);
754 etr_stetr(aib);
755 /* Adjust Linux timing variables. */
756 delay = (unsigned long long)
757 (aib->edf2.etv - sync_port->edf2.etv) << 32;
d2fec595 758 delta = adjust_time(old_clock, clock, delay);
750887de 759 etr_sync->fixup_cc = delta;
5a62b192 760 fixup_clock_comparator(delta);
d54853ef
MS
761 /* Verify that the clock is properly set. */
762 if (!etr_aib_follows(sync_port, aib, port)) {
763 /* Didn't work. */
d2fec595 764 disable_sync_clock(NULL);
750887de 765 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
766 rc = -EAGAIN;
767 } else {
750887de 768 etr_sync->in_sync = 1;
d54853ef
MS
769 rc = 0;
770 }
771 } else {
772 /* Could not set the clock ?!? */
773 __ctl_clear_bit(0, 29);
774 __ctl_clear_bit(14, 21);
d2fec595 775 disable_sync_clock(NULL);
750887de 776 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
777 rc = -EAGAIN;
778 }
750887de
HC
779 xchg(&first, 0);
780 return rc;
781}
782
783static int etr_sync_clock_stop(struct etr_aib *aib, int port)
784{
785 struct clock_sync_data etr_sync;
786 struct etr_aib *sync_port;
787 int follows;
788 int rc;
789
790 /* Check if the current aib is adjacent to the sync port aib. */
791 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
792 follows = etr_aib_follows(sync_port, aib, port);
793 memcpy(sync_port, aib, sizeof(*aib));
794 if (!follows)
795 return -EAGAIN;
796 memset(&etr_sync, 0, sizeof(etr_sync));
797 etr_sync.etr_aib = aib;
798 etr_sync.etr_port = port;
799 get_online_cpus();
800 atomic_set(&etr_sync.cpus, num_online_cpus() - 1);
801 rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map);
802 put_online_cpus();
d54853ef
MS
803 return rc;
804}
805
806/*
807 * Handle the immediate effects of the different events.
808 * The port change event is used for online/offline changes.
809 */
810static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
811{
812 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
813 eacr.es = 0;
814 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
815 eacr.es = eacr.sl = 0;
816 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
817 etr_port0_uptodate = etr_port1_uptodate = 0;
818
819 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
820 if (eacr.e0)
821 /*
822 * Port change of an enabled port. We have to
823 * assume that this can have caused an stepping
824 * port switch.
825 */
826 etr_tolec = get_clock();
827 eacr.p0 = etr_port0_online;
828 if (!eacr.p0)
829 eacr.e0 = 0;
830 etr_port0_uptodate = 0;
831 }
832 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
833 if (eacr.e1)
834 /*
835 * Port change of an enabled port. We have to
836 * assume that this can have caused an stepping
837 * port switch.
838 */
839 etr_tolec = get_clock();
840 eacr.p1 = etr_port1_online;
841 if (!eacr.p1)
842 eacr.e1 = 0;
843 etr_port1_uptodate = 0;
844 }
845 clear_bit(ETR_EVENT_UPDATE, &etr_events);
846 return eacr;
847}
848
849/*
850 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
851 * one of the ports needs an update.
852 */
853static void etr_set_tolec_timeout(unsigned long long now)
854{
855 unsigned long micros;
856
857 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
858 (!etr_eacr.p1 || etr_port1_uptodate))
859 return;
860 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
861 micros = (micros > 1600000) ? 0 : 1600000 - micros;
862 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
863}
864
865/*
866 * Set up a time that expires after 1/2 second.
867 */
868static void etr_set_sync_timeout(void)
869{
870 mod_timer(&etr_timer, jiffies + HZ/2);
871}
872
873/*
874 * Update the aib information for one or both ports.
875 */
876static struct etr_eacr etr_handle_update(struct etr_aib *aib,
877 struct etr_eacr eacr)
878{
879 /* With both ports disabled the aib information is useless. */
880 if (!eacr.e0 && !eacr.e1)
881 return eacr;
882
ecdcc023 883 /* Update port0 or port1 with aib stored in etr_work_fn. */
d54853ef
MS
884 if (aib->esw.q == 0) {
885 /* Information for port 0 stored. */
886 if (eacr.p0 && !etr_port0_uptodate) {
887 etr_port0 = *aib;
888 if (etr_port0_online)
889 etr_port0_uptodate = 1;
890 }
891 } else {
892 /* Information for port 1 stored. */
893 if (eacr.p1 && !etr_port1_uptodate) {
894 etr_port1 = *aib;
895 if (etr_port0_online)
896 etr_port1_uptodate = 1;
897 }
898 }
899
900 /*
901 * Do not try to get the alternate port aib if the clock
902 * is not in sync yet.
903 */
8283cb43 904 if (!check_sync_clock())
d54853ef
MS
905 return eacr;
906
907 /*
908 * If steai is available we can get the information about
909 * the other port immediately. If only stetr is available the
910 * data-port bit toggle has to be used.
911 */
d2fec595 912 if (etr_steai_available) {
d54853ef
MS
913 if (eacr.p0 && !etr_port0_uptodate) {
914 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
915 etr_port0_uptodate = 1;
916 }
917 if (eacr.p1 && !etr_port1_uptodate) {
918 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
919 etr_port1_uptodate = 1;
920 }
921 } else {
922 /*
923 * One port was updated above, if the other
924 * port is not uptodate toggle dp bit.
925 */
926 if ((eacr.p0 && !etr_port0_uptodate) ||
927 (eacr.p1 && !etr_port1_uptodate))
928 eacr.dp ^= 1;
929 else
930 eacr.dp = 0;
931 }
932 return eacr;
933}
934
935/*
936 * Write new etr control register if it differs from the current one.
937 * Return 1 if etr_tolec has been updated as well.
938 */
939static void etr_update_eacr(struct etr_eacr eacr)
940{
941 int dp_changed;
942
943 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
944 /* No change, return. */
945 return;
946 /*
947 * The disable of an active port of the change of the data port
948 * bit can/will cause a change in the data port.
949 */
950 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
951 (etr_eacr.dp ^ eacr.dp) != 0;
952 etr_eacr = eacr;
953 etr_setr(&etr_eacr);
954 if (dp_changed)
955 etr_tolec = get_clock();
956}
957
958/*
750887de 959 * ETR work. In this function you'll find the main logic. In
d54853ef
MS
960 * particular this is the only function that calls etr_update_eacr(),
961 * it "controls" the etr control register.
962 */
ecdcc023 963static void etr_work_fn(struct work_struct *work)
d54853ef
MS
964{
965 unsigned long long now;
966 struct etr_eacr eacr;
967 struct etr_aib aib;
968 int sync_port;
969
0b3016b7
MS
970 /* prevent multiple execution. */
971 mutex_lock(&etr_work_mutex);
972
d54853ef
MS
973 /* Create working copy of etr_eacr. */
974 eacr = etr_eacr;
975
976 /* Check for the different events and their immediate effects. */
977 eacr = etr_handle_events(eacr);
978
979 /* Check if ETR is supposed to be active. */
980 eacr.ea = eacr.p0 || eacr.p1;
981 if (!eacr.ea) {
982 /* Both ports offline. Reset everything. */
983 eacr.dp = eacr.es = eacr.sl = 0;
1a781a77 984 on_each_cpu(disable_sync_clock, NULL, 1);
d54853ef
MS
985 del_timer_sync(&etr_timer);
986 etr_update_eacr(eacr);
0b3016b7 987 goto out_unlock;
d54853ef
MS
988 }
989
990 /* Store aib to get the current ETR status word. */
991 BUG_ON(etr_stetr(&aib) != 0);
992 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
993 now = get_clock();
994
995 /*
996 * Update the port information if the last stepping port change
997 * or data port change is older than 1.6 seconds.
998 */
999 if (now >= etr_tolec + (1600000 << 12))
1000 eacr = etr_handle_update(&aib, eacr);
1001
1002 /*
1003 * Select ports to enable. The prefered synchronization mode is PPS.
1004 * If a port can be enabled depends on a number of things:
1005 * 1) The port needs to be online and uptodate. A port is not
1006 * disabled just because it is not uptodate, but it is only
1007 * enabled if it is uptodate.
1008 * 2) The port needs to have the same mode (pps / etr).
1009 * 3) The port needs to be usable -> etr_port_valid() == 1
1010 * 4) To enable the second port the clock needs to be in sync.
1011 * 5) If both ports are useable and are ETR ports, the network id
1012 * has to be the same.
1013 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
1014 */
1015 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
1016 eacr.sl = 0;
1017 eacr.e0 = 1;
1018 if (!etr_mode_is_pps(etr_eacr))
1019 eacr.es = 0;
1020 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
1021 eacr.e1 = 0;
1022 // FIXME: uptodate checks ?
1023 else if (etr_port0_uptodate && etr_port1_uptodate)
1024 eacr.e1 = 1;
1025 sync_port = (etr_port0_uptodate &&
1026 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1027 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
1028 eacr.sl = 0;
1029 eacr.e0 = 0;
1030 eacr.e1 = 1;
1031 if (!etr_mode_is_pps(etr_eacr))
1032 eacr.es = 0;
1033 sync_port = (etr_port1_uptodate &&
1034 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1035 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
1036 eacr.sl = 1;
1037 eacr.e0 = 1;
1038 if (!etr_mode_is_etr(etr_eacr))
1039 eacr.es = 0;
1040 if (!eacr.es || !eacr.p1 ||
1041 aib.esw.psc1 != etr_lpsc_operational_alt)
1042 eacr.e1 = 0;
1043 else if (etr_port0_uptodate && etr_port1_uptodate &&
1044 etr_compare_network(&etr_port0, &etr_port1))
1045 eacr.e1 = 1;
1046 sync_port = (etr_port0_uptodate &&
1047 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1048 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
1049 eacr.sl = 1;
1050 eacr.e0 = 0;
1051 eacr.e1 = 1;
1052 if (!etr_mode_is_etr(etr_eacr))
1053 eacr.es = 0;
1054 sync_port = (etr_port1_uptodate &&
1055 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1056 } else {
1057 /* Both ports not usable. */
1058 eacr.es = eacr.sl = 0;
1059 sync_port = -1;
d54853ef
MS
1060 }
1061
1062 /*
1063 * If the clock is in sync just update the eacr and return.
1064 * If there is no valid sync port wait for a port update.
1065 */
8283cb43 1066 if (check_sync_clock() || sync_port < 0) {
d54853ef
MS
1067 etr_update_eacr(eacr);
1068 etr_set_tolec_timeout(now);
0b3016b7 1069 goto out_unlock;
d54853ef
MS
1070 }
1071
1072 /*
1073 * Prepare control register for clock syncing
1074 * (reset data port bit, set sync check control.
1075 */
1076 eacr.dp = 0;
1077 eacr.es = 1;
1078
1079 /*
1080 * Update eacr and try to synchronize the clock. If the update
1081 * of eacr caused a stepping port switch (or if we have to
1082 * assume that a stepping port switch has occured) or the
1083 * clock syncing failed, reset the sync check control bit
1084 * and set up a timer to try again after 0.5 seconds
1085 */
1086 etr_update_eacr(eacr);
1087 if (now < etr_tolec + (1600000 << 12) ||
750887de 1088 etr_sync_clock_stop(&aib, sync_port) != 0) {
d54853ef
MS
1089 /* Sync failed. Try again in 1/2 second. */
1090 eacr.es = 0;
1091 etr_update_eacr(eacr);
1092 etr_set_sync_timeout();
1093 } else
1094 etr_set_tolec_timeout(now);
0b3016b7
MS
1095out_unlock:
1096 mutex_unlock(&etr_work_mutex);
d54853ef
MS
1097}
1098
1099/*
1100 * Sysfs interface functions
1101 */
1102static struct sysdev_class etr_sysclass = {
af5ca3f4 1103 .name = "etr",
d54853ef
MS
1104};
1105
1106static struct sys_device etr_port0_dev = {
1107 .id = 0,
1108 .cls = &etr_sysclass,
1109};
1110
1111static struct sys_device etr_port1_dev = {
1112 .id = 1,
1113 .cls = &etr_sysclass,
1114};
1115
1116/*
1117 * ETR class attributes
1118 */
c9be0a36
AK
1119static ssize_t etr_stepping_port_show(struct sysdev_class *class,
1120 struct sysdev_class_attribute *attr,
1121 char *buf)
d54853ef
MS
1122{
1123 return sprintf(buf, "%i\n", etr_port0.esw.p);
1124}
1125
1126static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
1127
c9be0a36
AK
1128static ssize_t etr_stepping_mode_show(struct sysdev_class *class,
1129 struct sysdev_class_attribute *attr,
1130 char *buf)
d54853ef
MS
1131{
1132 char *mode_str;
1133
1134 if (etr_mode_is_pps(etr_eacr))
1135 mode_str = "pps";
1136 else if (etr_mode_is_etr(etr_eacr))
1137 mode_str = "etr";
1138 else
1139 mode_str = "local";
1140 return sprintf(buf, "%s\n", mode_str);
1141}
1142
1143static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
1144
1145/*
1146 * ETR port attributes
1147 */
1148static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
1149{
1150 if (dev == &etr_port0_dev)
1151 return etr_port0_online ? &etr_port0 : NULL;
1152 else
1153 return etr_port1_online ? &etr_port1 : NULL;
1154}
1155
4a0b2b4d
AK
1156static ssize_t etr_online_show(struct sys_device *dev,
1157 struct sysdev_attribute *attr,
1158 char *buf)
d54853ef
MS
1159{
1160 unsigned int online;
1161
1162 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1163 return sprintf(buf, "%i\n", online);
1164}
1165
1166static ssize_t etr_online_store(struct sys_device *dev,
4a0b2b4d
AK
1167 struct sysdev_attribute *attr,
1168 const char *buf, size_t count)
d54853ef
MS
1169{
1170 unsigned int value;
1171
1172 value = simple_strtoul(buf, NULL, 0);
1173 if (value != 0 && value != 1)
1174 return -EINVAL;
d2fec595
MS
1175 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
1176 return -EOPNOTSUPP;
8283cb43 1177 mutex_lock(&clock_sync_mutex);
d54853ef
MS
1178 if (dev == &etr_port0_dev) {
1179 if (etr_port0_online == value)
8283cb43 1180 goto out; /* Nothing to do. */
d54853ef 1181 etr_port0_online = value;
8283cb43
MS
1182 if (etr_port0_online && etr_port1_online)
1183 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1184 else
1185 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1186 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 1187 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
1188 } else {
1189 if (etr_port1_online == value)
8283cb43 1190 goto out; /* Nothing to do. */
d54853ef 1191 etr_port1_online = value;
8283cb43
MS
1192 if (etr_port0_online && etr_port1_online)
1193 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1194 else
1195 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1196 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 1197 queue_work(time_sync_wq, &etr_work);
d54853ef 1198 }
8283cb43
MS
1199out:
1200 mutex_unlock(&clock_sync_mutex);
d54853ef
MS
1201 return count;
1202}
1203
1204static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
1205
4a0b2b4d
AK
1206static ssize_t etr_stepping_control_show(struct sys_device *dev,
1207 struct sysdev_attribute *attr,
1208 char *buf)
d54853ef
MS
1209{
1210 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1211 etr_eacr.e0 : etr_eacr.e1);
1212}
1213
1214static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
1215
4a0b2b4d
AK
1216static ssize_t etr_mode_code_show(struct sys_device *dev,
1217 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1218{
1219 if (!etr_port0_online && !etr_port1_online)
1220 /* Status word is not uptodate if both ports are offline. */
1221 return -ENODATA;
1222 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1223 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1224}
1225
1226static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
1227
4a0b2b4d
AK
1228static ssize_t etr_untuned_show(struct sys_device *dev,
1229 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1230{
1231 struct etr_aib *aib = etr_aib_from_dev(dev);
1232
1233 if (!aib || !aib->slsw.v1)
1234 return -ENODATA;
1235 return sprintf(buf, "%i\n", aib->edf1.u);
1236}
1237
1238static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
1239
4a0b2b4d
AK
1240static ssize_t etr_network_id_show(struct sys_device *dev,
1241 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1242{
1243 struct etr_aib *aib = etr_aib_from_dev(dev);
1244
1245 if (!aib || !aib->slsw.v1)
1246 return -ENODATA;
1247 return sprintf(buf, "%i\n", aib->edf1.net_id);
1248}
1249
1250static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
1251
4a0b2b4d
AK
1252static ssize_t etr_id_show(struct sys_device *dev,
1253 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1254{
1255 struct etr_aib *aib = etr_aib_from_dev(dev);
1256
1257 if (!aib || !aib->slsw.v1)
1258 return -ENODATA;
1259 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1260}
1261
1262static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
1263
4a0b2b4d
AK
1264static ssize_t etr_port_number_show(struct sys_device *dev,
1265 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1266{
1267 struct etr_aib *aib = etr_aib_from_dev(dev);
1268
1269 if (!aib || !aib->slsw.v1)
1270 return -ENODATA;
1271 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1272}
1273
1274static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
1275
4a0b2b4d
AK
1276static ssize_t etr_coupled_show(struct sys_device *dev,
1277 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1278{
1279 struct etr_aib *aib = etr_aib_from_dev(dev);
1280
1281 if (!aib || !aib->slsw.v3)
1282 return -ENODATA;
1283 return sprintf(buf, "%i\n", aib->edf3.c);
1284}
1285
1286static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
1287
4a0b2b4d
AK
1288static ssize_t etr_local_time_show(struct sys_device *dev,
1289 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1290{
1291 struct etr_aib *aib = etr_aib_from_dev(dev);
1292
1293 if (!aib || !aib->slsw.v3)
1294 return -ENODATA;
1295 return sprintf(buf, "%i\n", aib->edf3.blto);
1296}
1297
1298static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
1299
4a0b2b4d
AK
1300static ssize_t etr_utc_offset_show(struct sys_device *dev,
1301 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1302{
1303 struct etr_aib *aib = etr_aib_from_dev(dev);
1304
1305 if (!aib || !aib->slsw.v3)
1306 return -ENODATA;
1307 return sprintf(buf, "%i\n", aib->edf3.buo);
1308}
1309
1310static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
1311
1312static struct sysdev_attribute *etr_port_attributes[] = {
1313 &attr_online,
1314 &attr_stepping_control,
1315 &attr_state_code,
1316 &attr_untuned,
1317 &attr_network,
1318 &attr_id,
1319 &attr_port,
1320 &attr_coupled,
1321 &attr_local_time,
1322 &attr_utc_offset,
1323 NULL
1324};
1325
1326static int __init etr_register_port(struct sys_device *dev)
1327{
1328 struct sysdev_attribute **attr;
1329 int rc;
1330
1331 rc = sysdev_register(dev);
1332 if (rc)
1333 goto out;
1334 for (attr = etr_port_attributes; *attr; attr++) {
1335 rc = sysdev_create_file(dev, *attr);
1336 if (rc)
1337 goto out_unreg;
1338 }
1339 return 0;
1340out_unreg:
1341 for (; attr >= etr_port_attributes; attr--)
1342 sysdev_remove_file(dev, *attr);
1343 sysdev_unregister(dev);
1344out:
1345 return rc;
1346}
1347
1348static void __init etr_unregister_port(struct sys_device *dev)
1349{
1350 struct sysdev_attribute **attr;
1351
1352 for (attr = etr_port_attributes; *attr; attr++)
1353 sysdev_remove_file(dev, *attr);
1354 sysdev_unregister(dev);
1355}
1356
1357static int __init etr_init_sysfs(void)
1358{
1359 int rc;
1360
1361 rc = sysdev_class_register(&etr_sysclass);
1362 if (rc)
1363 goto out;
1364 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
1365 if (rc)
1366 goto out_unreg_class;
1367 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
1368 if (rc)
1369 goto out_remove_stepping_port;
1370 rc = etr_register_port(&etr_port0_dev);
1371 if (rc)
1372 goto out_remove_stepping_mode;
1373 rc = etr_register_port(&etr_port1_dev);
1374 if (rc)
1375 goto out_remove_port0;
1376 return 0;
1377
1378out_remove_port0:
1379 etr_unregister_port(&etr_port0_dev);
1380out_remove_stepping_mode:
1381 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
1382out_remove_stepping_port:
1383 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
1384out_unreg_class:
1385 sysdev_class_unregister(&etr_sysclass);
1386out:
1387 return rc;
1da177e4
LT
1388}
1389
d54853ef 1390device_initcall(etr_init_sysfs);
d2fec595
MS
1391
1392/*
1393 * Server Time Protocol (STP) code.
1394 */
1395static int stp_online;
1396static struct stp_sstpi stp_info;
1397static void *stp_page;
1398
1399static void stp_work_fn(struct work_struct *work);
0b3016b7 1400static DEFINE_MUTEX(stp_work_mutex);
d2fec595 1401static DECLARE_WORK(stp_work, stp_work_fn);
04362301 1402static struct timer_list stp_timer;
d2fec595
MS
1403
1404static int __init early_parse_stp(char *p)
1405{
1406 if (strncmp(p, "off", 3) == 0)
1407 stp_online = 0;
1408 else if (strncmp(p, "on", 2) == 0)
1409 stp_online = 1;
1410 return 0;
1411}
1412early_param("stp", early_parse_stp);
1413
1414/*
1415 * Reset STP attachment.
1416 */
8f847003 1417static void __init stp_reset(void)
d2fec595
MS
1418{
1419 int rc;
1420
d7d1104f 1421 stp_page = (void *) get_zeroed_page(GFP_ATOMIC);
d2fec595 1422 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
4a672cfa 1423 if (rc == 0)
d2fec595
MS
1424 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
1425 else if (stp_online) {
feab6501
MS
1426 pr_warning("The real or virtual hardware system does "
1427 "not provide an STP interface\n");
d7d1104f 1428 free_page((unsigned long) stp_page);
d2fec595
MS
1429 stp_page = NULL;
1430 stp_online = 0;
1431 }
1432}
1433
04362301
MS
1434static void stp_timeout(unsigned long dummy)
1435{
1436 queue_work(time_sync_wq, &stp_work);
1437}
1438
d2fec595
MS
1439static int __init stp_init(void)
1440{
750887de
HC
1441 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1442 return 0;
04362301 1443 setup_timer(&stp_timer, stp_timeout, 0UL);
750887de
HC
1444 time_init_wq();
1445 if (!stp_online)
1446 return 0;
1447 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1448 return 0;
1449}
1450
1451arch_initcall(stp_init);
1452
1453/*
1454 * STP timing alert. There are three causes:
1455 * 1) timing status change
1456 * 2) link availability change
1457 * 3) time control parameter change
1458 * In all three cases we are only interested in the clock source state.
1459 * If a STP clock source is now available use it.
1460 */
1461static void stp_timing_alert(struct stp_irq_parm *intparm)
1462{
1463 if (intparm->tsc || intparm->lac || intparm->tcpc)
750887de 1464 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1465}
1466
1467/*
1468 * STP sync check machine check. This is called when the timing state
1469 * changes from the synchronized state to the unsynchronized state.
1470 * After a STP sync check the clock is not in sync. The machine check
1471 * is broadcasted to all cpus at the same time.
1472 */
1473void stp_sync_check(void)
1474{
d2fec595 1475 disable_sync_clock(NULL);
750887de 1476 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1477}
1478
1479/*
1480 * STP island condition machine check. This is called when an attached
1481 * server attempts to communicate over an STP link and the servers
1482 * have matching CTN ids and have a valid stratum-1 configuration
1483 * but the configurations do not match.
1484 */
1485void stp_island_check(void)
1486{
d2fec595 1487 disable_sync_clock(NULL);
750887de 1488 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1489}
1490
750887de
HC
1491
1492static int stp_sync_clock(void *data)
d2fec595 1493{
750887de 1494 static int first;
d2fec595 1495 unsigned long long old_clock, delta;
750887de 1496 struct clock_sync_data *stp_sync;
d2fec595
MS
1497 int rc;
1498
750887de 1499 stp_sync = data;
d2fec595 1500
750887de
HC
1501 if (xchg(&first, 1) == 1) {
1502 /* Slave */
1503 clock_sync_cpu(stp_sync);
1504 return 0;
1505 }
d2fec595 1506
750887de
HC
1507 /* Wait until all other cpus entered the sync function. */
1508 while (atomic_read(&stp_sync->cpus) != 0)
1509 cpu_relax();
d2fec595 1510
d2fec595
MS
1511 enable_sync_clock();
1512
d2fec595
MS
1513 rc = 0;
1514 if (stp_info.todoff[0] || stp_info.todoff[1] ||
1515 stp_info.todoff[2] || stp_info.todoff[3] ||
1516 stp_info.tmd != 2) {
1517 old_clock = get_clock();
1518 rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
1519 if (rc == 0) {
1520 delta = adjust_time(old_clock, get_clock(), 0);
1521 fixup_clock_comparator(delta);
1522 rc = chsc_sstpi(stp_page, &stp_info,
1523 sizeof(struct stp_sstpi));
1524 if (rc == 0 && stp_info.tmd != 2)
1525 rc = -EAGAIN;
1526 }
1527 }
1528 if (rc) {
1529 disable_sync_clock(NULL);
750887de 1530 stp_sync->in_sync = -EAGAIN;
d2fec595 1531 } else
750887de
HC
1532 stp_sync->in_sync = 1;
1533 xchg(&first, 0);
1534 return 0;
1535}
d2fec595 1536
750887de
HC
1537/*
1538 * STP work. Check for the STP state and take over the clock
1539 * synchronization if the STP clock source is usable.
1540 */
1541static void stp_work_fn(struct work_struct *work)
1542{
1543 struct clock_sync_data stp_sync;
1544 int rc;
1545
0b3016b7
MS
1546 /* prevent multiple execution. */
1547 mutex_lock(&stp_work_mutex);
1548
750887de
HC
1549 if (!stp_online) {
1550 chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
04362301 1551 del_timer_sync(&stp_timer);
0b3016b7 1552 goto out_unlock;
750887de
HC
1553 }
1554
1555 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
1556 if (rc)
0b3016b7 1557 goto out_unlock;
750887de
HC
1558
1559 rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
1560 if (rc || stp_info.c == 0)
0b3016b7 1561 goto out_unlock;
750887de 1562
8283cb43
MS
1563 /* Skip synchronization if the clock is already in sync. */
1564 if (check_sync_clock())
1565 goto out_unlock;
1566
750887de
HC
1567 memset(&stp_sync, 0, sizeof(stp_sync));
1568 get_online_cpus();
1569 atomic_set(&stp_sync.cpus, num_online_cpus() - 1);
1570 stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map);
1571 put_online_cpus();
0b3016b7 1572
04362301
MS
1573 if (!check_sync_clock())
1574 /*
1575 * There is a usable clock but the synchonization failed.
1576 * Retry after a second.
1577 */
1578 mod_timer(&stp_timer, jiffies + HZ);
1579
0b3016b7
MS
1580out_unlock:
1581 mutex_unlock(&stp_work_mutex);
d2fec595
MS
1582}
1583
1584/*
1585 * STP class sysfs interface functions
1586 */
1587static struct sysdev_class stp_sysclass = {
1588 .name = "stp",
1589};
1590
c9be0a36
AK
1591static ssize_t stp_ctn_id_show(struct sysdev_class *class,
1592 struct sysdev_class_attribute *attr,
1593 char *buf)
d2fec595
MS
1594{
1595 if (!stp_online)
1596 return -ENODATA;
1597 return sprintf(buf, "%016llx\n",
1598 *(unsigned long long *) stp_info.ctnid);
1599}
1600
1601static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
1602
c9be0a36
AK
1603static ssize_t stp_ctn_type_show(struct sysdev_class *class,
1604 struct sysdev_class_attribute *attr,
1605 char *buf)
d2fec595
MS
1606{
1607 if (!stp_online)
1608 return -ENODATA;
1609 return sprintf(buf, "%i\n", stp_info.ctn);
1610}
1611
1612static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
1613
c9be0a36
AK
1614static ssize_t stp_dst_offset_show(struct sysdev_class *class,
1615 struct sysdev_class_attribute *attr,
1616 char *buf)
d2fec595
MS
1617{
1618 if (!stp_online || !(stp_info.vbits & 0x2000))
1619 return -ENODATA;
1620 return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
1621}
1622
1623static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
1624
c9be0a36
AK
1625static ssize_t stp_leap_seconds_show(struct sysdev_class *class,
1626 struct sysdev_class_attribute *attr,
1627 char *buf)
d2fec595
MS
1628{
1629 if (!stp_online || !(stp_info.vbits & 0x8000))
1630 return -ENODATA;
1631 return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
1632}
1633
1634static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
1635
c9be0a36
AK
1636static ssize_t stp_stratum_show(struct sysdev_class *class,
1637 struct sysdev_class_attribute *attr,
1638 char *buf)
d2fec595
MS
1639{
1640 if (!stp_online)
1641 return -ENODATA;
1642 return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
1643}
1644
1645static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
1646
c9be0a36
AK
1647static ssize_t stp_time_offset_show(struct sysdev_class *class,
1648 struct sysdev_class_attribute *attr,
1649 char *buf)
d2fec595
MS
1650{
1651 if (!stp_online || !(stp_info.vbits & 0x0800))
1652 return -ENODATA;
1653 return sprintf(buf, "%i\n", (int) stp_info.tto);
1654}
1655
1656static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
1657
c9be0a36
AK
1658static ssize_t stp_time_zone_offset_show(struct sysdev_class *class,
1659 struct sysdev_class_attribute *attr,
1660 char *buf)
d2fec595
MS
1661{
1662 if (!stp_online || !(stp_info.vbits & 0x4000))
1663 return -ENODATA;
1664 return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
1665}
1666
1667static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
1668 stp_time_zone_offset_show, NULL);
1669
c9be0a36
AK
1670static ssize_t stp_timing_mode_show(struct sysdev_class *class,
1671 struct sysdev_class_attribute *attr,
1672 char *buf)
d2fec595
MS
1673{
1674 if (!stp_online)
1675 return -ENODATA;
1676 return sprintf(buf, "%i\n", stp_info.tmd);
1677}
1678
1679static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
1680
c9be0a36
AK
1681static ssize_t stp_timing_state_show(struct sysdev_class *class,
1682 struct sysdev_class_attribute *attr,
1683 char *buf)
d2fec595
MS
1684{
1685 if (!stp_online)
1686 return -ENODATA;
1687 return sprintf(buf, "%i\n", stp_info.tst);
1688}
1689
1690static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
1691
c9be0a36
AK
1692static ssize_t stp_online_show(struct sysdev_class *class,
1693 struct sysdev_class_attribute *attr,
1694 char *buf)
d2fec595
MS
1695{
1696 return sprintf(buf, "%i\n", stp_online);
1697}
1698
1699static ssize_t stp_online_store(struct sysdev_class *class,
c9be0a36 1700 struct sysdev_class_attribute *attr,
d2fec595
MS
1701 const char *buf, size_t count)
1702{
1703 unsigned int value;
1704
1705 value = simple_strtoul(buf, NULL, 0);
1706 if (value != 0 && value != 1)
1707 return -EINVAL;
1708 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1709 return -EOPNOTSUPP;
8283cb43 1710 mutex_lock(&clock_sync_mutex);
d2fec595 1711 stp_online = value;
8283cb43
MS
1712 if (stp_online)
1713 set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1714 else
1715 clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
750887de 1716 queue_work(time_sync_wq, &stp_work);
8283cb43 1717 mutex_unlock(&clock_sync_mutex);
d2fec595
MS
1718 return count;
1719}
1720
1721/*
1722 * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
1723 * stp/online but attr_online already exists in this file ..
1724 */
1725static struct sysdev_class_attribute attr_stp_online = {
1726 .attr = { .name = "online", .mode = 0600 },
1727 .show = stp_online_show,
1728 .store = stp_online_store,
1729};
1730
1731static struct sysdev_class_attribute *stp_attributes[] = {
1732 &attr_ctn_id,
1733 &attr_ctn_type,
1734 &attr_dst_offset,
1735 &attr_leap_seconds,
1736 &attr_stp_online,
1737 &attr_stratum,
1738 &attr_time_offset,
1739 &attr_time_zone_offset,
1740 &attr_timing_mode,
1741 &attr_timing_state,
1742 NULL
1743};
1744
1745static int __init stp_init_sysfs(void)
1746{
1747 struct sysdev_class_attribute **attr;
1748 int rc;
1749
1750 rc = sysdev_class_register(&stp_sysclass);
1751 if (rc)
1752 goto out;
1753 for (attr = stp_attributes; *attr; attr++) {
1754 rc = sysdev_class_create_file(&stp_sysclass, *attr);
1755 if (rc)
1756 goto out_unreg;
1757 }
1758 return 0;
1759out_unreg:
1760 for (; attr >= stp_attributes; attr--)
1761 sysdev_class_remove_file(&stp_sysclass, *attr);
1762 sysdev_class_unregister(&stp_sysclass);
1763out:
1764 return rc;
1765}
1766
1767device_initcall(stp_init_sysfs);