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Commit | Line | Data |
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1da177e4 | 1 | /* |
54dfe5dd | 2 | * arch/s390/kernel/entry64.S |
1da177e4 LT |
3 | * S390 low-level entry points. |
4 | * | |
54dfe5dd | 5 | * Copyright (C) IBM Corp. 1999,2006 |
1da177e4 | 6 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), |
25d83cbf HC |
7 | * Hartmut Penner (hp@de.ibm.com), |
8 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
77fa2245 | 9 | * Heiko Carstens <heiko.carstens@de.ibm.com> |
1da177e4 LT |
10 | */ |
11 | ||
12 | #include <linux/sys.h> | |
13 | #include <linux/linkage.h> | |
2bc89b5e | 14 | #include <linux/init.h> |
1da177e4 LT |
15 | #include <asm/cache.h> |
16 | #include <asm/lowcore.h> | |
17 | #include <asm/errno.h> | |
18 | #include <asm/ptrace.h> | |
19 | #include <asm/thread_info.h> | |
0013a854 | 20 | #include <asm/asm-offsets.h> |
1da177e4 LT |
21 | #include <asm/unistd.h> |
22 | #include <asm/page.h> | |
23 | ||
24 | /* | |
25 | * Stack layout for the system_call stack entry. | |
26 | * The first few entries are identical to the user_regs_struct. | |
27 | */ | |
25d83cbf HC |
28 | SP_PTREGS = STACK_FRAME_OVERHEAD |
29 | SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS | |
30 | SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW | |
31 | SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS | |
32 | SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8 | |
33 | SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16 | |
34 | SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24 | |
35 | SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32 | |
36 | SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40 | |
37 | SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48 | |
38 | SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56 | |
39 | SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64 | |
40 | SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72 | |
41 | SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80 | |
42 | SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88 | |
43 | SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96 | |
44 | SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104 | |
45 | SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112 | |
46 | SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120 | |
47 | SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2 | |
48 | SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC | |
49 | SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP | |
50 | SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE | |
1da177e4 LT |
51 | |
52 | STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER | |
53 | STACK_SIZE = 1 << STACK_SHIFT | |
54 | ||
02a029b3 | 55 | _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \ |
54dfe5dd | 56 | _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) |
02a029b3 | 57 | _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \ |
54dfe5dd | 58 | _TIF_MCCK_PENDING) |
1da177e4 LT |
59 | |
60 | #define BASED(name) name-system_call(%r13) | |
61 | ||
1f194a4c HC |
62 | #ifdef CONFIG_TRACE_IRQFLAGS |
63 | .macro TRACE_IRQS_ON | |
64 | brasl %r14,trace_hardirqs_on | |
65 | .endm | |
66 | ||
67 | .macro TRACE_IRQS_OFF | |
68 | brasl %r14,trace_hardirqs_off | |
69 | .endm | |
523b44cf | 70 | |
411788ea HC |
71 | .macro TRACE_IRQS_CHECK |
72 | tm SP_PSW(%r15),0x03 # irqs enabled? | |
73 | jz 0f | |
74 | brasl %r14,trace_hardirqs_on | |
75 | j 1f | |
76 | 0: brasl %r14,trace_hardirqs_off | |
77 | 1: | |
523b44cf | 78 | .endm |
1f194a4c HC |
79 | #else |
80 | #define TRACE_IRQS_ON | |
81 | #define TRACE_IRQS_OFF | |
411788ea HC |
82 | #define TRACE_IRQS_CHECK |
83 | #endif | |
84 | ||
85 | #ifdef CONFIG_LOCKDEP | |
86 | .macro LOCKDEP_SYS_EXIT | |
87 | tm SP_PSW+1(%r15),0x01 # returning to user ? | |
88 | jz 0f | |
89 | brasl %r14,lockdep_sys_exit | |
90 | 0: | |
91 | .endm | |
92 | #else | |
523b44cf | 93 | #define LOCKDEP_SYS_EXIT |
1f194a4c HC |
94 | #endif |
95 | ||
25d83cbf | 96 | .macro STORE_TIMER lc_offset |
1da177e4 LT |
97 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
98 | stpt \lc_offset | |
99 | #endif | |
100 | .endm | |
101 | ||
102 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
25d83cbf | 103 | .macro UPDATE_VTIME lc_from,lc_to,lc_sum |
1da177e4 LT |
104 | lg %r10,\lc_from |
105 | slg %r10,\lc_to | |
106 | alg %r10,\lc_sum | |
107 | stg %r10,\lc_sum | |
108 | .endm | |
109 | #endif | |
110 | ||
111 | /* | |
112 | * Register usage in interrupt handlers: | |
113 | * R9 - pointer to current task structure | |
114 | * R13 - pointer to literal pool | |
115 | * R14 - return register for function calls | |
116 | * R15 - kernel stack pointer | |
117 | */ | |
118 | ||
25d83cbf | 119 | .macro SAVE_ALL_BASE savearea |
1da177e4 LT |
120 | stmg %r12,%r15,\savearea |
121 | larl %r13,system_call | |
122 | .endm | |
123 | ||
987ad70a MS |
124 | .macro SAVE_ALL_SVC psworg,savearea |
125 | la %r12,\psworg | |
126 | lg %r15,__LC_KERNEL_STACK # problem state -> load ksp | |
127 | .endm | |
128 | ||
63b12246 | 129 | .macro SAVE_ALL_SYNC psworg,savearea |
1da177e4 | 130 | la %r12,\psworg |
1da177e4 LT |
131 | tm \psworg+1,0x01 # test problem state bit |
132 | jz 2f # skip stack setup save | |
133 | lg %r15,__LC_KERNEL_STACK # problem state -> load ksp | |
63b12246 MS |
134 | #ifdef CONFIG_CHECK_STACK |
135 | j 3f | |
136 | 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
137 | jz stack_overflow | |
138 | 3: | |
139 | #endif | |
140 | 2: | |
141 | .endm | |
142 | ||
143 | .macro SAVE_ALL_ASYNC psworg,savearea | |
144 | la %r12,\psworg | |
1da177e4 LT |
145 | tm \psworg+1,0x01 # test problem state bit |
146 | jnz 1f # from user -> load kernel stack | |
147 | clc \psworg+8(8),BASED(.Lcritical_end) | |
148 | jhe 0f | |
149 | clc \psworg+8(8),BASED(.Lcritical_start) | |
150 | jl 0f | |
151 | brasl %r14,cleanup_critical | |
6add9f7f | 152 | tm 1(%r12),0x01 # retest problem state after cleanup |
1da177e4 LT |
153 | jnz 1f |
154 | 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ? | |
155 | slgr %r14,%r15 | |
156 | srag %r14,%r14,STACK_SHIFT | |
157 | jz 2f | |
158 | 1: lg %r15,__LC_ASYNC_STACK # load async stack | |
1da177e4 LT |
159 | #ifdef CONFIG_CHECK_STACK |
160 | j 3f | |
161 | 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD | |
162 | jz stack_overflow | |
163 | 3: | |
164 | #endif | |
77fa2245 HC |
165 | 2: |
166 | .endm | |
167 | ||
168 | .macro CREATE_STACK_FRAME psworg,savearea | |
25d83cbf HC |
169 | aghi %r15,-SP_SIZE # make room for registers & psw |
170 | mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack | |
1da177e4 LT |
171 | la %r12,\psworg |
172 | stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2 | |
173 | icm %r12,12,__LC_SVC_ILC | |
174 | stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack | |
175 | st %r12,SP_ILC(%r15) | |
176 | mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack | |
177 | la %r12,0 | |
178 | stg %r12,__SF_BACKCHAIN(%r15) | |
25d83cbf | 179 | .endm |
1da177e4 | 180 | |
ae6aa2ea MS |
181 | .macro RESTORE_ALL psworg,sync |
182 | mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore | |
1da177e4 | 183 | .if !\sync |
ae6aa2ea | 184 | ni \psworg+1,0xfd # clear wait state bit |
1da177e4 LT |
185 | .endif |
186 | lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user | |
187 | STORE_TIMER __LC_EXIT_TIMER | |
ae6aa2ea | 188 | lpswe \psworg # back to caller |
1da177e4 LT |
189 | .endm |
190 | ||
191 | /* | |
192 | * Scheduler resume function, called by switch_to | |
193 | * gpr2 = (task_struct *) prev | |
194 | * gpr3 = (task_struct *) next | |
195 | * Returns: | |
196 | * gpr2 = prev | |
197 | */ | |
25d83cbf | 198 | .globl __switch_to |
1da177e4 LT |
199 | __switch_to: |
200 | tm __THREAD_per+4(%r3),0xe8 # is the new process using per ? | |
201 | jz __switch_to_noper # if not we're fine | |
25d83cbf HC |
202 | stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff |
203 | clc __THREAD_per(24,%r3),__SF_EMPTY(%r15) | |
204 | je __switch_to_noper # we got away without bashing TLB's | |
205 | lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't | |
1da177e4 | 206 | __switch_to_noper: |
25d83cbf | 207 | lg %r4,__THREAD_info(%r2) # get thread_info of prev |
77fa2245 HC |
208 | tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending? |
209 | jz __switch_to_no_mcck | |
210 | ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev | |
211 | lg %r4,__THREAD_info(%r3) # get thread_info of next | |
212 | oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next | |
213 | __switch_to_no_mcck: | |
25d83cbf | 214 | stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task |
1da177e4 LT |
215 | stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp |
216 | lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp | |
25d83cbf | 217 | lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task |
1da177e4 LT |
218 | stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct |
219 | lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 | |
25d83cbf | 220 | lg %r3,__THREAD_info(%r3) # load thread_info from task struct |
1da177e4 LT |
221 | stg %r3,__LC_THREAD_INFO |
222 | aghi %r3,STACK_SIZE | |
223 | stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack | |
224 | br %r14 | |
225 | ||
226 | __critical_start: | |
227 | /* | |
228 | * SVC interrupt handler routine. System calls are synchronous events and | |
229 | * are executed with interrupts enabled. | |
230 | */ | |
231 | ||
25d83cbf | 232 | .globl system_call |
1da177e4 LT |
233 | system_call: |
234 | STORE_TIMER __LC_SYNC_ENTER_TIMER | |
235 | sysc_saveall: | |
236 | SAVE_ALL_BASE __LC_SAVE_AREA | |
987ad70a | 237 | SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
25d83cbf HC |
238 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
239 | llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore | |
1da177e4 LT |
240 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
241 | sysc_vtime: | |
1da177e4 LT |
242 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER |
243 | sysc_stime: | |
244 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
245 | sysc_update: | |
246 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
247 | #endif | |
248 | sysc_do_svc: | |
249 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
25d83cbf | 250 | slag %r7,%r7,2 # *4 and test for svc 0 |
1da177e4 LT |
251 | jnz sysc_nr_ok |
252 | # svc 0: system call number in %r1 | |
253 | cl %r1,BASED(.Lnr_syscalls) | |
254 | jnl sysc_nr_ok | |
25d83cbf HC |
255 | lgfr %r7,%r1 # clear high word in r1 |
256 | slag %r7,%r7,2 # svc 0: system call number in %r1 | |
1da177e4 LT |
257 | sysc_nr_ok: |
258 | mvc SP_ARGS(8,%r15),SP_R7(%r15) | |
259 | sysc_do_restart: | |
25d83cbf | 260 | larl %r10,sys_call_table |
347a8dc3 | 261 | #ifdef CONFIG_COMPAT |
c563077e HC |
262 | tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ? |
263 | jno sysc_noemu | |
25d83cbf | 264 | larl %r10,sys_call_table_emu # use 31 bit emulation system calls |
1da177e4 LT |
265 | sysc_noemu: |
266 | #endif | |
267 | tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) | |
25d83cbf HC |
268 | lgf %r8,0(%r7,%r10) # load address of system call routine |
269 | jnz sysc_tracesys | |
270 | basr %r14,%r8 # call sys_xxxx | |
271 | stg %r2,SP_R2(%r15) # store return value (change R2 on stack) | |
1da177e4 LT |
272 | |
273 | sysc_return: | |
25d83cbf | 274 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
411788ea | 275 | jno sysc_restore |
1da177e4 | 276 | tm __TI_flags+7(%r9),_TIF_WORK_SVC |
25d83cbf | 277 | jnz sysc_work # there is work to do (signals etc.) |
411788ea HC |
278 | sysc_restore: |
279 | #ifdef CONFIG_TRACE_IRQFLAGS | |
280 | larl %r1,sysc_restore_trace_psw | |
281 | lpswe 0(%r1) | |
282 | sysc_restore_trace: | |
283 | TRACE_IRQS_CHECK | |
523b44cf | 284 | LOCKDEP_SYS_EXIT |
411788ea | 285 | #endif |
1da177e4 | 286 | sysc_leave: |
25d83cbf | 287 | RESTORE_ALL __LC_RETURN_PSW,1 |
411788ea HC |
288 | sysc_done: |
289 | ||
290 | #ifdef CONFIG_TRACE_IRQFLAGS | |
291 | .align 8 | |
292 | .globl sysc_restore_trace_psw | |
293 | sysc_restore_trace_psw: | |
294 | .quad 0, sysc_restore_trace | |
295 | #endif | |
1da177e4 LT |
296 | |
297 | # | |
298 | # recheck if there is more work to do | |
299 | # | |
300 | sysc_work_loop: | |
301 | tm __TI_flags+7(%r9),_TIF_WORK_SVC | |
411788ea | 302 | jz sysc_restore # there is no work to do |
1da177e4 LT |
303 | # |
304 | # One of the work bits is on. Find out which one. | |
305 | # | |
306 | sysc_work: | |
77fa2245 HC |
307 | tm __TI_flags+7(%r9),_TIF_MCCK_PENDING |
308 | jo sysc_mcck_pending | |
1da177e4 LT |
309 | tm __TI_flags+7(%r9),_TIF_NEED_RESCHED |
310 | jo sysc_reschedule | |
02a029b3 | 311 | tm __TI_flags+7(%r9),_TIF_SIGPENDING |
54dfe5dd | 312 | jnz sysc_sigpending |
1da177e4 LT |
313 | tm __TI_flags+7(%r9),_TIF_RESTART_SVC |
314 | jo sysc_restart | |
315 | tm __TI_flags+7(%r9),_TIF_SINGLE_STEP | |
316 | jo sysc_singlestep | |
411788ea HC |
317 | j sysc_restore |
318 | sysc_work_done: | |
1da177e4 LT |
319 | |
320 | # | |
321 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
322 | # |
323 | sysc_reschedule: | |
324 | larl %r14,sysc_work_loop | |
325 | jg schedule # return point is sysc_return | |
1da177e4 | 326 | |
77fa2245 HC |
327 | # |
328 | # _TIF_MCCK_PENDING is set, call handler | |
329 | # | |
330 | sysc_mcck_pending: | |
331 | larl %r14,sysc_work_loop | |
25d83cbf | 332 | jg s390_handle_mcck # TIF bit will be cleared by handler |
77fa2245 | 333 | |
1da177e4 | 334 | # |
02a029b3 | 335 | # _TIF_SIGPENDING is set, call do_signal |
1da177e4 | 336 | # |
25d83cbf | 337 | sysc_sigpending: |
1da177e4 | 338 | ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP |
25d83cbf HC |
339 | la %r2,SP_PTREGS(%r15) # load pt_regs |
340 | brasl %r14,do_signal # call do_signal | |
1da177e4 LT |
341 | tm __TI_flags+7(%r9),_TIF_RESTART_SVC |
342 | jo sysc_restart | |
343 | tm __TI_flags+7(%r9),_TIF_SINGLE_STEP | |
344 | jo sysc_singlestep | |
e1c3ad96 | 345 | j sysc_work_loop |
1da177e4 LT |
346 | |
347 | # | |
348 | # _TIF_RESTART_SVC is set, set up registers and restart svc | |
349 | # | |
350 | sysc_restart: | |
351 | ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC | |
25d83cbf HC |
352 | lg %r7,SP_R2(%r15) # load new svc number |
353 | slag %r7,%r7,2 # *4 | |
1da177e4 | 354 | mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument |
25d83cbf HC |
355 | lmg %r2,%r6,SP_R2(%r15) # load svc arguments |
356 | j sysc_do_restart # restart svc | |
1da177e4 LT |
357 | |
358 | # | |
359 | # _TIF_SINGLE_STEP is set, call do_single_step | |
360 | # | |
361 | sysc_singlestep: | |
362 | ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP | |
363 | lhi %r0,__LC_PGM_OLD_PSW | |
364 | sth %r0,SP_TRAP(%r15) # set trap indication to pgm check | |
365 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
366 | larl %r14,sysc_return # load adr. of system return | |
367 | jg do_single_step # branch to do_sigtrap | |
368 | ||
1da177e4 LT |
369 | # |
370 | # call syscall_trace before and after system call | |
371 | # special linkage: %r12 contains the return address for trace_svc | |
372 | # | |
373 | sysc_tracesys: | |
25d83cbf | 374 | la %r2,SP_PTREGS(%r15) # load pt_regs |
1da177e4 LT |
375 | la %r3,0 |
376 | srl %r7,2 | |
25d83cbf HC |
377 | stg %r7,SP_R2(%r15) |
378 | brasl %r14,syscall_trace | |
1da177e4 LT |
379 | lghi %r0,NR_syscalls |
380 | clg %r0,SP_R2(%r15) | |
381 | jnh sysc_tracenogo | |
25d83cbf HC |
382 | lg %r7,SP_R2(%r15) # strace might have changed the |
383 | sll %r7,2 # system call | |
1da177e4 LT |
384 | lgf %r8,0(%r7,%r10) |
385 | sysc_tracego: | |
25d83cbf HC |
386 | lmg %r3,%r6,SP_R3(%r15) |
387 | lg %r2,SP_ORIG_R2(%r15) | |
388 | basr %r14,%r8 # call sys_xxx | |
389 | stg %r2,SP_R2(%r15) # store return value | |
1da177e4 LT |
390 | sysc_tracenogo: |
391 | tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) | |
25d83cbf HC |
392 | jz sysc_return |
393 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 | 394 | la %r3,1 |
25d83cbf | 395 | larl %r14,sysc_return # return point is sysc_return |
1da177e4 LT |
396 | jg syscall_trace |
397 | ||
398 | # | |
399 | # a new process exits the kernel with ret_from_fork | |
400 | # | |
25d83cbf | 401 | .globl ret_from_fork |
1da177e4 LT |
402 | ret_from_fork: |
403 | lg %r13,__LC_SVC_NEW_PSW+8 | |
404 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
405 | tm SP_PSW+1(%r15),0x01 # forking a kernel thread ? | |
406 | jo 0f | |
407 | stg %r15,SP_R15(%r15) # store stack pointer for new kthread | |
25d83cbf | 408 | 0: brasl %r14,schedule_tail |
1f194a4c | 409 | TRACE_IRQS_ON |
25d83cbf | 410 | stosm 24(%r15),0x03 # reenable interrupts |
1da177e4 LT |
411 | j sysc_return |
412 | ||
413 | # | |
03ff9a23 MS |
414 | # kernel_execve function needs to deal with pt_regs that is not |
415 | # at the usual place | |
1da177e4 | 416 | # |
03ff9a23 MS |
417 | .globl kernel_execve |
418 | kernel_execve: | |
419 | stmg %r12,%r15,96(%r15) | |
420 | lgr %r14,%r15 | |
421 | aghi %r15,-SP_SIZE | |
422 | stg %r14,__SF_BACKCHAIN(%r15) | |
423 | la %r12,SP_PTREGS(%r15) | |
424 | xc 0(__PT_SIZE,%r12),0(%r12) | |
425 | lgr %r5,%r12 | |
426 | brasl %r14,do_execve | |
427 | ltgfr %r2,%r2 | |
428 | je 0f | |
429 | aghi %r15,SP_SIZE | |
430 | lmg %r12,%r15,96(%r15) | |
431 | br %r14 | |
432 | # execve succeeded. | |
433 | 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts | |
434 | lg %r15,__LC_KERNEL_STACK # load ksp | |
435 | aghi %r15,-SP_SIZE # make room for registers & psw | |
436 | lg %r13,__LC_SVC_NEW_PSW+8 | |
437 | lg %r9,__LC_THREAD_INFO | |
438 | mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs | |
439 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) | |
440 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts | |
441 | brasl %r14,execve_tail | |
442 | j sysc_return | |
1da177e4 LT |
443 | |
444 | /* | |
445 | * Program check handler routine | |
446 | */ | |
447 | ||
25d83cbf | 448 | .globl pgm_check_handler |
1da177e4 LT |
449 | pgm_check_handler: |
450 | /* | |
451 | * First we need to check for a special case: | |
452 | * Single stepping an instruction that disables the PER event mask will | |
453 | * cause a PER event AFTER the mask has been set. Example: SVC or LPSW. | |
454 | * For a single stepped SVC the program check handler gets control after | |
455 | * the SVC new PSW has been loaded. But we want to execute the SVC first and | |
456 | * then handle the PER event. Therefore we update the SVC old PSW to point | |
457 | * to the pgm_check_handler and branch to the SVC handler after we checked | |
458 | * if we have to load the kernel stack register. | |
459 | * For every other possible cause for PER event without the PER mask set | |
460 | * we just ignore the PER event (FIXME: is there anything we have to do | |
461 | * for LPSW?). | |
462 | */ | |
463 | STORE_TIMER __LC_SYNC_ENTER_TIMER | |
464 | SAVE_ALL_BASE __LC_SAVE_AREA | |
25d83cbf HC |
465 | tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception |
466 | jnz pgm_per # got per exception -> special case | |
63b12246 | 467 | SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 468 | CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
469 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
470 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
471 | jz pgm_no_vtime | |
472 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
473 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
474 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
475 | pgm_no_vtime: | |
476 | #endif | |
477 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
9e74a6b8 | 478 | mvc SP_ARGS(8,%r15),__LC_LAST_BREAK |
411788ea | 479 | TRACE_IRQS_OFF |
25d83cbf | 480 | lgf %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 LT |
481 | lghi %r8,0x7f |
482 | ngr %r8,%r3 | |
483 | pgm_do_call: | |
25d83cbf HC |
484 | sll %r8,3 |
485 | larl %r1,pgm_check_table | |
486 | lg %r1,0(%r8,%r1) # load address of handler routine | |
487 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
1da177e4 | 488 | larl %r14,sysc_return |
25d83cbf | 489 | br %r1 # branch to interrupt-handler |
1da177e4 LT |
490 | |
491 | # | |
492 | # handle per exception | |
493 | # | |
494 | pgm_per: | |
25d83cbf HC |
495 | tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on |
496 | jnz pgm_per_std # ok, normal per event from user space | |
1da177e4 | 497 | # ok its one of the special cases, now we need to find out which one |
25d83cbf HC |
498 | clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW |
499 | je pgm_svcper | |
1da177e4 LT |
500 | # no interesting special case, ignore PER event |
501 | lmg %r12,%r15,__LC_SAVE_AREA | |
25d83cbf | 502 | lpswe __LC_PGM_OLD_PSW |
1da177e4 LT |
503 | |
504 | # | |
505 | # Normal per exception | |
506 | # | |
507 | pgm_per_std: | |
63b12246 | 508 | SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 509 | CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA |
1da177e4 LT |
510 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
511 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
512 | jz pgm_no_vtime2 | |
513 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER | |
514 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
515 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
516 | pgm_no_vtime2: | |
517 | #endif | |
518 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
411788ea | 519 | TRACE_IRQS_OFF |
1da177e4 | 520 | lg %r1,__TI_task(%r9) |
4ba069b8 MG |
521 | tm SP_PSW+1(%r15),0x01 # kernel per event ? |
522 | jz kernel_per | |
1da177e4 LT |
523 | mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID |
524 | mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS | |
525 | mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID | |
526 | oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP | |
25d83cbf | 527 | lgf %r3,__LC_PGM_ILC # load program interruption code |
1da177e4 | 528 | lghi %r8,0x7f |
25d83cbf | 529 | ngr %r8,%r3 # clear per-event-bit and ilc |
1da177e4 LT |
530 | je sysc_return |
531 | j pgm_do_call | |
532 | ||
533 | # | |
534 | # it was a single stepped SVC that is causing all the trouble | |
535 | # | |
536 | pgm_svcper: | |
63b12246 | 537 | SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 538 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
1da177e4 | 539 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
1da177e4 LT |
540 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER |
541 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
542 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
1da177e4 | 543 | #endif |
25d83cbf | 544 | llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore |
1da177e4 LT |
545 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct |
546 | lg %r1,__TI_task(%r9) | |
547 | mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID | |
548 | mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS | |
549 | mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID | |
550 | oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP | |
1f194a4c | 551 | TRACE_IRQS_ON |
1da177e4 LT |
552 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
553 | j sysc_do_svc | |
554 | ||
4ba069b8 MG |
555 | # |
556 | # per was called from kernel, must be kprobes | |
557 | # | |
558 | kernel_per: | |
559 | lhi %r0,__LC_PGM_OLD_PSW | |
560 | sth %r0,SP_TRAP(%r15) # set trap indication to pgm check | |
561 | la %r2,SP_PTREGS(%r15) # address of register-save area | |
411788ea | 562 | larl %r14,sysc_restore # load adr. of system ret, no work |
4ba069b8 MG |
563 | jg do_single_step # branch to do_single_step |
564 | ||
1da177e4 LT |
565 | /* |
566 | * IO interrupt handler routine | |
567 | */ | |
25d83cbf | 568 | .globl io_int_handler |
1da177e4 LT |
569 | io_int_handler: |
570 | STORE_TIMER __LC_ASYNC_ENTER_TIMER | |
571 | stck __LC_INT_CLOCK | |
572 | SAVE_ALL_BASE __LC_SAVE_AREA+32 | |
63b12246 | 573 | SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32 |
77fa2245 | 574 | CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32 |
1da177e4 LT |
575 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
576 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
577 | jz io_no_vtime | |
578 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
579 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
580 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
581 | io_no_vtime: | |
582 | #endif | |
583 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
1f194a4c | 584 | TRACE_IRQS_OFF |
25d83cbf HC |
585 | la %r2,SP_PTREGS(%r15) # address of register-save area |
586 | brasl %r14,do_IRQ # call standard irq handler | |
1da177e4 | 587 | io_return: |
25d83cbf | 588 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
1da177e4 | 589 | #ifdef CONFIG_PREEMPT |
25d83cbf | 590 | jno io_preempt # no -> check for preemptive scheduling |
1da177e4 | 591 | #else |
411788ea | 592 | jno io_restore # no-> skip resched & signal |
1da177e4 LT |
593 | #endif |
594 | tm __TI_flags+7(%r9),_TIF_WORK_INT | |
25d83cbf | 595 | jnz io_work # there is work to do (signals etc.) |
411788ea HC |
596 | io_restore: |
597 | #ifdef CONFIG_TRACE_IRQFLAGS | |
598 | larl %r1,io_restore_trace_psw | |
599 | lpswe 0(%r1) | |
600 | io_restore_trace: | |
601 | TRACE_IRQS_CHECK | |
523b44cf | 602 | LOCKDEP_SYS_EXIT |
411788ea | 603 | #endif |
1da177e4 | 604 | io_leave: |
25d83cbf | 605 | RESTORE_ALL __LC_RETURN_PSW,0 |
ae6aa2ea | 606 | io_done: |
1da177e4 | 607 | |
411788ea HC |
608 | #ifdef CONFIG_TRACE_IRQFLAGS |
609 | .align 8 | |
610 | .globl io_restore_trace_psw | |
611 | io_restore_trace_psw: | |
612 | .quad 0, io_restore_trace | |
613 | #endif | |
614 | ||
1da177e4 LT |
615 | #ifdef CONFIG_PREEMPT |
616 | io_preempt: | |
25d83cbf | 617 | icm %r0,15,__TI_precount(%r9) |
411788ea | 618 | jnz io_restore |
1da177e4 LT |
619 | # switch to kernel stack |
620 | lg %r1,SP_R15(%r15) | |
621 | aghi %r1,-SP_SIZE | |
622 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 623 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 LT |
624 | lgr %r15,%r1 |
625 | io_resume_loop: | |
626 | tm __TI_flags+7(%r9),_TIF_NEED_RESCHED | |
411788ea | 627 | jno io_restore |
b8e7a54c HC |
628 | larl %r14,io_resume_loop |
629 | jg preempt_schedule_irq | |
1da177e4 LT |
630 | #endif |
631 | ||
632 | # | |
633 | # switch to kernel stack, then check TIF bits | |
634 | # | |
635 | io_work: | |
636 | lg %r1,__LC_KERNEL_STACK | |
637 | aghi %r1,-SP_SIZE | |
638 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
25d83cbf | 639 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain |
1da177e4 LT |
640 | lgr %r15,%r1 |
641 | # | |
642 | # One of the work bits is on. Find out which one. | |
54dfe5dd HC |
643 | # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED |
644 | # and _TIF_MCCK_PENDING | |
1da177e4 LT |
645 | # |
646 | io_work_loop: | |
77fa2245 HC |
647 | tm __TI_flags+7(%r9),_TIF_MCCK_PENDING |
648 | jo io_mcck_pending | |
1da177e4 LT |
649 | tm __TI_flags+7(%r9),_TIF_NEED_RESCHED |
650 | jo io_reschedule | |
02a029b3 | 651 | tm __TI_flags+7(%r9),_TIF_SIGPENDING |
54dfe5dd | 652 | jnz io_sigpending |
411788ea HC |
653 | j io_restore |
654 | io_work_done: | |
1da177e4 | 655 | |
77fa2245 HC |
656 | # |
657 | # _TIF_MCCK_PENDING is set, call handler | |
658 | # | |
659 | io_mcck_pending: | |
b771aeac | 660 | brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler |
b771aeac | 661 | j io_work_loop |
77fa2245 | 662 | |
1da177e4 LT |
663 | # |
664 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf HC |
665 | # |
666 | io_reschedule: | |
411788ea | 667 | TRACE_IRQS_ON |
25d83cbf HC |
668 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
669 | brasl %r14,schedule # call scheduler | |
670 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts | |
411788ea | 671 | TRACE_IRQS_OFF |
1da177e4 | 672 | tm __TI_flags+7(%r9),_TIF_WORK_INT |
411788ea | 673 | jz io_restore # there is no work to do |
1da177e4 LT |
674 | j io_work_loop |
675 | ||
676 | # | |
02a029b3 | 677 | # _TIF_SIGPENDING or is set, call do_signal |
1da177e4 | 678 | # |
25d83cbf | 679 | io_sigpending: |
411788ea | 680 | TRACE_IRQS_ON |
25d83cbf HC |
681 | stosm __SF_EMPTY(%r15),0x03 # reenable interrupts |
682 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 | 683 | brasl %r14,do_signal # call do_signal |
25d83cbf | 684 | stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts |
411788ea | 685 | TRACE_IRQS_OFF |
e1c3ad96 | 686 | j io_work_loop |
1da177e4 LT |
687 | |
688 | /* | |
689 | * External interrupt handler routine | |
690 | */ | |
25d83cbf | 691 | .globl ext_int_handler |
1da177e4 LT |
692 | ext_int_handler: |
693 | STORE_TIMER __LC_ASYNC_ENTER_TIMER | |
694 | stck __LC_INT_CLOCK | |
695 | SAVE_ALL_BASE __LC_SAVE_AREA+32 | |
63b12246 | 696 | SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32 |
77fa2245 | 697 | CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32 |
1da177e4 LT |
698 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
699 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? | |
700 | jz ext_no_vtime | |
701 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
702 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
703 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
704 | ext_no_vtime: | |
705 | #endif | |
706 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct | |
1f194a4c | 707 | TRACE_IRQS_OFF |
25d83cbf HC |
708 | la %r2,SP_PTREGS(%r15) # address of register-save area |
709 | llgh %r3,__LC_EXT_INT_CODE # get interruption code | |
710 | brasl %r14,do_extint | |
1da177e4 LT |
711 | j io_return |
712 | ||
ae6aa2ea MS |
713 | __critical_end: |
714 | ||
1da177e4 LT |
715 | /* |
716 | * Machine check handler routines | |
717 | */ | |
25d83cbf | 718 | .globl mcck_int_handler |
1da177e4 | 719 | mcck_int_handler: |
77fa2245 HC |
720 | la %r1,4095 # revalidate r1 |
721 | spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer | |
25d83cbf | 722 | lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs |
1da177e4 | 723 | SAVE_ALL_BASE __LC_SAVE_AREA+64 |
77fa2245 | 724 | la %r12,__LC_MCK_OLD_PSW |
25d83cbf | 725 | tm __LC_MCCK_CODE,0x80 # system damage? |
77fa2245 | 726 | jo mcck_int_main # yes -> rest of mcck code invalid |
1da177e4 | 727 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
63b12246 MS |
728 | la %r14,4095 |
729 | mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER | |
730 | mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14) | |
731 | tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid? | |
732 | jo 1f | |
733 | la %r14,__LC_SYNC_ENTER_TIMER | |
734 | clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER | |
735 | jl 0f | |
736 | la %r14,__LC_ASYNC_ENTER_TIMER | |
737 | 0: clc 0(8,%r14),__LC_EXIT_TIMER | |
738 | jl 0f | |
739 | la %r14,__LC_EXIT_TIMER | |
740 | 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER | |
741 | jl 0f | |
742 | la %r14,__LC_LAST_UPDATE_TIMER | |
743 | 0: spt 0(%r14) | |
744 | mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14) | |
745 | 1: | |
1da177e4 | 746 | #endif |
63b12246 | 747 | tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid? |
77fa2245 | 748 | jno mcck_int_main # no -> skip cleanup critical |
25d83cbf | 749 | tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit |
77fa2245 HC |
750 | jnz mcck_int_main # from user -> load kernel stack |
751 | clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end) | |
752 | jhe mcck_int_main | |
25d83cbf | 753 | clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start) |
77fa2245 | 754 | jl mcck_int_main |
25d83cbf | 755 | brasl %r14,cleanup_critical |
77fa2245 | 756 | mcck_int_main: |
25d83cbf | 757 | lg %r14,__LC_PANIC_STACK # are we already on the panic stack? |
77fa2245 HC |
758 | slgr %r14,%r15 |
759 | srag %r14,%r14,PAGE_SHIFT | |
760 | jz 0f | |
25d83cbf | 761 | lg %r15,__LC_PANIC_STACK # load panic stack |
77fa2245 | 762 | 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64 |
ae6aa2ea MS |
763 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
764 | tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid? | |
765 | jno mcck_no_vtime # no -> no timer update | |
63b12246 | 766 | tm SP_PSW+1(%r15),0x01 # interrupting from user ? |
ae6aa2ea MS |
767 | jz mcck_no_vtime |
768 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER | |
769 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
770 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
771 | mcck_no_vtime: | |
772 | #endif | |
77fa2245 HC |
773 | lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct |
774 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
775 | brasl %r14,s390_do_machine_check | |
25d83cbf | 776 | tm SP_PSW+1(%r15),0x01 # returning to user ? |
77fa2245 HC |
777 | jno mcck_return |
778 | lg %r1,__LC_KERNEL_STACK # switch to kernel stack | |
779 | aghi %r1,-SP_SIZE | |
780 | mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15) | |
781 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain | |
782 | lgr %r15,%r1 | |
783 | stosm __SF_EMPTY(%r15),0x04 # turn dat on | |
784 | tm __TI_flags+7(%r9),_TIF_MCCK_PENDING | |
785 | jno mcck_return | |
1f194a4c | 786 | TRACE_IRQS_OFF |
77fa2245 | 787 | brasl %r14,s390_handle_mcck |
1f194a4c | 788 | TRACE_IRQS_ON |
1da177e4 | 789 | mcck_return: |
63b12246 MS |
790 | mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW |
791 | ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit | |
792 | lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 | |
793 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
794 | mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104 | |
795 | tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ? | |
796 | jno 0f | |
797 | stpt __LC_EXIT_TIMER | |
798 | 0: | |
799 | #endif | |
800 | lpswe __LC_RETURN_MCCK_PSW # back to caller | |
1da177e4 | 801 | |
1da177e4 LT |
802 | /* |
803 | * Restart interruption handler, kick starter for additional CPUs | |
804 | */ | |
84b36a8e | 805 | #ifdef CONFIG_SMP |
2bc89b5e | 806 | __CPUINIT |
25d83cbf | 807 | .globl restart_int_handler |
1da177e4 | 808 | restart_int_handler: |
25d83cbf HC |
809 | lg %r15,__LC_SAVE_AREA+120 # load ksp |
810 | lghi %r10,__LC_CREGS_SAVE_AREA | |
811 | lctlg %c0,%c15,0(%r10) # get new ctl regs | |
812 | lghi %r10,__LC_AREGS_SAVE_AREA | |
813 | lam %a0,%a15,0(%r10) | |
814 | lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone | |
815 | stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on | |
816 | jg start_secondary | |
84b36a8e | 817 | .previous |
1da177e4 LT |
818 | #else |
819 | /* | |
820 | * If we do not run with SMP enabled, let the new CPU crash ... | |
821 | */ | |
25d83cbf | 822 | .globl restart_int_handler |
1da177e4 | 823 | restart_int_handler: |
25d83cbf | 824 | basr %r1,0 |
1da177e4 | 825 | restart_base: |
25d83cbf HC |
826 | lpswe restart_crash-restart_base(%r1) |
827 | .align 8 | |
1da177e4 | 828 | restart_crash: |
25d83cbf | 829 | .long 0x000a0000,0x00000000,0x00000000,0x00000000 |
1da177e4 LT |
830 | restart_go: |
831 | #endif | |
832 | ||
833 | #ifdef CONFIG_CHECK_STACK | |
834 | /* | |
835 | * The synchronous or the asynchronous stack overflowed. We are dead. | |
836 | * No need to properly save the registers, we are going to panic anyway. | |
837 | * Setup a pt_regs so that show_trace can provide a good call trace. | |
838 | */ | |
839 | stack_overflow: | |
840 | lg %r15,__LC_PANIC_STACK # change to panic stack | |
9514e231 | 841 | aghi %r15,-SP_SIZE |
1da177e4 LT |
842 | mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack |
843 | stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack | |
844 | la %r1,__LC_SAVE_AREA | |
845 | chi %r12,__LC_SVC_OLD_PSW | |
846 | je 0f | |
847 | chi %r12,__LC_PGM_OLD_PSW | |
848 | je 0f | |
9514e231 | 849 | la %r1,__LC_SAVE_AREA+32 |
25d83cbf | 850 | 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack |
9e74a6b8 | 851 | mvc SP_ARGS(8,%r15),__LC_LAST_BREAK |
25d83cbf HC |
852 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain |
853 | la %r2,SP_PTREGS(%r15) # load pt_regs | |
1da177e4 LT |
854 | jg kernel_stack_overflow |
855 | #endif | |
856 | ||
857 | cleanup_table_system_call: | |
858 | .quad system_call, sysc_do_svc | |
859 | cleanup_table_sysc_return: | |
860 | .quad sysc_return, sysc_leave | |
861 | cleanup_table_sysc_leave: | |
411788ea | 862 | .quad sysc_leave, sysc_done |
1da177e4 | 863 | cleanup_table_sysc_work_loop: |
411788ea | 864 | .quad sysc_work_loop, sysc_work_done |
63b12246 MS |
865 | cleanup_table_io_return: |
866 | .quad io_return, io_leave | |
ae6aa2ea MS |
867 | cleanup_table_io_leave: |
868 | .quad io_leave, io_done | |
869 | cleanup_table_io_work_loop: | |
411788ea | 870 | .quad io_work_loop, io_work_done |
1da177e4 LT |
871 | |
872 | cleanup_critical: | |
873 | clc 8(8,%r12),BASED(cleanup_table_system_call) | |
874 | jl 0f | |
875 | clc 8(8,%r12),BASED(cleanup_table_system_call+8) | |
876 | jl cleanup_system_call | |
877 | 0: | |
878 | clc 8(8,%r12),BASED(cleanup_table_sysc_return) | |
879 | jl 0f | |
880 | clc 8(8,%r12),BASED(cleanup_table_sysc_return+8) | |
881 | jl cleanup_sysc_return | |
882 | 0: | |
883 | clc 8(8,%r12),BASED(cleanup_table_sysc_leave) | |
884 | jl 0f | |
885 | clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8) | |
886 | jl cleanup_sysc_leave | |
887 | 0: | |
888 | clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop) | |
889 | jl 0f | |
890 | clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8) | |
77fa2245 | 891 | jl cleanup_sysc_return |
63b12246 MS |
892 | 0: |
893 | clc 8(8,%r12),BASED(cleanup_table_io_return) | |
894 | jl 0f | |
895 | clc 8(8,%r12),BASED(cleanup_table_io_return+8) | |
896 | jl cleanup_io_return | |
ae6aa2ea MS |
897 | 0: |
898 | clc 8(8,%r12),BASED(cleanup_table_io_leave) | |
899 | jl 0f | |
900 | clc 8(8,%r12),BASED(cleanup_table_io_leave+8) | |
901 | jl cleanup_io_leave | |
902 | 0: | |
903 | clc 8(8,%r12),BASED(cleanup_table_io_work_loop) | |
904 | jl 0f | |
905 | clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8) | |
906 | jl cleanup_io_return | |
1da177e4 LT |
907 | 0: |
908 | br %r14 | |
909 | ||
910 | cleanup_system_call: | |
911 | mvc __LC_RETURN_PSW(16),0(%r12) | |
ae6aa2ea MS |
912 | cghi %r12,__LC_MCK_OLD_PSW |
913 | je 0f | |
914 | la %r12,__LC_SAVE_AREA+32 | |
915 | j 1f | |
916 | 0: la %r12,__LC_SAVE_AREA+64 | |
917 | 1: | |
1da177e4 LT |
918 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
919 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8) | |
920 | jh 0f | |
921 | mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
922 | 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16) | |
923 | jhe cleanup_vtime | |
924 | #endif | |
925 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn) | |
926 | jh 0f | |
ae6aa2ea MS |
927 | mvc __LC_SAVE_AREA(32),0(%r12) |
928 | 0: stg %r13,8(%r12) | |
929 | stg %r12,__LC_SAVE_AREA+96 # argh | |
63b12246 | 930 | SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
77fa2245 | 931 | CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA |
ae6aa2ea MS |
932 | lg %r12,__LC_SAVE_AREA+96 # argh |
933 | stg %r15,24(%r12) | |
1da177e4 LT |
934 | llgh %r7,__LC_SVC_INT_CODE |
935 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
936 | cleanup_vtime: | |
937 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24) | |
938 | jhe cleanup_stime | |
1da177e4 LT |
939 | UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER |
940 | cleanup_stime: | |
941 | clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32) | |
942 | jh cleanup_update | |
943 | UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER | |
944 | cleanup_update: | |
945 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER | |
1da177e4 LT |
946 | #endif |
947 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8) | |
948 | la %r12,__LC_RETURN_PSW | |
949 | br %r14 | |
950 | cleanup_system_call_insn: | |
951 | .quad sysc_saveall | |
952 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
25d83cbf HC |
953 | .quad system_call |
954 | .quad sysc_vtime | |
955 | .quad sysc_stime | |
956 | .quad sysc_update | |
1da177e4 LT |
957 | #endif |
958 | ||
959 | cleanup_sysc_return: | |
960 | mvc __LC_RETURN_PSW(8),0(%r12) | |
961 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return) | |
962 | la %r12,__LC_RETURN_PSW | |
963 | br %r14 | |
964 | ||
965 | cleanup_sysc_leave: | |
966 | clc 8(8,%r12),BASED(cleanup_sysc_leave_insn) | |
ae6aa2ea | 967 | je 2f |
1da177e4 LT |
968 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
969 | mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
970 | clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8) | |
ae6aa2ea | 971 | je 2f |
1da177e4 LT |
972 | #endif |
973 | mvc __LC_RETURN_PSW(16),SP_PSW(%r15) | |
ae6aa2ea MS |
974 | cghi %r12,__LC_MCK_OLD_PSW |
975 | jne 0f | |
976 | mvc __LC_SAVE_AREA+64(32),SP_R12(%r15) | |
977 | j 1f | |
978 | 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15) | |
979 | 1: lmg %r0,%r11,SP_R0(%r15) | |
1da177e4 | 980 | lg %r15,SP_R15(%r15) |
ae6aa2ea | 981 | 2: la %r12,__LC_RETURN_PSW |
1da177e4 LT |
982 | br %r14 |
983 | cleanup_sysc_leave_insn: | |
411788ea | 984 | .quad sysc_done - 4 |
1da177e4 | 985 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
411788ea | 986 | .quad sysc_done - 8 |
1da177e4 | 987 | #endif |
1da177e4 | 988 | |
ae6aa2ea MS |
989 | cleanup_io_return: |
990 | mvc __LC_RETURN_PSW(8),0(%r12) | |
991 | mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop) | |
992 | la %r12,__LC_RETURN_PSW | |
993 | br %r14 | |
994 | ||
995 | cleanup_io_leave: | |
996 | clc 8(8,%r12),BASED(cleanup_io_leave_insn) | |
997 | je 2f | |
998 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
999 | mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
1000 | clc 8(8,%r12),BASED(cleanup_io_leave_insn+8) | |
1001 | je 2f | |
1002 | #endif | |
1003 | mvc __LC_RETURN_PSW(16),SP_PSW(%r15) | |
1004 | cghi %r12,__LC_MCK_OLD_PSW | |
1005 | jne 0f | |
1006 | mvc __LC_SAVE_AREA+64(32),SP_R12(%r15) | |
1007 | j 1f | |
1008 | 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15) | |
1009 | 1: lmg %r0,%r11,SP_R0(%r15) | |
1010 | lg %r15,SP_R15(%r15) | |
1011 | 2: la %r12,__LC_RETURN_PSW | |
1012 | br %r14 | |
1013 | cleanup_io_leave_insn: | |
411788ea | 1014 | .quad io_done - 4 |
ae6aa2ea | 1015 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
411788ea | 1016 | .quad io_done - 8 |
ae6aa2ea | 1017 | #endif |
ae6aa2ea | 1018 | |
1da177e4 LT |
1019 | /* |
1020 | * Integer constants | |
1021 | */ | |
25d83cbf | 1022 | .align 4 |
1da177e4 | 1023 | .Lconst: |
25d83cbf HC |
1024 | .Lnr_syscalls: .long NR_syscalls |
1025 | .L0x0130: .short 0x130 | |
1026 | .L0x0140: .short 0x140 | |
1027 | .L0x0150: .short 0x150 | |
1028 | .L0x0160: .short 0x160 | |
1029 | .L0x0170: .short 0x170 | |
1da177e4 | 1030 | .Lcritical_start: |
25d83cbf | 1031 | .quad __critical_start |
1da177e4 | 1032 | .Lcritical_end: |
25d83cbf | 1033 | .quad __critical_end |
1da177e4 | 1034 | |
25d83cbf | 1035 | .section .rodata, "a" |
1da177e4 | 1036 | #define SYSCALL(esa,esame,emu) .long esame |
1da177e4 LT |
1037 | sys_call_table: |
1038 | #include "syscalls.S" | |
1039 | #undef SYSCALL | |
1040 | ||
347a8dc3 | 1041 | #ifdef CONFIG_COMPAT |
1da177e4 LT |
1042 | |
1043 | #define SYSCALL(esa,esame,emu) .long emu | |
1da177e4 LT |
1044 | sys_call_table_emu: |
1045 | #include "syscalls.S" | |
1046 | #undef SYSCALL | |
1047 | #endif |