]> bbs.cooldavid.org Git - net-next-2.6.git/blame - arch/ppc/kernel/head_fsl_booke.S
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] ppc32: Fix errata for some G3 CPUs
[net-next-2.6.git] / arch / ppc / kernel / head_fsl_booke.S
CommitLineData
1da177e4
LT		 1/*
2 * arch/ppc/kernel/head_fsl_booke.S
3 *
4 * Kernel execution entry point code.
5 *
6 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
7 * Initial PowerPC version.
8 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Rewritten for PReP
10 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
11 * Low-level exception handers, MMU support, and rewrite.
12 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
13 * PowerPC 8xx modifications.
14 * Copyright (c) 1998-1999 TiVo, Inc.
15 * PowerPC 403GCX modifications.
16 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
17 * PowerPC 403GCX/405GP modifications.
18 * Copyright 2000 MontaVista Software Inc.
19 * PPC405 modifications
20 * PowerPC 403GCX/405GP modifications.
21 * Author: MontaVista Software, Inc.
22 * frank_rowand@mvista.com or source@mvista.com
23 * debbie_chu@mvista.com
24 * Copyright 2002-2004 MontaVista Software, Inc.
25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
26 * Copyright 2004 Freescale Semiconductor, Inc
27 * PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com>
28 *
29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms of the GNU General Public License as published by the
31 * Free Software Foundation; either version 2 of the License, or (at your
32 * option) any later version.
33 */
34
35#include <linux/config.h>
36#include <linux/threads.h>
37#include <asm/processor.h>
38#include <asm/page.h>
39#include <asm/mmu.h>
40#include <asm/pgtable.h>
41#include <asm/cputable.h>
42#include <asm/thread_info.h>
43#include <asm/ppc_asm.h>
44#include <asm/offsets.h>
45#include "head_booke.h"
46
47/* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
56 *
57 */
58 .text
59_GLOBAL(_stext)
60_GLOBAL(_start)
61 /*
62 * Reserve a word at a fixed location to store the address
63 * of abatron_pteptrs
64 */
65 nop
66/*
67 * Save parameters we are passed
68 */
69 mr r31,r3
70 mr r30,r4
71 mr r29,r5
72 mr r28,r6
73 mr r27,r7
74 li r24,0 /* CPU number */
75
76/* We try to not make any assumptions about how the boot loader
77 * setup or used the TLBs. We invalidate all mappings from the
78 * boot loader and load a single entry in TLB1[0] to map the
79 * first 16M of kernel memory. Any boot info passed from the
80 * bootloader needs to live in this first 16M.
81 *
82 * Requirement on bootloader:
83 * - The page we're executing in needs to reside in TLB1 and
84 * have IPROT=1. If not an invalidate broadcast could
85 * evict the entry we're currently executing in.
86 *
87 * r3 = Index of TLB1 were executing in
88 * r4 = Current MSR[IS]
89 * r5 = Index of TLB1 temp mapping
90 *
91 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
92 * if needed
93 */
94
95/* 1. Find the index of the entry we're executing in */
96 bl invstr /* Find our address */
97invstr: mflr r6 /* Make it accessible */
98 mfmsr r7
99 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
100 mfspr r7, SPRN_PID0
101 slwi r7,r7,16
102 or r7,r7,r4
103 mtspr SPRN_MAS6,r7
104 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
105 mfspr r7,SPRN_MAS1
106 andis. r7,r7,MAS1_VALID@h
107 bne match_TLB
108 mfspr r7,SPRN_PID1
109 slwi r7,r7,16
110 or r7,r7,r4
111 mtspr SPRN_MAS6,r7
112 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
113 mfspr r7,SPRN_MAS1
114 andis. r7,r7,MAS1_VALID@h
115 bne match_TLB
116 mfspr r7, SPRN_PID2
117 slwi r7,r7,16
118 or r7,r7,r4
119 mtspr SPRN_MAS6,r7
120 tlbsx 0,r6 /* Fall through, we had to match */
121match_TLB:
122 mfspr r7,SPRN_MAS0
123 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
124
125 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
126 oris r7,r7,MAS1_IPROT@h
127 mtspr SPRN_MAS1,r7
128 tlbwe
129
130/* 2. Invalidate all entries except the entry we're executing in */
131 mfspr r9,SPRN_TLB1CFG
132 andi. r9,r9,0xfff
133 li r6,0 /* Set Entry counter to 0 */
1341: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
135 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
136 mtspr SPRN_MAS0,r7
137 tlbre
138 mfspr r7,SPRN_MAS1
139 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
140 cmpw r3,r6
141 beq skpinv /* Dont update the current execution TLB */
142 mtspr SPRN_MAS1,r7
143 tlbwe
144 isync
145skpinv: addi r6,r6,1 /* Increment */
146 cmpw r6,r9 /* Are we done? */
147 bne 1b /* If not, repeat */
148
149 /* Invalidate TLB0 */
150 li r6,0x04
151 tlbivax 0,r6
152#ifdef CONFIG_SMP
153 tlbsync
154#endif
155 /* Invalidate TLB1 */
156 li r6,0x0c
157 tlbivax 0,r6
158#ifdef CONFIG_SMP
159 tlbsync
160#endif
161 msync
162
163/* 3. Setup a temp mapping and jump to it */
164 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
165 addi r5, r5, 0x1
166 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
167 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
168 mtspr SPRN_MAS0,r7
169 tlbre
170
171 /* Just modify the entry ID and EPN for the temp mapping */
172 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
173 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
174 mtspr SPRN_MAS0,r7
175 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
176 slwi r6,r6,12
177 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
178 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
179 mtspr SPRN_MAS1,r6
180 mfspr r6,SPRN_MAS2
181 li r7,0 /* temp EPN = 0 */
182 rlwimi r7,r6,0,20,31
183 mtspr SPRN_MAS2,r7
184 tlbwe
185
186 xori r6,r4,1
187 slwi r6,r6,5 /* setup new context with other address space */
188 bl 1f /* Find our address */
1891: mflr r9
190 rlwimi r7,r9,0,20,31
191 addi r7,r7,24
192 mtspr SPRN_SRR0,r7
193 mtspr SPRN_SRR1,r6
194 rfi
195
196/* 4. Clear out PIDs & Search info */
197 li r6,0
198 mtspr SPRN_PID0,r6
199 mtspr SPRN_PID1,r6
200 mtspr SPRN_PID2,r6
201 mtspr SPRN_MAS6,r6
202
203/* 5. Invalidate mapping we started in */
204 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
205 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
206 mtspr SPRN_MAS0,r7
207 tlbre
208 li r6,0
209 mtspr SPRN_MAS1,r6
210 tlbwe
211 /* Invalidate TLB1 */
212 li r9,0x0c
213 tlbivax 0,r9
214#ifdef CONFIG_SMP
215 tlbsync
216#endif
217 msync
218
219/* 6. Setup KERNELBASE mapping in TLB1[0] */
220 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
221 mtspr SPRN_MAS0,r6
222 lis r6,(MAS1_VALID|MAS1_IPROT)@h
223 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l
224 mtspr SPRN_MAS1,r6
225 li r7,0
226 lis r6,KERNELBASE@h
227 ori r6,r6,KERNELBASE@l
228 rlwimi r6,r7,0,20,31
229 mtspr SPRN_MAS2,r6
230 li r7,(MAS3_SX|MAS3_SW|MAS3_SR)
231 mtspr SPRN_MAS3,r7
232 tlbwe
233
234/* 7. Jump to KERNELBASE mapping */
235 li r7,0
236 bl 1f /* Find our address */
2371: mflr r9
238 rlwimi r6,r9,0,20,31
239 addi r6,r6,24
240 mtspr SPRN_SRR0,r6
241 mtspr SPRN_SRR1,r7
242 rfi /* start execution out of TLB1[0] entry */
243
244/* 8. Clear out the temp mapping */
245 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
246 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
247 mtspr SPRN_MAS0,r7
248 tlbre
249 mtspr SPRN_MAS1,r8
250 tlbwe
251 /* Invalidate TLB1 */
252 li r9,0x0c
253 tlbivax 0,r9
254#ifdef CONFIG_SMP
255 tlbsync
256#endif
257 msync
258
259 /* Establish the interrupt vector offsets */
260 SET_IVOR(0, CriticalInput);
261 SET_IVOR(1, MachineCheck);
262 SET_IVOR(2, DataStorage);
263 SET_IVOR(3, InstructionStorage);
264 SET_IVOR(4, ExternalInput);
265 SET_IVOR(5, Alignment);
266 SET_IVOR(6, Program);
267 SET_IVOR(7, FloatingPointUnavailable);
268 SET_IVOR(8, SystemCall);
269 SET_IVOR(9, AuxillaryProcessorUnavailable);
270 SET_IVOR(10, Decrementer);
271 SET_IVOR(11, FixedIntervalTimer);
272 SET_IVOR(12, WatchdogTimer);
273 SET_IVOR(13, DataTLBError);
274 SET_IVOR(14, InstructionTLBError);
275 SET_IVOR(15, Debug);
276 SET_IVOR(32, SPEUnavailable);
277 SET_IVOR(33, SPEFloatingPointData);
278 SET_IVOR(34, SPEFloatingPointRound);
279 SET_IVOR(35, PerformanceMonitor);
280
281 /* Establish the interrupt vector base */
282 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
283 mtspr SPRN_IVPR,r4
284
285 /* Setup the defaults for TLB entries */
286 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
287 mtspr SPRN_MAS4, r2
288
289#if 0
290 /* Enable DOZE */
291 mfspr r2,SPRN_HID0
292 oris r2,r2,HID0_DOZE@h
293 mtspr SPRN_HID0, r2
294#endif
295
296 /*
297 * This is where the main kernel code starts.
298 */
299
300 /* ptr to current */
301 lis r2,init_task@h
302 ori r2,r2,init_task@l
303
304 /* ptr to current thread */
305 addi r4,r2,THREAD /* init task's THREAD */
306 mtspr SPRN_SPRG3,r4
307
308 /* stack */
309 lis r1,init_thread_union@h
310 ori r1,r1,init_thread_union@l
311 li r0,0
312 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
313
314 bl early_init
315
316 mfspr r3,SPRN_TLB1CFG
317 andi. r3,r3,0xfff
318 lis r4,num_tlbcam_entries@ha
319 stw r3,num_tlbcam_entries@l(r4)
320/*
321 * Decide what sort of machine this is and initialize the MMU.
322 */
323 mr r3,r31
324 mr r4,r30
325 mr r5,r29
326 mr r6,r28
327 mr r7,r27
328 bl machine_init
329 bl MMU_init
330
331 /* Setup PTE pointers for the Abatron bdiGDB */
332 lis r6, swapper_pg_dir@h
333 ori r6, r6, swapper_pg_dir@l
334 lis r5, abatron_pteptrs@h
335 ori r5, r5, abatron_pteptrs@l
336 lis r4, KERNELBASE@h
337 ori r4, r4, KERNELBASE@l
338 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
339 stw r6, 0(r5)
340
341 /* Let's move on */
342 lis r4,start_kernel@h
343 ori r4,r4,start_kernel@l
344 lis r3,MSR_KERNEL@h
345 ori r3,r3,MSR_KERNEL@l
346 mtspr SPRN_SRR0,r4
347 mtspr SPRN_SRR1,r3
348 rfi /* change context and jump to start_kernel */
349
f50b153b
KG		 350/* Macros to hide the PTE size differences
351 *
352 * FIND_PTE -- walks the page tables given EA & pgdir pointer
353 * r10 -- EA of fault
354 * r11 -- PGDIR pointer
355 * r12 -- free
356 * label 2: is the bailout case
357 *
358 * if we find the pte (fall through):
359 * r11 is low pte word
360 * r12 is pointer to the pte
361 */
362#ifdef CONFIG_PTE_64BIT
363#define PTE_FLAGS_OFFSET 4
364#define FIND_PTE \
365 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
366 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
367 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
368 beq 2f; /* Bail if no table */ \
369 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
370 lwz r11, 4(r12); /* Get pte entry */
371#else
372#define PTE_FLAGS_OFFSET 0
373#define FIND_PTE \
374 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
375 lwz r11, 0(r11); /* Get L1 entry */ \
376 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
377 beq 2f; /* Bail if no table */ \
378 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
379 lwz r11, 0(r12); /* Get Linux PTE */
380#endif
381
1da177e4
LT		 382/*
383 * Interrupt vector entry code
384 *
385 * The Book E MMUs are always on so we don't need to handle
386 * interrupts in real mode as with previous PPC processors. In
387 * this case we handle interrupts in the kernel virtual address
388 * space.
389 *
390 * Interrupt vectors are dynamically placed relative to the
391 * interrupt prefix as determined by the address of interrupt_base.
392 * The interrupt vectors offsets are programmed using the labels
393 * for each interrupt vector entry.
394 *
395 * Interrupt vectors must be aligned on a 16 byte boundary.
396 * We align on a 32 byte cache line boundary for good measure.
397 */
398
399interrupt_base:
400 /* Critical Input Interrupt */
401 CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
402
403 /* Machine Check Interrupt */
404 MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
405
406 /* Data Storage Interrupt */
407 START_EXCEPTION(DataStorage)
408 mtspr SPRN_SPRG0, r10 /* Save some working registers */
409 mtspr SPRN_SPRG1, r11
410 mtspr SPRN_SPRG4W, r12
411 mtspr SPRN_SPRG5W, r13
412 mfcr r11
413 mtspr SPRN_SPRG7W, r11
414
415 /*
416 * Check if it was a store fault, if not then bail
417 * because a user tried to access a kernel or
418 * read-protected page. Otherwise, get the
419 * offending address and handle it.
420 */
421 mfspr r10, SPRN_ESR
422 andis. r10, r10, ESR_ST@h
423 beq 2f
424
425 mfspr r10, SPRN_DEAR /* Get faulting address */
426
427 /* If we are faulting a kernel address, we have to use the
428 * kernel page tables.
429 */
430 lis r11, TASK_SIZE@h
431 ori r11, r11, TASK_SIZE@l
432 cmplw 0, r10, r11
433 bge 2f
434
435 /* Get the PGD for the current thread */
4363:
437 mfspr r11,SPRN_SPRG3
438 lwz r11,PGDIR(r11)
4394:
f50b153b 440 FIND_PTE
1da177e4
LT		 441
442 /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
443 andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
444 cmpwi 0, r13, _PAGE_RW|_PAGE_USER
445 bne 2f /* Bail if not */
446
447 /* Update 'changed'. */
448 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
f50b153b 449 stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
1da177e4
LT		 450
451 /* MAS2 not updated as the entry does exist in the tlb, this
452 fault taken to detect state transition (eg: COW -> DIRTY)
453 */
f50b153b 454 andi. r11, r11, _PAGE_HWEXEC
1da177e4
LT		 455 rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
456 ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
457
458 /* update search PID in MAS6, AS = 0 */
459 mfspr r12, SPRN_PID0
460 slwi r12, r12, 16
461 mtspr SPRN_MAS6, r12
462
463 /* find the TLB index that caused the fault. It has to be here. */
464 tlbsx 0, r10
465
f50b153b
KG		 466 /* only update the perm bits, assume the RPN is fine */
467 mfspr r12, SPRN_MAS3
468 rlwimi r12, r11, 0, 20, 31
469 mtspr SPRN_MAS3,r12
1da177e4
LT		 470 tlbwe
471
472 /* Done...restore registers and get out of here. */
473 mfspr r11, SPRN_SPRG7R
474 mtcr r11
475 mfspr r13, SPRN_SPRG5R
476 mfspr r12, SPRN_SPRG4R
477 mfspr r11, SPRN_SPRG1
478 mfspr r10, SPRN_SPRG0
479 rfi /* Force context change */
480
4812:
482 /*
483 * The bailout. Restore registers to pre-exception conditions
484 * and call the heavyweights to help us out.
485 */
486 mfspr r11, SPRN_SPRG7R
487 mtcr r11
488 mfspr r13, SPRN_SPRG5R
489 mfspr r12, SPRN_SPRG4R
490 mfspr r11, SPRN_SPRG1
491 mfspr r10, SPRN_SPRG0
492 b data_access
493
494 /* Instruction Storage Interrupt */
495 INSTRUCTION_STORAGE_EXCEPTION
496
497 /* External Input Interrupt */
498 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
499
500 /* Alignment Interrupt */
501 ALIGNMENT_EXCEPTION
502
503 /* Program Interrupt */
504 PROGRAM_EXCEPTION
505
506 /* Floating Point Unavailable Interrupt */
507 EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
508
509 /* System Call Interrupt */
510 START_EXCEPTION(SystemCall)
511 NORMAL_EXCEPTION_PROLOG
512 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
513
514 /* Auxillary Processor Unavailable Interrupt */
515 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
516
517 /* Decrementer Interrupt */
518 DECREMENTER_EXCEPTION
519
520 /* Fixed Internal Timer Interrupt */
521 /* TODO: Add FIT support */
522 EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
523
524 /* Watchdog Timer Interrupt */
525 /* TODO: Add watchdog support */
526 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException)
527
528 /* Data TLB Error Interrupt */
529 START_EXCEPTION(DataTLBError)
530 mtspr SPRN_SPRG0, r10 /* Save some working registers */
531 mtspr SPRN_SPRG1, r11
532 mtspr SPRN_SPRG4W, r12
533 mtspr SPRN_SPRG5W, r13
534 mfcr r11
535 mtspr SPRN_SPRG7W, r11
536 mfspr r10, SPRN_DEAR /* Get faulting address */
537
538 /* If we are faulting a kernel address, we have to use the
539 * kernel page tables.
540 */
541 lis r11, TASK_SIZE@h
542 ori r11, r11, TASK_SIZE@l
543 cmplw 5, r10, r11
544 blt 5, 3f
545 lis r11, swapper_pg_dir@h
546 ori r11, r11, swapper_pg_dir@l
547
548 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
549 rlwinm r12,r12,0,16,1
550 mtspr SPRN_MAS1,r12
551
552 b 4f
553
554 /* Get the PGD for the current thread */
5553:
556 mfspr r11,SPRN_SPRG3
557 lwz r11,PGDIR(r11)
558
5594:
f50b153b
KG		 560 FIND_PTE
561 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
562 beq 2f /* Bail if not present */
1da177e4 563
f50b153b
KG		 564#ifdef CONFIG_PTE_64BIT
565 lwz r13, 0(r12)
566#endif
1da177e4 567 ori r11, r11, _PAGE_ACCESSED
f50b153b 568 stw r11, PTE_FLAGS_OFFSET(r12)
1da177e4
LT		 569
570 /* Jump to common tlb load */
571 b finish_tlb_load
5722:
573 /* The bailout. Restore registers to pre-exception conditions
574 * and call the heavyweights to help us out.
575 */
576 mfspr r11, SPRN_SPRG7R
577 mtcr r11
578 mfspr r13, SPRN_SPRG5R
579 mfspr r12, SPRN_SPRG4R
580 mfspr r11, SPRN_SPRG1
581 mfspr r10, SPRN_SPRG0
582 b data_access
583
584 /* Instruction TLB Error Interrupt */
585 /*
586 * Nearly the same as above, except we get our
587 * information from different registers and bailout
588 * to a different point.
589 */
590 START_EXCEPTION(InstructionTLBError)
591 mtspr SPRN_SPRG0, r10 /* Save some working registers */
592 mtspr SPRN_SPRG1, r11
593 mtspr SPRN_SPRG4W, r12
594 mtspr SPRN_SPRG5W, r13
595 mfcr r11
596 mtspr SPRN_SPRG7W, r11
597 mfspr r10, SPRN_SRR0 /* Get faulting address */
598
599 /* If we are faulting a kernel address, we have to use the
600 * kernel page tables.
601 */
602 lis r11, TASK_SIZE@h
603 ori r11, r11, TASK_SIZE@l
604 cmplw 5, r10, r11
605 blt 5, 3f
606 lis r11, swapper_pg_dir@h
607 ori r11, r11, swapper_pg_dir@l
608
609 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
610 rlwinm r12,r12,0,16,1
611 mtspr SPRN_MAS1,r12
612
613 b 4f
614
615 /* Get the PGD for the current thread */
6163:
617 mfspr r11,SPRN_SPRG3
618 lwz r11,PGDIR(r11)
619
6204:
f50b153b
KG		 621 FIND_PTE
622 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
623 beq 2f /* Bail if not present */
1da177e4 624
f50b153b
KG		 625#ifdef CONFIG_PTE_64BIT
626 lwz r13, 0(r12)
627#endif
1da177e4 628 ori r11, r11, _PAGE_ACCESSED
f50b153b 629 stw r11, PTE_FLAGS_OFFSET(r12)
1da177e4
LT		 630
631 /* Jump to common TLB load point */
632 b finish_tlb_load
633
6342:
635 /* The bailout. Restore registers to pre-exception conditions
636 * and call the heavyweights to help us out.
637 */
638 mfspr r11, SPRN_SPRG7R
639 mtcr r11
640 mfspr r13, SPRN_SPRG5R
641 mfspr r12, SPRN_SPRG4R
642 mfspr r11, SPRN_SPRG1
643 mfspr r10, SPRN_SPRG0
644 b InstructionStorage
645
646#ifdef CONFIG_SPE
647 /* SPE Unavailable */
648 START_EXCEPTION(SPEUnavailable)
649 NORMAL_EXCEPTION_PROLOG
650 bne load_up_spe
651 addi r3,r1,STACK_FRAME_OVERHEAD
652 EXC_XFER_EE_LITE(0x2010, KernelSPE)
653#else
654 EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE)
655#endif /* CONFIG_SPE */
656
657 /* SPE Floating Point Data */
658#ifdef CONFIG_SPE
659 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
660#else
661 EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE)
662#endif /* CONFIG_SPE */
663
664 /* SPE Floating Point Round */
665 EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE)
666
667 /* Performance Monitor */
668 EXCEPTION(0x2060, PerformanceMonitor, PerformanceMonitorException, EXC_XFER_STD)
669
670
671 /* Debug Interrupt */
672 DEBUG_EXCEPTION
673
674/*
675 * Local functions
676 */
677 /*
678 * Data TLB exceptions will bail out to this point
679 * if they can't resolve the lightweight TLB fault.
680 */
681data_access:
682 NORMAL_EXCEPTION_PROLOG
683 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
684 stw r5,_ESR(r11)
685 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
686 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
687 bne 1f
688 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
6891:
690 addi r3,r1,STACK_FRAME_OVERHEAD
691 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
692
693/*
694
695 * Both the instruction and data TLB miss get to this
696 * point to load the TLB.
697 * r10 - EA of fault
698 * r11 - TLB (info from Linux PTE)
699 * r12, r13 - available to use
700 * CR5 - results of addr < TASK_SIZE
701 * MAS0, MAS1 - loaded with proper value when we get here
702 * MAS2, MAS3 - will need additional info from Linux PTE
703 * Upon exit, we reload everything and RFI.
704 */
705finish_tlb_load:
706 /*
707 * We set execute, because we don't have the granularity to
708 * properly set this at the page level (Linux problem).
709 * Many of these bits are software only. Bits we don't set
710 * here we (properly should) assume have the appropriate value.
711 */
712
713 mfspr r12, SPRN_MAS2
f50b153b
KG		 714#ifdef CONFIG_PTE_64BIT
715 rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
716#else
1da177e4 717 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
f50b153b 718#endif
1da177e4
LT		 719 mtspr SPRN_MAS2, r12
720
721 bge 5, 1f
722
f50b153b
KG		 723 /* is user addr */
724 andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
725 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
726 srwi r10, r12, 1
1da177e4 727 or r12, r12, r10 /* Copy user perms into supervisor */
f50b153b 728 iseleq r12, 0, r12
1da177e4
LT		 729 b 2f
730
f50b153b 731 /* is kernel addr */
1da177e4
LT		 7321: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
733 ori r12, r12, (MAS3_SX | MAS3_SR)
734
f50b153b
KG		 735#ifdef CONFIG_PTE_64BIT
7362: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
737 rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
738 mtspr SPRN_MAS3, r12
739BEGIN_FTR_SECTION
740 srwi r10, r13, 8 /* grab RPN[8:31] */
741 mtspr SPRN_MAS7, r10
742END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
743#else
1da177e4
LT		 7442: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
745 mtspr SPRN_MAS3, r11
f50b153b 746#endif
1da177e4
LT		 747 tlbwe
748
749 /* Done...restore registers and get out of here. */
750 mfspr r11, SPRN_SPRG7R
751 mtcr r11
752 mfspr r13, SPRN_SPRG5R
753 mfspr r12, SPRN_SPRG4R
754 mfspr r11, SPRN_SPRG1
755 mfspr r10, SPRN_SPRG0
756 rfi /* Force context change */
757
758#ifdef CONFIG_SPE
759/* Note that the SPE support is closely modeled after the AltiVec
760 * support. Changes to one are likely to be applicable to the
761 * other! */
762load_up_spe:
763/*
764 * Disable SPE for the task which had SPE previously,
765 * and save its SPE registers in its thread_struct.
766 * Enables SPE for use in the kernel on return.
767 * On SMP we know the SPE units are free, since we give it up every
768 * switch. -- Kumar
769 */
770 mfmsr r5
771 oris r5,r5,MSR_SPE@h
772 mtmsr r5 /* enable use of SPE now */
773 isync
774/*
775 * For SMP, we don't do lazy SPE switching because it just gets too
776 * horrendously complex, especially when a task switches from one CPU
777 * to another. Instead we call giveup_spe in switch_to.
778 */
779#ifndef CONFIG_SMP
780 lis r3,last_task_used_spe@ha
781 lwz r4,last_task_used_spe@l(r3)
782 cmpi 0,r4,0
783 beq 1f
784 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
785 SAVE_32EVR(0,r10,r4)
786 evxor evr10, evr10, evr10 /* clear out evr10 */
787 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
788 li r5,THREAD_ACC
789 evstddx evr10, r4, r5 /* save off accumulator */
790 lwz r5,PT_REGS(r4)
791 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
792 lis r10,MSR_SPE@h
793 andc r4,r4,r10 /* disable SPE for previous task */
794 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7951:
796#endif /* CONFIG_SMP */
797 /* enable use of SPE after return */
798 oris r9,r9,MSR_SPE@h
799 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
800 li r4,1
801 li r10,THREAD_ACC
802 stw r4,THREAD_USED_SPE(r5)
803 evlddx evr4,r10,r5
804 evmra evr4,evr4
805 REST_32EVR(0,r10,r5)
806#ifndef CONFIG_SMP
807 subi r4,r5,THREAD
808 stw r4,last_task_used_spe@l(r3)
809#endif /* CONFIG_SMP */
810 /* restore registers and return */
8112: REST_4GPRS(3, r11)
812 lwz r10,_CCR(r11)
813 REST_GPR(1, r11)
814 mtcr r10
815 lwz r10,_LINK(r11)
816 mtlr r10
817 REST_GPR(10, r11)
818 mtspr SPRN_SRR1,r9
819 mtspr SPRN_SRR0,r12
820 REST_GPR(9, r11)
821 REST_GPR(12, r11)
822 lwz r11,GPR11(r11)
823 SYNC
824 rfi
825
826/*
827 * SPE unavailable trap from kernel - print a message, but let
828 * the task use SPE in the kernel until it returns to user mode.
829 */
830KernelSPE:
831 lwz r3,_MSR(r1)
832 oris r3,r3,MSR_SPE@h
833 stw r3,_MSR(r1) /* enable use of SPE after return */
834 lis r3,87f@h
835 ori r3,r3,87f@l
836 mr r4,r2 /* current */
837 lwz r5,_NIP(r1)
838 bl printk
839 b ret_from_except
84087: .string "SPE used in kernel (task=%p, pc=%x) \n"
841 .align 4,0
842
843#endif /* CONFIG_SPE */
844
845/*
846 * Global functions
847 */
848
849/*
850 * extern void loadcam_entry(unsigned int index)
851 *
852 * Load TLBCAM[index] entry in to the L2 CAM MMU
853 */
854_GLOBAL(loadcam_entry)
855 lis r4,TLBCAM@ha
856 addi r4,r4,TLBCAM@l
857 mulli r5,r3,20
858 add r3,r5,r4
859 lwz r4,0(r3)
860 mtspr SPRN_MAS0,r4
861 lwz r4,4(r3)
862 mtspr SPRN_MAS1,r4
863 lwz r4,8(r3)
864 mtspr SPRN_MAS2,r4
865 lwz r4,12(r3)
866 mtspr SPRN_MAS3,r4
867 tlbwe
868 isync
869 blr
870
871/*
872 * extern void giveup_altivec(struct task_struct *prev)
873 *
874 * The e500 core does not have an AltiVec unit.
875 */
876_GLOBAL(giveup_altivec)
877 blr
878
879#ifdef CONFIG_SPE
880/*
881 * extern void giveup_spe(struct task_struct *prev)
882 *
883 */
884_GLOBAL(giveup_spe)
885 mfmsr r5
886 oris r5,r5,MSR_SPE@h
887 SYNC
888 mtmsr r5 /* enable use of SPE now */
889 isync
890 cmpi 0,r3,0
891 beqlr- /* if no previous owner, done */
892 addi r3,r3,THREAD /* want THREAD of task */
893 lwz r5,PT_REGS(r3)
894 cmpi 0,r5,0
895 SAVE_32EVR(0, r4, r3)
896 evxor evr6, evr6, evr6 /* clear out evr6 */
897 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
898 li r4,THREAD_ACC
899 evstddx evr6, r4, r3 /* save off accumulator */
900 mfspr r6,SPRN_SPEFSCR
901 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
902 beq 1f
903 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
904 lis r3,MSR_SPE@h
905 andc r4,r4,r3 /* disable SPE for previous task */
906 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
9071:
908#ifndef CONFIG_SMP
909 li r5,0
910 lis r4,last_task_used_spe@ha
911 stw r5,last_task_used_spe@l(r4)
912#endif /* CONFIG_SMP */
913 blr
914#endif /* CONFIG_SPE */
915
916/*
917 * extern void giveup_fpu(struct task_struct *prev)
918 *
919 * The e500 core does not have an FPU.
920 */
921_GLOBAL(giveup_fpu)
922 blr
923
924/*
925 * extern void abort(void)
926 *
927 * At present, this routine just applies a system reset.
928 */
929_GLOBAL(abort)
930 li r13,0
931 mtspr SPRN_DBCR0,r13 /* disable all debug events */
932 mfmsr r13
933 ori r13,r13,MSR_DE@l /* Enable Debug Events */
934 mtmsr r13
935 mfspr r13,SPRN_DBCR0
936 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
937 mtspr SPRN_DBCR0,r13
938
939_GLOBAL(set_context)
940
941#ifdef CONFIG_BDI_SWITCH
942 /* Context switch the PTE pointer for the Abatron BDI2000.
943 * The PGDIR is the second parameter.
944 */
945 lis r5, abatron_pteptrs@h
946 ori r5, r5, abatron_pteptrs@l
947 stw r4, 0x4(r5)
948#endif
949 mtspr SPRN_PID,r3
950 isync /* Force context change */
951 blr
952
953/*
954 * We put a few things here that have to be page-aligned. This stuff
955 * goes at the beginning of the data segment, which is page-aligned.
956 */
957 .data
958_GLOBAL(sdata)
959_GLOBAL(empty_zero_page)
960 .space 4096
961_GLOBAL(swapper_pg_dir)
962 .space 4096
963
964/* Reserved 4k for the critical exception stack & 4k for the machine
965 * check stack per CPU for kernel mode exceptions */
966 .section .bss
967 .align 12
968exception_stack_bottom:
969 .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
970_GLOBAL(exception_stack_top)
971
972/*
973 * This space gets a copy of optional info passed to us by the bootstrap
974 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
975 */
976_GLOBAL(cmd_line)
977 .space 512
978
979/*
980 * Room for two PTE pointers, usually the kernel and current user pointers
981 * to their respective root page table.
982 */
983abatron_pteptrs:
984 .space 8
985
Clone of davem's net-next-2.6 tree