[net-next-2.6.git] / arch / powerpc / sysdev / qe_lib / qe_ic.c

/*
 * arch/powerpc/sysdev/qe_lib/qe_ic.c
 *
 * Copyright (C) 2006 Freescale Semicondutor, Inc.  All rights reserved.
 *
 * Author: Li Yang <leoli@freescale.com>
 * Based on code from Shlomi Gridish <gridish@freescale.com>
 *
 * QUICC ENGINE Interrupt Controller
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/stddef.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/sysdev.h>
#include <linux/device.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/qe_ic.h>

#include "qe_ic.h"

static DEFINE_SPINLOCK(qe_ic_lock);

static struct qe_ic_info qe_ic_info[] = {
	[1] = {
	       .mask = 0x00008000,
	       .mask_reg = QEIC_CIMR,
	       .pri_code = 0,
	       .pri_reg = QEIC_CIPWCC,
	       },
	[2] = {
	       .mask = 0x00004000,
	       .mask_reg = QEIC_CIMR,
	       .pri_code = 1,
	       .pri_reg = QEIC_CIPWCC,
	       },
	[3] = {
	       .mask = 0x00002000,
	       .mask_reg = QEIC_CIMR,
	       .pri_code = 2,
	       .pri_reg = QEIC_CIPWCC,
	       },
	[10] = {
		.mask = 0x00000040,
		.mask_reg = QEIC_CIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPZCC,
		},
	[11] = {
		.mask = 0x00000020,
		.mask_reg = QEIC_CIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPZCC,
		},
	[12] = {
		.mask = 0x00000010,
		.mask_reg = QEIC_CIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPZCC,
		},
	[13] = {
		.mask = 0x00000008,
		.mask_reg = QEIC_CIMR,
		.pri_code = 4,
		.pri_reg = QEIC_CIPZCC,
		},
	[14] = {
		.mask = 0x00000004,
		.mask_reg = QEIC_CIMR,
		.pri_code = 5,
		.pri_reg = QEIC_CIPZCC,
		},
	[15] = {
		.mask = 0x00000002,
		.mask_reg = QEIC_CIMR,
		.pri_code = 6,
		.pri_reg = QEIC_CIPZCC,
		},
	[20] = {
		.mask = 0x10000000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPRTA,
		},
	[25] = {
		.mask = 0x00800000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 0,
		.pri_reg = QEIC_CIPRTB,
		},
	[26] = {
		.mask = 0x00400000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPRTB,
		},
	[27] = {
		.mask = 0x00200000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPRTB,
		},
	[28] = {
		.mask = 0x00100000,
		.mask_reg = QEIC_CRIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPRTB,
		},
	[32] = {
		.mask = 0x80000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 0,
		.pri_reg = QEIC_CIPXCC,
		},
	[33] = {
		.mask = 0x40000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPXCC,
		},
	[34] = {
		.mask = 0x20000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPXCC,
		},
	[35] = {
		.mask = 0x10000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPXCC,
		},
	[36] = {
		.mask = 0x08000000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 4,
		.pri_reg = QEIC_CIPXCC,
		},
	[40] = {
		.mask = 0x00800000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 0,
		.pri_reg = QEIC_CIPYCC,
		},
	[41] = {
		.mask = 0x00400000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 1,
		.pri_reg = QEIC_CIPYCC,
		},
	[42] = {
		.mask = 0x00200000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 2,
		.pri_reg = QEIC_CIPYCC,
		},
	[43] = {
		.mask = 0x00100000,
		.mask_reg = QEIC_CIMR,
		.pri_code = 3,
		.pri_reg = QEIC_CIPYCC,
		},
};

static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
{
	return in_be32(base + (reg >> 2));
}

static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg,
			       u32 value)
{
	out_be32(base + (reg >> 2), value);
}

static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
{
	return irq_desc[virq].chip_data;
}

#define virq_to_hw(virq)	((unsigned int)irq_map[virq].hwirq)

static void qe_ic_unmask_irq(unsigned int virq)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	unsigned long flags;
	u32 temp;

	spin_lock_irqsave(&qe_ic_lock, flags);

	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
		    temp | qe_ic_info[src].mask);

	spin_unlock_irqrestore(&qe_ic_lock, flags);
}

static void qe_ic_mask_irq(unsigned int virq)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	unsigned long flags;
	u32 temp;

	spin_lock_irqsave(&qe_ic_lock, flags);

	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
		    temp & ~qe_ic_info[src].mask);

	/* Flush the above write before enabling interrupts; otherwise,
	 * spurious interrupts will sometimes happen.  To be 100% sure
	 * that the write has reached the device before interrupts are
	 * enabled, the mask register would have to be read back; however,
	 * this is not required for correctness, only to avoid wasting
	 * time on a large number of spurious interrupts.  In testing,
	 * a sync reduced the observed spurious interrupts to zero.
	 */
	mb();

	spin_unlock_irqrestore(&qe_ic_lock, flags);
}

static struct irq_chip qe_ic_irq_chip = {
	.typename = " QEIC  ",
	.unmask = qe_ic_unmask_irq,
	.mask = qe_ic_mask_irq,
	.mask_ack = qe_ic_mask_irq,
};

static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
{
	/* Exact match, unless qe_ic node is NULL */
	return h->of_node == NULL || h->of_node == node;
}

static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	struct qe_ic *qe_ic = h->host_data;
	struct irq_chip *chip;

	if (qe_ic_info[hw].mask == 0) {
		printk(KERN_ERR "Can't map reserved IRQ \n");
		return -EINVAL;
	}
	/* Default chip */
	chip = &qe_ic->hc_irq;

	set_irq_chip_data(virq, qe_ic);
	get_irq_desc(virq)->status |= IRQ_LEVEL;

	set_irq_chip_and_handler(virq, chip, handle_level_irq);

	return 0;
}

static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
			    u32 * intspec, unsigned int intsize,
			    irq_hw_number_t * out_hwirq,
			    unsigned int *out_flags)
{
	*out_hwirq = intspec[0];
	if (intsize > 1)
		*out_flags = intspec[1];
	else
		*out_flags = IRQ_TYPE_NONE;
	return 0;
}

static struct irq_host_ops qe_ic_host_ops = {
	.match = qe_ic_host_match,
	.map = qe_ic_host_map,
	.xlate = qe_ic_host_xlate,
};

/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
	int irq;

	BUG_ON(qe_ic == NULL);

	/* get the interrupt source vector. */
	irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;

	if (irq == 0)
		return NO_IRQ;

	return irq_linear_revmap(qe_ic->irqhost, irq);
}

/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
	int irq;

	BUG_ON(qe_ic == NULL);

	/* get the interrupt source vector. */
	irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;

	if (irq == 0)
		return NO_IRQ;

	return irq_linear_revmap(qe_ic->irqhost, irq);
}

void __init qe_ic_init(struct device_node *node, unsigned int flags,
		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
		void (*high_handler)(unsigned int irq, struct irq_desc *desc))
{
	struct qe_ic *qe_ic;
	struct resource res;
	u32 temp = 0, ret, high_active = 0;

	qe_ic = alloc_bootmem(sizeof(struct qe_ic));
	if (qe_ic == NULL)
		return;

	memset(qe_ic, 0, sizeof(struct qe_ic));

	qe_ic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
					NR_QE_IC_INTS, &qe_ic_host_ops, 0);
	if (qe_ic->irqhost == NULL) {
		of_node_put(node);
		return;
	}

	ret = of_address_to_resource(node, 0, &res);
	if (ret)
		return;

	qe_ic->regs = ioremap(res.start, res.end - res.start + 1);

	qe_ic->irqhost->host_data = qe_ic;
	qe_ic->hc_irq = qe_ic_irq_chip;

	qe_ic->virq_high = irq_of_parse_and_map(node, 0);
	qe_ic->virq_low = irq_of_parse_and_map(node, 1);

	if (qe_ic->virq_low == NO_IRQ) {
		printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
		return;
	}

	/* default priority scheme is grouped. If spread mode is    */
	/* required, configure cicr accordingly.                    */
	if (flags & QE_IC_SPREADMODE_GRP_W)
		temp |= CICR_GWCC;
	if (flags & QE_IC_SPREADMODE_GRP_X)
		temp |= CICR_GXCC;
	if (flags & QE_IC_SPREADMODE_GRP_Y)
		temp |= CICR_GYCC;
	if (flags & QE_IC_SPREADMODE_GRP_Z)
		temp |= CICR_GZCC;
	if (flags & QE_IC_SPREADMODE_GRP_RISCA)
		temp |= CICR_GRTA;
	if (flags & QE_IC_SPREADMODE_GRP_RISCB)
		temp |= CICR_GRTB;

	/* choose destination signal for highest priority interrupt */
	if (flags & QE_IC_HIGH_SIGNAL) {
		temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
		high_active = 1;
	}

	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);

	set_irq_data(qe_ic->virq_low, qe_ic);
	set_irq_chained_handler(qe_ic->virq_low, low_handler);

	if (qe_ic->virq_high != NO_IRQ &&
			qe_ic->virq_high != qe_ic->virq_low) {
		set_irq_data(qe_ic->virq_high, qe_ic);
		set_irq_chained_handler(qe_ic->virq_high, high_handler);
	}
}

void qe_ic_set_highest_priority(unsigned int virq, int high)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	u32 temp = 0;

	temp = qe_ic_read(qe_ic->regs, QEIC_CICR);

	temp &= ~CICR_HP_MASK;
	temp |= src << CICR_HP_SHIFT;

	temp &= ~CICR_HPIT_MASK;
	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;

	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
}

/* Set Priority level within its group, from 1 to 8 */
int qe_ic_set_priority(unsigned int virq, unsigned int priority)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	u32 temp;

	if (priority > 8 || priority == 0)
		return -EINVAL;
	if (src > 127)
		return -EINVAL;
	if (qe_ic_info[src].pri_reg == 0)
		return -EINVAL;

	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);

	if (priority < 4) {
		temp &= ~(0x7 << (32 - priority * 3));
		temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
	} else {
		temp &= ~(0x7 << (24 - priority * 3));
		temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
	}

	qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);

	return 0;
}

/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
{
	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	unsigned int src = virq_to_hw(virq);
	u32 temp, control_reg = QEIC_CICNR, shift = 0;

	if (priority > 2 || priority == 0)
		return -EINVAL;

	switch (qe_ic_info[src].pri_reg) {
	case QEIC_CIPZCC:
		shift = CICNR_ZCC1T_SHIFT;
		break;
	case QEIC_CIPWCC:
		shift = CICNR_WCC1T_SHIFT;
		break;
	case QEIC_CIPYCC:
		shift = CICNR_YCC1T_SHIFT;
		break;
	case QEIC_CIPXCC:
		shift = CICNR_XCC1T_SHIFT;
		break;
	case QEIC_CIPRTA:
		shift = CRICR_RTA1T_SHIFT;
		control_reg = QEIC_CRICR;
		break;
	case QEIC_CIPRTB:
		shift = CRICR_RTB1T_SHIFT;
		control_reg = QEIC_CRICR;
		break;
	default:
		return -EINVAL;
	}

	shift += (2 - priority) * 2;
	temp = qe_ic_read(qe_ic->regs, control_reg);
	temp &= ~(SIGNAL_MASK << shift);
	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
	qe_ic_write(qe_ic->regs, control_reg, temp);

	return 0;
}

static struct sysdev_class qe_ic_sysclass = {
	.name = "qe_ic",
};

static struct sys_device device_qe_ic = {
	.id = 0,
	.cls = &qe_ic_sysclass,
};

static int __init init_qe_ic_sysfs(void)
{
	int rc;

	printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");

	rc = sysdev_class_register(&qe_ic_sysclass);
	if (rc) {
		printk(KERN_ERR "Failed registering qe_ic sys class\n");
		return -ENODEV;
	}
	rc = sysdev_register(&device_qe_ic);
	if (rc) {
		printk(KERN_ERR "Failed registering qe_ic sys device\n");
		return -ENODEV;
	}
	return 0;
}

subsys_initcall(init_qe_ic_sysfs);
Commit	Line	Data
98658538 LY	1	/*
	2	* arch/powerpc/sysdev/qe_lib/qe_ic.c
	3	*
	4	* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
	5	*
	6	* Author: Li Yang <leoli@freescale.com>
	7	* Based on code from Shlomi Gridish <gridish@freescale.com>
	8	*
	9	* QUICC ENGINE Interrupt Controller
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/errno.h>
	20	#include <linux/reboot.h>
	21	#include <linux/slab.h>
	22	#include <linux/stddef.h>
	23	#include <linux/sched.h>
	24	#include <linux/signal.h>
	25	#include <linux/sysdev.h>
	26	#include <linux/device.h>
	27	#include <linux/bootmem.h>
	28	#include <linux/spinlock.h>
	29	#include <asm/irq.h>
	30	#include <asm/io.h>
	31	#include <asm/prom.h>
	32	#include <asm/qe_ic.h>
	33
	34	#include "qe_ic.h"
	35
	36	static DEFINE_SPINLOCK(qe_ic_lock);
	37
	38	static struct qe_ic_info qe_ic_info[] = {
	39	[1] = {
	40	.mask = 0x00008000,
	41	.mask_reg = QEIC_CIMR,
	42	.pri_code = 0,
	43	.pri_reg = QEIC_CIPWCC,
	44	},
	45	[2] = {
	46	.mask = 0x00004000,
	47	.mask_reg = QEIC_CIMR,
	48	.pri_code = 1,
	49	.pri_reg = QEIC_CIPWCC,
	50	},
	51	[3] = {
	52	.mask = 0x00002000,
	53	.mask_reg = QEIC_CIMR,
	54	.pri_code = 2,
	55	.pri_reg = QEIC_CIPWCC,
	56	},
	57	[10] = {
	58	.mask = 0x00000040,
	59	.mask_reg = QEIC_CIMR,
	60	.pri_code = 1,
	61	.pri_reg = QEIC_CIPZCC,
	62	},
	63	[11] = {
	64	.mask = 0x00000020,
65	.mask_reg = QEIC_CIMR,
66	.pri_code = 2,
67	.pri_reg = QEIC_CIPZCC,
68	},
69	[12] = {
70	.mask = 0x00000010,
71	.mask_reg = QEIC_CIMR,
72	.pri_code = 3,
73	.pri_reg = QEIC_CIPZCC,
74	},
75	[13] = {
76	.mask = 0x00000008,
77	.mask_reg = QEIC_CIMR,
78	.pri_code = 4,
79	.pri_reg = QEIC_CIPZCC,
80	},
81	[14] = {
82	.mask = 0x00000004,
83	.mask_reg = QEIC_CIMR,
84	.pri_code = 5,
85	.pri_reg = QEIC_CIPZCC,
86	},
87	[15] = {
88	.mask = 0x00000002,
89	.mask_reg = QEIC_CIMR,
90	.pri_code = 6,
91	.pri_reg = QEIC_CIPZCC,
92	},
93	[20] = {
94	.mask = 0x10000000,
95	.mask_reg = QEIC_CRIMR,
96	.pri_code = 3,
97	.pri_reg = QEIC_CIPRTA,
98	},
99	[25] = {
100	.mask = 0x00800000,
101	.mask_reg = QEIC_CRIMR,
102	.pri_code = 0,
103	.pri_reg = QEIC_CIPRTB,
104	},
105	[26] = {
106	.mask = 0x00400000,
107	.mask_reg = QEIC_CRIMR,
108	.pri_code = 1,
109	.pri_reg = QEIC_CIPRTB,
110	},
111	[27] = {
112	.mask = 0x00200000,
113	.mask_reg = QEIC_CRIMR,
114	.pri_code = 2,
115	.pri_reg = QEIC_CIPRTB,
116	},
117	[28] = {
118	.mask = 0x00100000,
119	.mask_reg = QEIC_CRIMR,
120	.pri_code = 3,
121	.pri_reg = QEIC_CIPRTB,
122	},
123	[32] = {
124	.mask = 0x80000000,
125	.mask_reg = QEIC_CIMR,
126	.pri_code = 0,
127	.pri_reg = QEIC_CIPXCC,
128	},
129	[33] = {
130	.mask = 0x40000000,
131	.mask_reg = QEIC_CIMR,
132	.pri_code = 1,
133	.pri_reg = QEIC_CIPXCC,
134	},
135	[34] = {
136	.mask = 0x20000000,
137	.mask_reg = QEIC_CIMR,
138	.pri_code = 2,
139	.pri_reg = QEIC_CIPXCC,
140	},
141	[35] = {
142	.mask = 0x10000000,
143	.mask_reg = QEIC_CIMR,
144	.pri_code = 3,
145	.pri_reg = QEIC_CIPXCC,
146	},
147	[36] = {
148	.mask = 0x08000000,
149	.mask_reg = QEIC_CIMR,
150	.pri_code = 4,
151	.pri_reg = QEIC_CIPXCC,
152	},
153	[40] = {
154	.mask = 0x00800000,
155	.mask_reg = QEIC_CIMR,
156	.pri_code = 0,
157	.pri_reg = QEIC_CIPYCC,
158	},
159	[41] = {
160	.mask = 0x00400000,
161	.mask_reg = QEIC_CIMR,
162	.pri_code = 1,
163	.pri_reg = QEIC_CIPYCC,
164	},
165	[42] = {
166	.mask = 0x00200000,
167	.mask_reg = QEIC_CIMR,
168	.pri_code = 2,
169	.pri_reg = QEIC_CIPYCC,
170	},
171	[43] = {
172	.mask = 0x00100000,
173	.mask_reg = QEIC_CIMR,
174	.pri_code = 3,
175	.pri_reg = QEIC_CIPYCC,
176	},
177	};
178
179	static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
180	{
181	return in_be32(base + (reg >> 2));
182	}
183
184	static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
185	u32 value)
186	{
187	out_be32(base + (reg >> 2), value);
188	}
189
190	static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
191	{
192	return irq_desc[virq].chip_data;
193	}
194
195	#define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
196
197	static void qe_ic_unmask_irq(unsigned int virq)
198	{
199	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
200	unsigned int src = virq_to_hw(virq);
201	unsigned long flags;
202	u32 temp;
203
204	spin_lock_irqsave(&qe_ic_lock, flags);
205
206	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
207	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
208	temp \| qe_ic_info[src].mask);
209
210	spin_unlock_irqrestore(&qe_ic_lock, flags);
211	}
212
213	static void qe_ic_mask_irq(unsigned int virq)
214	{
215	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
216	unsigned int src = virq_to_hw(virq);
217	unsigned long flags;
218	u32 temp;
219
220	spin_lock_irqsave(&qe_ic_lock, flags);
221
222	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
223	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
224	temp & ~qe_ic_info[src].mask);
225
2c1d2f34 SW	226	/* Flush the above write before enabling interrupts; otherwise,
	227	* spurious interrupts will sometimes happen. To be 100% sure
	228	* that the write has reached the device before interrupts are
	229	* enabled, the mask register would have to be read back; however,
	230	* this is not required for correctness, only to avoid wasting
	231	* time on a large number of spurious interrupts. In testing,
	232	* a sync reduced the observed spurious interrupts to zero.
	233	*/
	234	mb();
98658538 LY	235
	236	spin_unlock_irqrestore(&qe_ic_lock, flags);
	237	}
	238
	239	static struct irq_chip qe_ic_irq_chip = {
	240	.typename = " QEIC ",
	241	.unmask = qe_ic_unmask_irq,
	242	.mask = qe_ic_mask_irq,
2c1d2f34	243	.mask_ack = qe_ic_mask_irq,
98658538 LY	244	};
	245
	246	static int qe_ic_host_match(struct irq_host h, struct device_node node)
	247	{
98658538	248	/* Exact match, unless qe_ic node is NULL */
52964f87	249	return h->of_node == NULL \|\| h->of_node == node;
98658538 LY	250	}
	251
	252	static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
	253	irq_hw_number_t hw)
	254	{
	255	struct qe_ic *qe_ic = h->host_data;
	256	struct irq_chip *chip;
	257
	258	if (qe_ic_info[hw].mask == 0) {
	259	printk(KERN_ERR "Can't map reserved IRQ \n");
	260	return -EINVAL;
	261	}
	262	/* Default chip */
	263	chip = &qe_ic->hc_irq;
	264
	265	set_irq_chip_data(virq, qe_ic);
	266	get_irq_desc(virq)->status \|= IRQ_LEVEL;
	267
	268	set_irq_chip_and_handler(virq, chip, handle_level_irq);
	269
	270	return 0;
	271	}
	272
	273	static int qe_ic_host_xlate(struct irq_host h, struct device_node ct,
	274	u32 * intspec, unsigned int intsize,
	275	irq_hw_number_t * out_hwirq,
	276	unsigned int *out_flags)
	277	{
	278	*out_hwirq = intspec[0];
	279	if (intsize > 1)
	280	*out_flags = intspec[1];
	281	else
	282	*out_flags = IRQ_TYPE_NONE;
	283	return 0;
	284	}
	285
	286	static struct irq_host_ops qe_ic_host_ops = {
	287	.match = qe_ic_host_match,
	288	.map = qe_ic_host_map,
	289	.xlate = qe_ic_host_xlate,
	290	};
	291
	292	/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
35a84c2f	293	unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
98658538 LY	294	{
	295	int irq;
	296
	297	BUG_ON(qe_ic == NULL);
	298
	299	/* get the interrupt source vector. */
	300	irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
	301
	302	if (irq == 0)
	303	return NO_IRQ;
	304
	305	return irq_linear_revmap(qe_ic->irqhost, irq);
	306	}
	307
	308	/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
35a84c2f	309	unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
98658538 LY	310	{
	311	int irq;
	312
	313	BUG_ON(qe_ic == NULL);
	314
	315	/* get the interrupt source vector. */
	316	irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
	317
	318	if (irq == 0)
	319	return NO_IRQ;
	320
	321	return irq_linear_revmap(qe_ic->irqhost, irq);
	322	}
	323
cccd2102 AV	324	void __init qe_ic_init(struct device_node *node, unsigned int flags,
	325	void (low_handler)(unsigned int irq, struct irq_desc desc),
	326	void (high_handler)(unsigned int irq, struct irq_desc desc))
98658538 LY	327	{
	328	struct qe_ic *qe_ic;
	329	struct resource res;
	330	u32 temp = 0, ret, high_active = 0;
	331
	332	qe_ic = alloc_bootmem(sizeof(struct qe_ic));
	333	if (qe_ic == NULL)
	334	return;
	335
	336	memset(qe_ic, 0, sizeof(struct qe_ic));
98658538	337
52964f87	338	qe_ic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
98658538 LY	339	NR_QE_IC_INTS, &qe_ic_host_ops, 0);
	340	if (qe_ic->irqhost == NULL) {
	341	of_node_put(node);
	342	return;
	343	}
	344
	345	ret = of_address_to_resource(node, 0, &res);
	346	if (ret)
	347	return;
	348
	349	qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
	350
	351	qe_ic->irqhost->host_data = qe_ic;
	352	qe_ic->hc_irq = qe_ic_irq_chip;
	353
	354	qe_ic->virq_high = irq_of_parse_and_map(node, 0);
	355	qe_ic->virq_low = irq_of_parse_and_map(node, 1);
	356
	357	if (qe_ic->virq_low == NO_IRQ) {
	358	printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
	359	return;
	360	}
	361
	362	/* default priority scheme is grouped. If spread mode is */
	363	/* required, configure cicr accordingly. */
	364	if (flags & QE_IC_SPREADMODE_GRP_W)
	365	temp \|= CICR_GWCC;
	366	if (flags & QE_IC_SPREADMODE_GRP_X)
	367	temp \|= CICR_GXCC;
	368	if (flags & QE_IC_SPREADMODE_GRP_Y)
	369	temp \|= CICR_GYCC;
	370	if (flags & QE_IC_SPREADMODE_GRP_Z)
	371	temp \|= CICR_GZCC;
	372	if (flags & QE_IC_SPREADMODE_GRP_RISCA)
	373	temp \|= CICR_GRTA;
	374	if (flags & QE_IC_SPREADMODE_GRP_RISCB)
	375	temp \|= CICR_GRTB;
	376
	377	/* choose destination signal for highest priority interrupt */
	378	if (flags & QE_IC_HIGH_SIGNAL) {
	379	temp \|= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
	380	high_active = 1;
	381	}
	382
	383	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
	384
	385	set_irq_data(qe_ic->virq_low, qe_ic);
cccd2102	386	set_irq_chained_handler(qe_ic->virq_low, low_handler);
98658538	387
cccd2102 AV	388	if (qe_ic->virq_high != NO_IRQ &&
cccd2102 AV	389	qe_ic->virq_high != qe_ic->virq_low) {
98658538	390	set_irq_data(qe_ic->virq_high, qe_ic);
cccd2102	391	set_irq_chained_handler(qe_ic->virq_high, high_handler);
98658538	392	}
98658538 LY	393	}
	394
	395	void qe_ic_set_highest_priority(unsigned int virq, int high)
	396	{
	397	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	398	unsigned int src = virq_to_hw(virq);
	399	u32 temp = 0;
	400
	401	temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
	402
	403	temp &= ~CICR_HP_MASK;
	404	temp \|= src << CICR_HP_SHIFT;
	405
	406	temp &= ~CICR_HPIT_MASK;
	407	temp \|= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
	408
	409	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
	410	}
	411
	412	/* Set Priority level within its group, from 1 to 8 */
	413	int qe_ic_set_priority(unsigned int virq, unsigned int priority)
	414	{
	415	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	416	unsigned int src = virq_to_hw(virq);
	417	u32 temp;
	418
	419	if (priority > 8 \|\| priority == 0)
	420	return -EINVAL;
	421	if (src > 127)
	422	return -EINVAL;
	423	if (qe_ic_info[src].pri_reg == 0)
	424	return -EINVAL;
	425
	426	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
	427
	428	if (priority < 4) {
	429	temp &= ~(0x7 << (32 - priority * 3));
	430	temp \|= qe_ic_info[src].pri_code << (32 - priority * 3);
	431	} else {
	432	temp &= ~(0x7 << (24 - priority * 3));
	433	temp \|= qe_ic_info[src].pri_code << (24 - priority * 3);
	434	}
	435
	436	qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
	437
	438	return 0;
	439	}
	440
	441	/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
	442	int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
	443	{
	444	struct qe_ic *qe_ic = qe_ic_from_irq(virq);
	445	unsigned int src = virq_to_hw(virq);
	446	u32 temp, control_reg = QEIC_CICNR, shift = 0;
	447
	448	if (priority > 2 \|\| priority == 0)
	449	return -EINVAL;
	450
	451	switch (qe_ic_info[src].pri_reg) {
	452	case QEIC_CIPZCC:
	453	shift = CICNR_ZCC1T_SHIFT;
	454	break;
	455	case QEIC_CIPWCC:
	456	shift = CICNR_WCC1T_SHIFT;
457	break;
458	case QEIC_CIPYCC:
459	shift = CICNR_YCC1T_SHIFT;
460	break;
461	case QEIC_CIPXCC:
462	shift = CICNR_XCC1T_SHIFT;
463	break;
464	case QEIC_CIPRTA:
465	shift = CRICR_RTA1T_SHIFT;
466	control_reg = QEIC_CRICR;
467	break;
468	case QEIC_CIPRTB:
469	shift = CRICR_RTB1T_SHIFT;
470	control_reg = QEIC_CRICR;
471	break;
472	default:
473	return -EINVAL;
474	}
475
476	shift += (2 - priority) * 2;
477	temp = qe_ic_read(qe_ic->regs, control_reg);
478	temp &= ~(SIGNAL_MASK << shift);
479	temp \|= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
480	qe_ic_write(qe_ic->regs, control_reg, temp);
481
482	return 0;
483	}
484
485	static struct sysdev_class qe_ic_sysclass = {
af5ca3f4	486	.name = "qe_ic",
98658538 LY	487	};
	488
	489	static struct sys_device device_qe_ic = {
	490	.id = 0,
	491	.cls = &qe_ic_sysclass,
	492	};
	493
	494	static int __init init_qe_ic_sysfs(void)
	495	{
	496	int rc;
	497
	498	printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
	499
	500	rc = sysdev_class_register(&qe_ic_sysclass);
	501	if (rc) {
	502	printk(KERN_ERR "Failed registering qe_ic sys class\n");
	503	return -ENODEV;
	504	}
	505	rc = sysdev_register(&device_qe_ic);
	506	if (rc) {
	507	printk(KERN_ERR "Failed registering qe_ic sys device\n");
	508	return -ENODEV;
	509	}
	510	return 0;
	511	}
	512
	513	subsys_initcall(init_qe_ic_sysfs);