[net-next-2.6.git] / arch / powerpc / sysdev / fsl_msi.c

/*
 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
 *
 * Author: Tony Li <tony.li@freescale.com>
 *	   Jason Jin <Jason.jin@freescale.com>
 *
 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2 of the
 * License.
 *
 */
#include <linux/irq.h>
#include <linux/bootmem.h>
#include <linux/msi.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <asm/prom.h>
#include <asm/hw_irq.h>
#include <asm/ppc-pci.h>
#include <asm/mpic.h>
#include "fsl_msi.h"
#include "fsl_pci.h"

LIST_HEAD(msi_head);

struct fsl_msi_feature {
	u32 fsl_pic_ip;
	u32 msiir_offset;
};

struct fsl_msi_cascade_data {
	struct fsl_msi *msi_data;
	int index;
};

static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
{
	return in_be32(base + (reg >> 2));
}

/*
 * We do not need this actually. The MSIR register has been read once
 * in the cascade interrupt. So, this MSI interrupt has been acked
*/
static void fsl_msi_end_irq(unsigned int virq)
{
}

static struct irq_chip fsl_msi_chip = {
	.irq_mask	= mask_msi_irq,
	.irq_unmask	= unmask_msi_irq,
	.ack		= fsl_msi_end_irq,
	.name		= "FSL-MSI",
};

static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
				irq_hw_number_t hw)
{
	struct fsl_msi *msi_data = h->host_data;
	struct irq_chip *chip = &fsl_msi_chip;

	irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;

	set_irq_chip_data(virq, msi_data);
	set_irq_chip_and_handler(virq, chip, handle_edge_irq);

	return 0;
}

static struct irq_host_ops fsl_msi_host_ops = {
	.map = fsl_msi_host_map,
};

static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
{
	int rc;

	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
			      msi_data->irqhost->of_node);
	if (rc)
		return rc;

	rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
	if (rc < 0) {
		msi_bitmap_free(&msi_data->bitmap);
		return rc;
	}

	return 0;
}

static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
{
	if (type == PCI_CAP_ID_MSIX)
		pr_debug("fslmsi: MSI-X untested, trying anyway.\n");

	return 0;
}

static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct msi_desc *entry;
	struct fsl_msi *msi_data;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;
		msi_data = get_irq_data(entry->irq);
		set_irq_msi(entry->irq, NULL);
		msi_bitmap_free_hwirqs(&msi_data->bitmap,
				       virq_to_hw(entry->irq), 1);
		irq_dispose_mapping(entry->irq);
	}

	return;
}

static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
				struct msi_msg *msg,
				struct fsl_msi *fsl_msi_data)
{
	struct fsl_msi *msi_data = fsl_msi_data;
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	u64 base = fsl_pci_immrbar_base(hose);

	msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base);
	msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base);

	msg->data = hwirq;

	pr_debug("%s: allocated srs: %d, ibs: %d\n",
		__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
}

static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	int rc, hwirq = -ENOMEM;
	unsigned int virq;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct fsl_msi *msi_data;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		list_for_each_entry(msi_data, &msi_head, list) {
			hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
			if (hwirq >= 0)
				break;
		}

		if (hwirq < 0) {
			rc = hwirq;
			pr_debug("%s: fail allocating msi interrupt\n",
					__func__);
			goto out_free;
		}

		virq = irq_create_mapping(msi_data->irqhost, hwirq);

		if (virq == NO_IRQ) {
			pr_debug("%s: fail mapping hwirq 0x%x\n",
					__func__, hwirq);
			msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
			rc = -ENOSPC;
			goto out_free;
		}
		set_irq_data(virq, msi_data);
		set_irq_msi(virq, entry);

		fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
		write_msi_msg(virq, &msg);
	}
	return 0;

out_free:
	/* free by the caller of this function */
	return rc;
}

static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	unsigned int cascade_irq;
	struct fsl_msi *msi_data;
	int msir_index = -1;
	u32 msir_value = 0;
	u32 intr_index;
	u32 have_shift = 0;
	struct fsl_msi_cascade_data *cascade_data;

	cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
	msi_data = cascade_data->msi_data;

	raw_spin_lock(&desc->lock);
	if ((msi_data->feature &  FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
		if (desc->chip->mask_ack)
			desc->chip->mask_ack(irq);
		else {
			desc->chip->mask(irq);
			desc->chip->ack(irq);
		}
	}

	if (unlikely(desc->status & IRQ_INPROGRESS))
		goto unlock;

	msir_index = cascade_data->index;

	if (msir_index >= NR_MSI_REG)
		cascade_irq = NO_IRQ;

	desc->status |= IRQ_INPROGRESS;
	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs,
			msir_index * 0x10);
		break;
	case FSL_PIC_IP_IPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
		break;
	}

	while (msir_value) {
		intr_index = ffs(msir_value) - 1;

		cascade_irq = irq_linear_revmap(msi_data->irqhost,
				msir_index * IRQS_PER_MSI_REG +
					intr_index + have_shift);
		if (cascade_irq != NO_IRQ)
			generic_handle_irq(cascade_irq);
		have_shift += intr_index + 1;
		msir_value = msir_value >> (intr_index + 1);
	}
	desc->status &= ~IRQ_INPROGRESS;

	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		desc->chip->eoi(irq);
		break;
	case FSL_PIC_IP_IPIC:
		if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
			desc->chip->unmask(irq);
		break;
	}
unlock:
	raw_spin_unlock(&desc->lock);
}

static int fsl_of_msi_remove(struct platform_device *ofdev)
{
	struct fsl_msi *msi = ofdev->dev.platform_data;
	int virq, i;
	struct fsl_msi_cascade_data *cascade_data;

	if (msi->list.prev != NULL)
		list_del(&msi->list);
	for (i = 0; i < NR_MSI_REG; i++) {
		virq = msi->msi_virqs[i];
		if (virq != NO_IRQ) {
			cascade_data = get_irq_data(virq);
			kfree(cascade_data);
			irq_dispose_mapping(virq);
		}
	}
	if (msi->bitmap.bitmap)
		msi_bitmap_free(&msi->bitmap);
	iounmap(msi->msi_regs);
	kfree(msi);

	return 0;
}

static int __devinit fsl_of_msi_probe(struct platform_device *dev,
				const struct of_device_id *match)
{
	struct fsl_msi *msi;
	struct resource res;
	int err, i, count;
	int rc;
	int virt_msir;
	const u32 *p;
	struct fsl_msi_feature *features = match->data;
	struct fsl_msi_cascade_data *cascade_data = NULL;
	int len;
	u32 offset;

	printk(KERN_DEBUG "Setting up Freescale MSI support\n");

	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	if (!msi) {
		dev_err(&dev->dev, "No memory for MSI structure\n");
		return -ENOMEM;
	}
	dev->dev.platform_data = msi;

	msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
				      NR_MSI_IRQS, &fsl_msi_host_ops, 0);

	if (msi->irqhost == NULL) {
		dev_err(&dev->dev, "No memory for MSI irqhost\n");
		err = -ENOMEM;
		goto error_out;
	}

	/* Get the MSI reg base */
	err = of_address_to_resource(dev->dev.of_node, 0, &res);
	if (err) {
		dev_err(&dev->dev, "%s resource error!\n",
				dev->dev.of_node->full_name);
		goto error_out;
	}

	msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
	if (!msi->msi_regs) {
		dev_err(&dev->dev, "ioremap problem failed\n");
		goto error_out;
	}

	msi->feature = features->fsl_pic_ip;

	msi->irqhost->host_data = msi;

	msi->msi_addr_hi = 0x0;
	msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);

	rc = fsl_msi_init_allocator(msi);
	if (rc) {
		dev_err(&dev->dev, "Error allocating MSI bitmap\n");
		goto error_out;
	}

	p = of_get_property(dev->dev.of_node, "interrupts", &count);
	if (!p) {
		dev_err(&dev->dev, "no interrupts property found on %s\n",
				dev->dev.of_node->full_name);
		err = -ENODEV;
		goto error_out;
	}
	if (count % 8 != 0) {
		dev_err(&dev->dev, "Malformed interrupts property on %s\n",
				dev->dev.of_node->full_name);
		err = -EINVAL;
		goto error_out;
	}
	offset = 0;
	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
	if (p)
		offset = *p / IRQS_PER_MSI_REG;

	count /= sizeof(u32);
	for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
		virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
		if (virt_msir != NO_IRQ) {
			cascade_data = kzalloc(
					sizeof(struct fsl_msi_cascade_data),
					GFP_KERNEL);
			if (!cascade_data) {
				dev_err(&dev->dev,
					"No memory for MSI cascade data\n");
				err = -ENOMEM;
				goto error_out;
			}
			msi->msi_virqs[i] = virt_msir;
			cascade_data->index = i + offset;
			cascade_data->msi_data = msi;
			set_irq_data(virt_msir, (void *)cascade_data);
			set_irq_chained_handler(virt_msir, fsl_msi_cascade);
		}
	}

	list_add_tail(&msi->list, &msi_head);

	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
	if (!ppc_md.setup_msi_irqs) {
		ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
		ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
		ppc_md.msi_check_device = fsl_msi_check_device;
	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
		dev_err(&dev->dev, "Different MSI driver already installed!\n");
		err = -ENODEV;
		goto error_out;
	}
	return 0;
error_out:
	fsl_of_msi_remove(dev);
	return err;
}

static const struct fsl_msi_feature mpic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	.msiir_offset = 0x140,
};

static const struct fsl_msi_feature ipic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	.msiir_offset = 0x38,
};

static const struct of_device_id fsl_of_msi_ids[] = {
	{
		.compatible = "fsl,mpic-msi",
		.data = (void *)&mpic_msi_feature,
	},
	{
		.compatible = "fsl,ipic-msi",
		.data = (void *)&ipic_msi_feature,
	},
	{}
};

static struct of_platform_driver fsl_of_msi_driver = {
	.driver = {
		.name = "fsl-msi",
		.owner = THIS_MODULE,
		.of_match_table = fsl_of_msi_ids,
	},
	.probe = fsl_of_msi_probe,
	.remove = fsl_of_msi_remove,
};

static __init int fsl_of_msi_init(void)
{
	return of_register_platform_driver(&fsl_of_msi_driver);
}

subsys_initcall(fsl_of_msi_init);
Commit	Line	Data
34e36c15	1	/*
80818813	2	* Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
34e36c15 JJ	3	*
	4	* Author: Tony Li <tony.li@freescale.com>
	5	* Jason Jin <Jason.jin@freescale.com>
	6	*
	7	* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; version 2 of the
	12	* License.
	13	*
	14	*/
	15	#include <linux/irq.h>
	16	#include <linux/bootmem.h>
34e36c15 JJ	17	#include <linux/msi.h>
34e36c15 JJ	18	#include <linux/pci.h>
5a0e3ad6	19	#include <linux/slab.h>
34e36c15 JJ	20	#include <linux/of_platform.h>
	21	#include <sysdev/fsl_soc.h>
	22	#include <asm/prom.h>
	23	#include <asm/hw_irq.h>
	24	#include <asm/ppc-pci.h>
02adac60	25	#include <asm/mpic.h>
34e36c15	26	#include "fsl_msi.h"
b8f44ec2	27	#include "fsl_pci.h"
34e36c15	28
694a7a36 LY	29	LIST_HEAD(msi_head);
694a7a36 LY	30
34e36c15 JJ	31	struct fsl_msi_feature {
	32	u32 fsl_pic_ip;
	33	u32 msiir_offset;
	34	};
	35
02adac60 LY	36	struct fsl_msi_cascade_data {
	37	struct fsl_msi *msi_data;
	38	int index;
	39	};
34e36c15 JJ	40
	41	static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
	42	{
	43	return in_be32(base + (reg >> 2));
	44	}
	45
34e36c15 JJ	46	/*
	47	* We do not need this actually. The MSIR register has been read once
	48	* in the cascade interrupt. So, this MSI interrupt has been acked
	49	*/
	50	static void fsl_msi_end_irq(unsigned int virq)
	51	{
	52	}
	53
	54	static struct irq_chip fsl_msi_chip = {
1c9db525 TG	55	.irq_mask = mask_msi_irq,
1c9db525 TG	56	.irq_unmask = unmask_msi_irq,
34e36c15	57	.ack = fsl_msi_end_irq,
fc380c0c	58	.name = "FSL-MSI",
34e36c15 JJ	59	};
	60
	61	static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
	62	irq_hw_number_t hw)
	63	{
80818813	64	struct fsl_msi *msi_data = h->host_data;
34e36c15 JJ	65	struct irq_chip *chip = &fsl_msi_chip;
34e36c15 JJ	66
6cff46f4	67	irq_to_desc(virq)->status \|= IRQ_TYPE_EDGE_FALLING;
34e36c15	68
80818813	69	set_irq_chip_data(virq, msi_data);
692d1037	70	set_irq_chip_and_handler(virq, chip, handle_edge_irq);
34e36c15 JJ	71
	72	return 0;
	73	}
	74
	75	static struct irq_host_ops fsl_msi_host_ops = {
	76	.map = fsl_msi_host_map,
	77	};
	78
34e36c15 JJ	79	static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
34e36c15 JJ	80	{
692d1037	81	int rc;
34e36c15	82
7e7ab367 ME	83	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
	84	msi_data->irqhost->of_node);
	85	if (rc)
	86	return rc;
34e36c15	87
7e7ab367 ME	88	rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
	89	if (rc < 0) {
	90	msi_bitmap_free(&msi_data->bitmap);
	91	return rc;
34e36c15 JJ	92	}
34e36c15 JJ	93
34e36c15	94	return 0;
34e36c15 JJ	95	}
	96
	97	static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
	98	{
	99	if (type == PCI_CAP_ID_MSIX)
	100	pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
	101
	102	return 0;
	103	}
	104
	105	static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
	106	{
	107	struct msi_desc *entry;
80818813	108	struct fsl_msi *msi_data;
34e36c15 JJ	109
	110	list_for_each_entry(entry, &pdev->msi_list, list) {
	111	if (entry->irq == NO_IRQ)
	112	continue;
02adac60	113	msi_data = get_irq_data(entry->irq);
34e36c15	114	set_irq_msi(entry->irq, NULL);
7e7ab367 ME	115	msi_bitmap_free_hwirqs(&msi_data->bitmap,
7e7ab367 ME	116	virq_to_hw(entry->irq), 1);
34e36c15 JJ	117	irq_dispose_mapping(entry->irq);
	118	}
	119
	120	return;
	121	}
	122
	123	static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
80818813 LCB	124	struct msi_msg *msg,
80818813 LCB	125	struct fsl_msi *fsl_msi_data)
34e36c15	126	{
80818813	127	struct fsl_msi *msi_data = fsl_msi_data;
3da34aae	128	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
b8f44ec2	129	u64 base = fsl_pci_immrbar_base(hose);
34e36c15	130
b8f44ec2 KG	131	msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base);
b8f44ec2 KG	132	msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base);
3da34aae	133
34e36c15 JJ	134	msg->data = hwirq;
	135
	136	pr_debug("%s: allocated srs: %d, ibs: %d\n",
	137	__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
	138	}
	139
	140	static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	141	{
694a7a36	142	int rc, hwirq = -ENOMEM;
34e36c15 JJ	143	unsigned int virq;
	144	struct msi_desc *entry;
	145	struct msi_msg msg;
80818813	146	struct fsl_msi *msi_data;
34e36c15 JJ	147
34e36c15 JJ	148	list_for_each_entry(entry, &pdev->msi_list, list) {
694a7a36 LY	149	list_for_each_entry(msi_data, &msi_head, list) {
	150	hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
	151	if (hwirq >= 0)
	152	break;
	153	}
80818813	154
34e36c15 JJ	155	if (hwirq < 0) {
	156	rc = hwirq;
	157	pr_debug("%s: fail allocating msi interrupt\n",
	158	__func__);
	159	goto out_free;
	160	}
	161
	162	virq = irq_create_mapping(msi_data->irqhost, hwirq);
	163
	164	if (virq == NO_IRQ) {
7e7ab367	165	pr_debug("%s: fail mapping hwirq 0x%x\n",
34e36c15	166	__func__, hwirq);
7e7ab367	167	msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
34e36c15 JJ	168	rc = -ENOSPC;
	169	goto out_free;
	170	}
02adac60	171	set_irq_data(virq, msi_data);
34e36c15 JJ	172	set_irq_msi(virq, entry);
34e36c15 JJ	173
80818813	174	fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
34e36c15 JJ	175	write_msi_msg(virq, &msg);
	176	}
	177	return 0;
	178
	179	out_free:
694a7a36	180	/* free by the caller of this function */
34e36c15 JJ	181	return rc;
	182	}
	183
692d1037	184	static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
34e36c15 JJ	185	{
34e36c15 JJ	186	unsigned int cascade_irq;
02adac60	187	struct fsl_msi *msi_data;
34e36c15 JJ	188	int msir_index = -1;
	189	u32 msir_value = 0;
	190	u32 intr_index;
	191	u32 have_shift = 0;
02adac60 LY	192	struct fsl_msi_cascade_data *cascade_data;
	193
	194	cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
	195	msi_data = cascade_data->msi_data;
34e36c15	196
239007b8	197	raw_spin_lock(&desc->lock);
34e36c15 JJ	198	if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
	199	if (desc->chip->mask_ack)
	200	desc->chip->mask_ack(irq);
	201	else {
	202	desc->chip->mask(irq);
	203	desc->chip->ack(irq);
	204	}
	205	}
	206
	207	if (unlikely(desc->status & IRQ_INPROGRESS))
	208	goto unlock;
	209
02adac60	210	msir_index = cascade_data->index;
34e36c15 JJ	211
	212	if (msir_index >= NR_MSI_REG)
	213	cascade_irq = NO_IRQ;
	214
	215	desc->status \|= IRQ_INPROGRESS;
80818813	216	switch (msi_data->feature & FSL_PIC_IP_MASK) {
34e36c15 JJ	217	case FSL_PIC_IP_MPIC:
	218	msir_value = fsl_msi_read(msi_data->msi_regs,
	219	msir_index * 0x10);
	220	break;
	221	case FSL_PIC_IP_IPIC:
	222	msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
	223	break;
	224	}
	225
	226	while (msir_value) {
	227	intr_index = ffs(msir_value) - 1;
	228
	229	cascade_irq = irq_linear_revmap(msi_data->irqhost,
692d1037 AV	230	msir_index * IRQS_PER_MSI_REG +
692d1037 AV	231	intr_index + have_shift);
34e36c15 JJ	232	if (cascade_irq != NO_IRQ)
34e36c15 JJ	233	generic_handle_irq(cascade_irq);
692d1037 AV	234	have_shift += intr_index + 1;
692d1037 AV	235	msir_value = msir_value >> (intr_index + 1);
34e36c15 JJ	236	}
	237	desc->status &= ~IRQ_INPROGRESS;
	238
	239	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	240	case FSL_PIC_IP_MPIC:
	241	desc->chip->eoi(irq);
	242	break;
	243	case FSL_PIC_IP_IPIC:
	244	if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
	245	desc->chip->unmask(irq);
	246	break;
	247	}
	248	unlock:
239007b8	249	raw_spin_unlock(&desc->lock);
34e36c15 JJ	250	}
34e36c15 JJ	251
a454dc50	252	static int fsl_of_msi_remove(struct platform_device *ofdev)
48059993 LY	253	{
	254	struct fsl_msi *msi = ofdev->dev.platform_data;
	255	int virq, i;
	256	struct fsl_msi_cascade_data *cascade_data;
	257
	258	if (msi->list.prev != NULL)
	259	list_del(&msi->list);
	260	for (i = 0; i < NR_MSI_REG; i++) {
	261	virq = msi->msi_virqs[i];
	262	if (virq != NO_IRQ) {
	263	cascade_data = get_irq_data(virq);
	264	kfree(cascade_data);
	265	irq_dispose_mapping(virq);
	266	}
	267	}
	268	if (msi->bitmap.bitmap)
	269	msi_bitmap_free(&msi->bitmap);
	270	iounmap(msi->msi_regs);
	271	kfree(msi);
	272
	273	return 0;
	274	}
	275
a454dc50	276	static int __devinit fsl_of_msi_probe(struct platform_device *dev,
34e36c15 JJ	277	const struct of_device_id *match)
	278	{
	279	struct fsl_msi *msi;
	280	struct resource res;
	281	int err, i, count;
	282	int rc;
	283	int virt_msir;
	284	const u32 *p;
692d1037	285	struct fsl_msi_feature *features = match->data;
02adac60	286	struct fsl_msi_cascade_data *cascade_data = NULL;
061ca4ad LY	287	int len;
061ca4ad LY	288	u32 offset;
34e36c15 JJ	289
	290	printk(KERN_DEBUG "Setting up Freescale MSI support\n");
	291
	292	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	293	if (!msi) {
	294	dev_err(&dev->dev, "No memory for MSI structure\n");
48059993	295	return -ENOMEM;
34e36c15	296	}
48059993	297	dev->dev.platform_data = msi;
34e36c15	298
61c7a080	299	msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
611cd90c	300	NR_MSI_IRQS, &fsl_msi_host_ops, 0);
34e36c15	301
34e36c15 JJ	302	if (msi->irqhost == NULL) {
34e36c15 JJ	303	dev_err(&dev->dev, "No memory for MSI irqhost\n");
34e36c15 JJ	304	err = -ENOMEM;
	305	goto error_out;
	306	}
	307
	308	/* Get the MSI reg base */
61c7a080	309	err = of_address_to_resource(dev->dev.of_node, 0, &res);
34e36c15 JJ	310	if (err) {
34e36c15 JJ	311	dev_err(&dev->dev, "%s resource error!\n",
61c7a080	312	dev->dev.of_node->full_name);
34e36c15 JJ	313	goto error_out;
	314	}
	315
	316	msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
	317	if (!msi->msi_regs) {
	318	dev_err(&dev->dev, "ioremap problem failed\n");
	319	goto error_out;
	320	}
	321
692d1037	322	msi->feature = features->fsl_pic_ip;
34e36c15 JJ	323
	324	msi->irqhost->host_data = msi;
	325
	326	msi->msi_addr_hi = 0x0;
3da34aae	327	msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
34e36c15 JJ	328
	329	rc = fsl_msi_init_allocator(msi);
	330	if (rc) {
	331	dev_err(&dev->dev, "Error allocating MSI bitmap\n");
	332	goto error_out;
	333	}
	334
61c7a080	335	p = of_get_property(dev->dev.of_node, "interrupts", &count);
34e36c15 JJ	336	if (!p) {
34e36c15 JJ	337	dev_err(&dev->dev, "no interrupts property found on %s\n",
61c7a080	338	dev->dev.of_node->full_name);
34e36c15 JJ	339	err = -ENODEV;
	340	goto error_out;
	341	}
	342	if (count % 8 != 0) {
	343	dev_err(&dev->dev, "Malformed interrupts property on %s\n",
61c7a080	344	dev->dev.of_node->full_name);
34e36c15 JJ	345	err = -EINVAL;
	346	goto error_out;
	347	}
061ca4ad	348	offset = 0;
ee227c57	349	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
061ca4ad LY	350	if (p)
061ca4ad LY	351	offset = *p / IRQS_PER_MSI_REG;
34e36c15 JJ	352
34e36c15 JJ	353	count /= sizeof(u32);
48059993	354	for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
61c7a080	355	virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
34e36c15	356	if (virt_msir != NO_IRQ) {
02adac60 LY	357	cascade_data = kzalloc(
	358	sizeof(struct fsl_msi_cascade_data),
	359	GFP_KERNEL);
	360	if (!cascade_data) {
	361	dev_err(&dev->dev,
	362	"No memory for MSI cascade data\n");
	363	err = -ENOMEM;
	364	goto error_out;
	365	}
48059993	366	msi->msi_virqs[i] = virt_msir;
061ca4ad	367	cascade_data->index = i + offset;
02adac60 LY	368	cascade_data->msi_data = msi;
02adac60 LY	369	set_irq_data(virt_msir, (void *)cascade_data);
34e36c15 JJ	370	set_irq_chained_handler(virt_msir, fsl_msi_cascade);
	371	}
	372	}
	373
694a7a36	374	list_add_tail(&msi->list, &msi_head);
34e36c15	375
80818813 LCB	376	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
	377	if (!ppc_md.setup_msi_irqs) {
	378	ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
	379	ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
	380	ppc_md.msi_check_device = fsl_msi_check_device;
	381	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
	382	dev_err(&dev->dev, "Different MSI driver already installed!\n");
	383	err = -ENODEV;
	384	goto error_out;
	385	}
34e36c15 JJ	386	return 0;
34e36c15 JJ	387	error_out:
48059993	388	fsl_of_msi_remove(dev);
34e36c15 JJ	389	return err;
	390	}
	391
	392	static const struct fsl_msi_feature mpic_msi_feature = {
	393	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	394	.msiir_offset = 0x140,
	395	};
	396
	397	static const struct fsl_msi_feature ipic_msi_feature = {
	398	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	399	.msiir_offset = 0x38,
	400	};
	401
	402	static const struct of_device_id fsl_of_msi_ids[] = {
	403	{
	404	.compatible = "fsl,mpic-msi",
	405	.data = (void *)&mpic_msi_feature,
	406	},
	407	{
	408	.compatible = "fsl,ipic-msi",
	409	.data = (void *)&ipic_msi_feature,
	410	},
	411	{}
	412	};
	413
	414	static struct of_platform_driver fsl_of_msi_driver = {
4018294b GL	415	.driver = {
	416	.name = "fsl-msi",
	417	.owner = THIS_MODULE,
	418	.of_match_table = fsl_of_msi_ids,
	419	},
34e36c15	420	.probe = fsl_of_msi_probe,
48059993	421	.remove = fsl_of_msi_remove,
34e36c15 JJ	422	};
	423
	424	static __init int fsl_of_msi_init(void)
	425	{
	426	return of_register_platform_driver(&fsl_of_msi_driver);
	427	}
	428
	429	subsys_initcall(fsl_of_msi_init);