[net-next-2.6.git] / arch / powerpc / sysdev / fsl_msi.c

/*
 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Tony Li <tony.li@freescale.com>
 *	   Jason Jin <Jason.jin@freescale.com>
 *
 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2 of the
 * License.
 *
 */
#include <linux/irq.h>
#include <linux/bootmem.h>
#include <linux/bitmap.h>
#include <linux/msi.h>
#include <linux/pci.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <asm/prom.h>
#include <asm/hw_irq.h>
#include <asm/ppc-pci.h>
#include "fsl_msi.h"

struct fsl_msi_feature {
	u32 fsl_pic_ip;
	u32 msiir_offset;
};

static struct fsl_msi *fsl_msi;

static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
{
	return in_be32(base + (reg >> 2));
}

/*
 * We do not need this actually. The MSIR register has been read once
 * in the cascade interrupt. So, this MSI interrupt has been acked
*/
static void fsl_msi_end_irq(unsigned int virq)
{
}

static struct irq_chip fsl_msi_chip = {
	.mask		= mask_msi_irq,
	.unmask		= unmask_msi_irq,
	.ack		= fsl_msi_end_irq,
	.typename	= " FSL-MSI  ",
};

static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
				irq_hw_number_t hw)
{
	struct irq_chip *chip = &fsl_msi_chip;

	get_irq_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;

	set_irq_chip_and_handler(virq, chip, handle_edge_irq);

	return 0;
}

static struct irq_host_ops fsl_msi_host_ops = {
	.map = fsl_msi_host_map,
};

static irq_hw_number_t fsl_msi_alloc_hwirqs(struct fsl_msi *msi, int num)
{
	unsigned long flags;
	int order = get_count_order(num);
	int offset;

	spin_lock_irqsave(&msi->bitmap_lock, flags);

	offset = bitmap_find_free_region(msi->fsl_msi_bitmap,
					NR_MSI_IRQS, order);

	spin_unlock_irqrestore(&msi->bitmap_lock, flags);

	pr_debug("%s: allocated 0x%x (2^%d) at offset 0x%x\n",
		__func__, num, order, offset);

	return offset;
}

static void fsl_msi_free_hwirqs(struct fsl_msi *msi, int offset, int num)
{
	unsigned long flags;
	int order = get_count_order(num);

	pr_debug("%s: freeing 0x%x (2^%d) at offset 0x%x\n",
		__func__, num, order, offset);

	spin_lock_irqsave(&msi->bitmap_lock, flags);
	bitmap_release_region(msi->fsl_msi_bitmap, offset, order);
	spin_unlock_irqrestore(&msi->bitmap_lock, flags);
}

static int fsl_msi_free_dt_hwirqs(struct fsl_msi *msi)
{
	int i;
	int len;
	const u32 *p;

	bitmap_allocate_region(msi->fsl_msi_bitmap, 0,
		       get_count_order(NR_MSI_IRQS));

	p = of_get_property(msi->irqhost->of_node, "msi-available-ranges",
			    &len);

	if (!p) {
		/* No msi-available-ranges property,
		 * All the 256 MSI interrupts can be used
		 */
		fsl_msi_free_hwirqs(msi, 0, 0x100);
		return 0;
	}

	if ((len % (2 * sizeof(u32))) != 0) {
		printk(KERN_WARNING "fsl_msi: Malformed msi-available-ranges "
		       "property on %s\n", msi->irqhost->of_node->full_name);
		return -EINVAL;
	}

	/* Format is: (<u32 start> <u32 count>)+ */
	len /= 2 * sizeof(u32);
	for (i = 0; i < len; i++, p += 2)
		fsl_msi_free_hwirqs(msi, *p, *(p + 1));

	return 0;
}

static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
{
	int rc;
	int size = BITS_TO_LONGS(NR_MSI_IRQS) * sizeof(u32);

	msi_data->fsl_msi_bitmap = kzalloc(size, GFP_KERNEL);

	if (msi_data->fsl_msi_bitmap == NULL) {
		pr_debug("%s: ENOMEM allocating allocator bitmap!\n",
				__func__);
		return -ENOMEM;
	}

	rc = fsl_msi_free_dt_hwirqs(msi_data);
	if (rc)
		goto out_free;

	return 0;
out_free:
	kfree(msi_data->fsl_msi_bitmap);

	msi_data->fsl_msi_bitmap = NULL;
	return rc;

}

static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
{
	if (type == PCI_CAP_ID_MSIX)
		pr_debug("fslmsi: MSI-X untested, trying anyway.\n");

	return 0;
}

static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct msi_desc *entry;
	struct fsl_msi *msi_data = fsl_msi;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;
		set_irq_msi(entry->irq, NULL);
		fsl_msi_free_hwirqs(msi_data, virq_to_hw(entry->irq), 1);
		irq_dispose_mapping(entry->irq);
	}

	return;
}

static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
				  struct msi_msg *msg)
{
	struct fsl_msi *msi_data = fsl_msi;

	msg->address_lo = msi_data->msi_addr_lo;
	msg->address_hi = msi_data->msi_addr_hi;
	msg->data = hwirq;

	pr_debug("%s: allocated srs: %d, ibs: %d\n",
		__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
}

static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	irq_hw_number_t hwirq;
	int rc;
	unsigned int virq;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct fsl_msi *msi_data = fsl_msi;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		hwirq = fsl_msi_alloc_hwirqs(msi_data, 1);
		if (hwirq < 0) {
			rc = hwirq;
			pr_debug("%s: fail allocating msi interrupt\n",
					__func__);
			goto out_free;
		}

		virq = irq_create_mapping(msi_data->irqhost, hwirq);

		if (virq == NO_IRQ) {
			pr_debug("%s: fail mapping hwirq 0x%lx\n",
					__func__, hwirq);
			fsl_msi_free_hwirqs(msi_data, hwirq, 1);
			rc = -ENOSPC;
			goto out_free;
		}
		set_irq_msi(virq, entry);

		fsl_compose_msi_msg(pdev, hwirq, &msg);
		write_msi_msg(virq, &msg);
	}
	return 0;

out_free:
	return rc;
}

static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	unsigned int cascade_irq;
	struct fsl_msi *msi_data = fsl_msi;
	int msir_index = -1;
	u32 msir_value = 0;
	u32 intr_index;
	u32 have_shift = 0;

	spin_lock(&desc->lock);
	if ((msi_data->feature &  FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
		if (desc->chip->mask_ack)
			desc->chip->mask_ack(irq);
		else {
			desc->chip->mask(irq);
			desc->chip->ack(irq);
		}
	}

	if (unlikely(desc->status & IRQ_INPROGRESS))
		goto unlock;

	msir_index = (int)desc->handler_data;

	if (msir_index >= NR_MSI_REG)
		cascade_irq = NO_IRQ;

	desc->status |= IRQ_INPROGRESS;
	switch (fsl_msi->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs,
			msir_index * 0x10);
		break;
	case FSL_PIC_IP_IPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
		break;
	}

	while (msir_value) {
		intr_index = ffs(msir_value) - 1;

		cascade_irq = irq_linear_revmap(msi_data->irqhost,
				msir_index * IRQS_PER_MSI_REG +
					intr_index + have_shift);
		if (cascade_irq != NO_IRQ)
			generic_handle_irq(cascade_irq);
		have_shift += intr_index + 1;
		msir_value = msir_value >> (intr_index + 1);
	}
	desc->status &= ~IRQ_INPROGRESS;

	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		desc->chip->eoi(irq);
		break;
	case FSL_PIC_IP_IPIC:
		if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
			desc->chip->unmask(irq);
		break;
	}
unlock:
	spin_unlock(&desc->lock);
}

static int __devinit fsl_of_msi_probe(struct of_device *dev,
				const struct of_device_id *match)
{
	struct fsl_msi *msi;
	struct resource res;
	int err, i, count;
	int rc;
	int virt_msir;
	const u32 *p;
	struct fsl_msi_feature *features = match->data;

	printk(KERN_DEBUG "Setting up Freescale MSI support\n");

	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	if (!msi) {
		dev_err(&dev->dev, "No memory for MSI structure\n");
		err = -ENOMEM;
		goto error_out;
	}

	msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
				      NR_MSI_IRQS, &fsl_msi_host_ops, 0);

	if (msi->irqhost == NULL) {
		dev_err(&dev->dev, "No memory for MSI irqhost\n");
		err = -ENOMEM;
		goto error_out;
	}

	/* Get the MSI reg base */
	err = of_address_to_resource(dev->node, 0, &res);
	if (err) {
		dev_err(&dev->dev, "%s resource error!\n",
				dev->node->full_name);
		goto error_out;
	}

	msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
	if (!msi->msi_regs) {
		dev_err(&dev->dev, "ioremap problem failed\n");
		goto error_out;
	}

	msi->feature = features->fsl_pic_ip;

	msi->irqhost->host_data = msi;

	msi->msi_addr_hi = 0x0;
	msi->msi_addr_lo = res.start + features->msiir_offset;

	rc = fsl_msi_init_allocator(msi);
	if (rc) {
		dev_err(&dev->dev, "Error allocating MSI bitmap\n");
		goto error_out;
	}

	p = of_get_property(dev->node, "interrupts", &count);
	if (!p) {
		dev_err(&dev->dev, "no interrupts property found on %s\n",
				dev->node->full_name);
		err = -ENODEV;
		goto error_out;
	}
	if (count % 8 != 0) {
		dev_err(&dev->dev, "Malformed interrupts property on %s\n",
				dev->node->full_name);
		err = -EINVAL;
		goto error_out;
	}

	count /= sizeof(u32);
	for (i = 0; i < count / 2; i++) {
		if (i > NR_MSI_REG)
			break;
		virt_msir = irq_of_parse_and_map(dev->node, i);
		if (virt_msir != NO_IRQ) {
			set_irq_data(virt_msir, (void *)i);
			set_irq_chained_handler(virt_msir, fsl_msi_cascade);
		}
	}

	fsl_msi = msi;

	WARN_ON(ppc_md.setup_msi_irqs);
	ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
	ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
	ppc_md.msi_check_device = fsl_msi_check_device;
	return 0;
error_out:
	kfree(msi);
	return err;
}

static const struct fsl_msi_feature mpic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	.msiir_offset = 0x140,
};

static const struct fsl_msi_feature ipic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	.msiir_offset = 0x38,
};

static const struct of_device_id fsl_of_msi_ids[] = {
	{
		.compatible = "fsl,mpic-msi",
		.data = (void *)&mpic_msi_feature,
	},
	{
		.compatible = "fsl,ipic-msi",
		.data = (void *)&ipic_msi_feature,
	},
	{}
};

static struct of_platform_driver fsl_of_msi_driver = {
	.name = "fsl-msi",
	.match_table = fsl_of_msi_ids,
	.probe = fsl_of_msi_probe,
};

static __init int fsl_of_msi_init(void)
{
	return of_register_platform_driver(&fsl_of_msi_driver);
}

subsys_initcall(fsl_of_msi_init);
Commit	Line	Data
34e36c15 JJ	1	/*
	2	* Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
	3	*
	4	* Author: Tony Li <tony.li@freescale.com>
	5	* Jason Jin <Jason.jin@freescale.com>
	6	*
	7	* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; version 2 of the
	12	* License.
	13	*
	14	*/
	15	#include <linux/irq.h>
	16	#include <linux/bootmem.h>
	17	#include <linux/bitmap.h>
	18	#include <linux/msi.h>
	19	#include <linux/pci.h>
	20	#include <linux/of_platform.h>
	21	#include <sysdev/fsl_soc.h>
	22	#include <asm/prom.h>
	23	#include <asm/hw_irq.h>
	24	#include <asm/ppc-pci.h>
	25	#include "fsl_msi.h"
	26
	27	struct fsl_msi_feature {
	28	u32 fsl_pic_ip;
	29	u32 msiir_offset;
	30	};
	31
	32	static struct fsl_msi *fsl_msi;
	33
	34	static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
	35	{
	36	return in_be32(base + (reg >> 2));
	37	}
	38
34e36c15 JJ	39	/*
	40	* We do not need this actually. The MSIR register has been read once
	41	* in the cascade interrupt. So, this MSI interrupt has been acked
	42	*/
	43	static void fsl_msi_end_irq(unsigned int virq)
	44	{
	45	}
	46
	47	static struct irq_chip fsl_msi_chip = {
	48	.mask = mask_msi_irq,
	49	.unmask = unmask_msi_irq,
	50	.ack = fsl_msi_end_irq,
	51	.typename = " FSL-MSI ",
	52	};
	53
	54	static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
	55	irq_hw_number_t hw)
	56	{
	57	struct irq_chip *chip = &fsl_msi_chip;
	58
	59	get_irq_desc(virq)->status \|= IRQ_TYPE_EDGE_FALLING;
	60
692d1037	61	set_irq_chip_and_handler(virq, chip, handle_edge_irq);
34e36c15 JJ	62
	63	return 0;
	64	}
	65
	66	static struct irq_host_ops fsl_msi_host_ops = {
	67	.map = fsl_msi_host_map,
	68	};
	69
692d1037	70	static irq_hw_number_t fsl_msi_alloc_hwirqs(struct fsl_msi *msi, int num)
34e36c15 JJ	71	{
34e36c15 JJ	72	unsigned long flags;
692d1037 AV	73	int order = get_count_order(num);
692d1037 AV	74	int offset;
34e36c15 JJ	75
	76	spin_lock_irqsave(&msi->bitmap_lock, flags);
	77
	78	offset = bitmap_find_free_region(msi->fsl_msi_bitmap,
	79	NR_MSI_IRQS, order);
	80
	81	spin_unlock_irqrestore(&msi->bitmap_lock, flags);
	82
	83	pr_debug("%s: allocated 0x%x (2^%d) at offset 0x%x\n",
	84	__func__, num, order, offset);
	85
	86	return offset;
	87	}
	88
692d1037	89	static void fsl_msi_free_hwirqs(struct fsl_msi *msi, int offset, int num)
34e36c15 JJ	90	{
	91	unsigned long flags;
	92	int order = get_count_order(num);
	93
	94	pr_debug("%s: freeing 0x%x (2^%d) at offset 0x%x\n",
	95	__func__, num, order, offset);
	96
	97	spin_lock_irqsave(&msi->bitmap_lock, flags);
	98	bitmap_release_region(msi->fsl_msi_bitmap, offset, order);
	99	spin_unlock_irqrestore(&msi->bitmap_lock, flags);
	100	}
	101
	102	static int fsl_msi_free_dt_hwirqs(struct fsl_msi *msi)
	103	{
692d1037 AV	104	int i;
692d1037 AV	105	int len;
34e36c15 JJ	106	const u32 *p;
	107
	108	bitmap_allocate_region(msi->fsl_msi_bitmap, 0,
	109	get_count_order(NR_MSI_IRQS));
	110
611cd90c ME	111	p = of_get_property(msi->irqhost->of_node, "msi-available-ranges",
611cd90c ME	112	&len);
34e36c15 JJ	113
	114	if (!p) {
	115	/* No msi-available-ranges property,
	116	* All the 256 MSI interrupts can be used
	117	*/
	118	fsl_msi_free_hwirqs(msi, 0, 0x100);
	119	return 0;
	120	}
	121
	122	if ((len % (2 * sizeof(u32))) != 0) {
	123	printk(KERN_WARNING "fsl_msi: Malformed msi-available-ranges "
611cd90c	124	"property on %s\n", msi->irqhost->of_node->full_name);
34e36c15 JJ	125	return -EINVAL;
	126	}
	127
	128	/* Format is: (<u32 start> <u32 count>)+ */
	129	len /= 2 * sizeof(u32);
	130	for (i = 0; i < len; i++, p += 2)
	131	fsl_msi_free_hwirqs(msi, p, (p + 1));
	132
	133	return 0;
	134	}
	135
	136	static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
	137	{
692d1037 AV	138	int rc;
692d1037 AV	139	int size = BITS_TO_LONGS(NR_MSI_IRQS) * sizeof(u32);
34e36c15 JJ	140
	141	msi_data->fsl_msi_bitmap = kzalloc(size, GFP_KERNEL);
	142
	143	if (msi_data->fsl_msi_bitmap == NULL) {
	144	pr_debug("%s: ENOMEM allocating allocator bitmap!\n",
	145	__func__);
	146	return -ENOMEM;
	147	}
	148
	149	rc = fsl_msi_free_dt_hwirqs(msi_data);
	150	if (rc)
	151	goto out_free;
	152
	153	return 0;
	154	out_free:
	155	kfree(msi_data->fsl_msi_bitmap);
	156
	157	msi_data->fsl_msi_bitmap = NULL;
	158	return rc;
	159
	160	}
	161
	162	static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
	163	{
	164	if (type == PCI_CAP_ID_MSIX)
	165	pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
	166
	167	return 0;
	168	}
	169
	170	static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
	171	{
	172	struct msi_desc *entry;
	173	struct fsl_msi *msi_data = fsl_msi;
	174
	175	list_for_each_entry(entry, &pdev->msi_list, list) {
	176	if (entry->irq == NO_IRQ)
	177	continue;
	178	set_irq_msi(entry->irq, NULL);
	179	fsl_msi_free_hwirqs(msi_data, virq_to_hw(entry->irq), 1);
	180	irq_dispose_mapping(entry->irq);
	181	}
	182
	183	return;
	184	}
	185
	186	static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
	187	struct msi_msg *msg)
	188	{
	189	struct fsl_msi *msi_data = fsl_msi;
	190
	191	msg->address_lo = msi_data->msi_addr_lo;
	192	msg->address_hi = msi_data->msi_addr_hi;
	193	msg->data = hwirq;
	194
	195	pr_debug("%s: allocated srs: %d, ibs: %d\n",
	196	__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
	197	}
	198
	199	static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	200	{
	201	irq_hw_number_t hwirq;
	202	int rc;
	203	unsigned int virq;
204	struct msi_desc *entry;
205	struct msi_msg msg;
206	struct fsl_msi *msi_data = fsl_msi;
207
208	list_for_each_entry(entry, &pdev->msi_list, list) {
209	hwirq = fsl_msi_alloc_hwirqs(msi_data, 1);
210	if (hwirq < 0) {
211	rc = hwirq;
212	pr_debug("%s: fail allocating msi interrupt\n",
213	__func__);
214	goto out_free;
215	}
216
217	virq = irq_create_mapping(msi_data->irqhost, hwirq);
218
219	if (virq == NO_IRQ) {
220	pr_debug("%s: fail mapping hwirq 0x%lx\n",
221	__func__, hwirq);
222	fsl_msi_free_hwirqs(msi_data, hwirq, 1);
223	rc = -ENOSPC;
224	goto out_free;
225	}
226	set_irq_msi(virq, entry);
227
228	fsl_compose_msi_msg(pdev, hwirq, &msg);
229	write_msi_msg(virq, &msg);
230	}
231	return 0;
232
233	out_free:
234	return rc;
235	}
236
692d1037	237	static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
34e36c15 JJ	238	{
	239	unsigned int cascade_irq;
	240	struct fsl_msi *msi_data = fsl_msi;
	241	int msir_index = -1;
	242	u32 msir_value = 0;
	243	u32 intr_index;
	244	u32 have_shift = 0;
	245
	246	spin_lock(&desc->lock);
	247	if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
	248	if (desc->chip->mask_ack)
	249	desc->chip->mask_ack(irq);
	250	else {
	251	desc->chip->mask(irq);
	252	desc->chip->ack(irq);
	253	}
	254	}
	255
	256	if (unlikely(desc->status & IRQ_INPROGRESS))
	257	goto unlock;
	258
692d1037	259	msir_index = (int)desc->handler_data;
34e36c15 JJ	260
	261	if (msir_index >= NR_MSI_REG)
	262	cascade_irq = NO_IRQ;
	263
	264	desc->status \|= IRQ_INPROGRESS;
	265	switch (fsl_msi->feature & FSL_PIC_IP_MASK) {
	266	case FSL_PIC_IP_MPIC:
	267	msir_value = fsl_msi_read(msi_data->msi_regs,
	268	msir_index * 0x10);
	269	break;
	270	case FSL_PIC_IP_IPIC:
	271	msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
	272	break;
	273	}
	274
	275	while (msir_value) {
	276	intr_index = ffs(msir_value) - 1;
	277
	278	cascade_irq = irq_linear_revmap(msi_data->irqhost,
692d1037 AV	279	msir_index * IRQS_PER_MSI_REG +
692d1037 AV	280	intr_index + have_shift);
34e36c15 JJ	281	if (cascade_irq != NO_IRQ)
34e36c15 JJ	282	generic_handle_irq(cascade_irq);
692d1037 AV	283	have_shift += intr_index + 1;
692d1037 AV	284	msir_value = msir_value >> (intr_index + 1);
34e36c15 JJ	285	}
	286	desc->status &= ~IRQ_INPROGRESS;
	287
	288	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	289	case FSL_PIC_IP_MPIC:
	290	desc->chip->eoi(irq);
	291	break;
	292	case FSL_PIC_IP_IPIC:
	293	if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
	294	desc->chip->unmask(irq);
	295	break;
	296	}
	297	unlock:
	298	spin_unlock(&desc->lock);
	299	}
	300
	301	static int __devinit fsl_of_msi_probe(struct of_device *dev,
	302	const struct of_device_id *match)
	303	{
	304	struct fsl_msi *msi;
	305	struct resource res;
	306	int err, i, count;
	307	int rc;
	308	int virt_msir;
	309	const u32 *p;
692d1037	310	struct fsl_msi_feature *features = match->data;
34e36c15 JJ	311
	312	printk(KERN_DEBUG "Setting up Freescale MSI support\n");
	313
	314	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	315	if (!msi) {
	316	dev_err(&dev->dev, "No memory for MSI structure\n");
	317	err = -ENOMEM;
	318	goto error_out;
	319	}
	320
611cd90c ME	321	msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
611cd90c ME	322	NR_MSI_IRQS, &fsl_msi_host_ops, 0);
34e36c15	323
34e36c15 JJ	324	if (msi->irqhost == NULL) {
34e36c15 JJ	325	dev_err(&dev->dev, "No memory for MSI irqhost\n");
34e36c15 JJ	326	err = -ENOMEM;
	327	goto error_out;
	328	}
	329
	330	/* Get the MSI reg base */
	331	err = of_address_to_resource(dev->node, 0, &res);
	332	if (err) {
	333	dev_err(&dev->dev, "%s resource error!\n",
	334	dev->node->full_name);
	335	goto error_out;
	336	}
	337
	338	msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
	339	if (!msi->msi_regs) {
	340	dev_err(&dev->dev, "ioremap problem failed\n");
	341	goto error_out;
	342	}
	343
692d1037	344	msi->feature = features->fsl_pic_ip;
34e36c15 JJ	345
	346	msi->irqhost->host_data = msi;
	347
	348	msi->msi_addr_hi = 0x0;
692d1037	349	msi->msi_addr_lo = res.start + features->msiir_offset;
34e36c15 JJ	350
	351	rc = fsl_msi_init_allocator(msi);
	352	if (rc) {
	353	dev_err(&dev->dev, "Error allocating MSI bitmap\n");
	354	goto error_out;
	355	}
	356
	357	p = of_get_property(dev->node, "interrupts", &count);
	358	if (!p) {
	359	dev_err(&dev->dev, "no interrupts property found on %s\n",
	360	dev->node->full_name);
	361	err = -ENODEV;
	362	goto error_out;
	363	}
	364	if (count % 8 != 0) {
	365	dev_err(&dev->dev, "Malformed interrupts property on %s\n",
	366	dev->node->full_name);
	367	err = -EINVAL;
	368	goto error_out;
	369	}
	370
	371	count /= sizeof(u32);
	372	for (i = 0; i < count / 2; i++) {
	373	if (i > NR_MSI_REG)
	374	break;
	375	virt_msir = irq_of_parse_and_map(dev->node, i);
	376	if (virt_msir != NO_IRQ) {
	377	set_irq_data(virt_msir, (void *)i);
	378	set_irq_chained_handler(virt_msir, fsl_msi_cascade);
	379	}
	380	}
	381
	382	fsl_msi = msi;
	383
	384	WARN_ON(ppc_md.setup_msi_irqs);
	385	ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
	386	ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
	387	ppc_md.msi_check_device = fsl_msi_check_device;
	388	return 0;
	389	error_out:
	390	kfree(msi);
	391	return err;
	392	}
	393
	394	static const struct fsl_msi_feature mpic_msi_feature = {
	395	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	396	.msiir_offset = 0x140,
	397	};
	398
	399	static const struct fsl_msi_feature ipic_msi_feature = {
	400	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	401	.msiir_offset = 0x38,
	402	};
	403
	404	static const struct of_device_id fsl_of_msi_ids[] = {
	405	{
	406	.compatible = "fsl,mpic-msi",
	407	.data = (void *)&mpic_msi_feature,
	408	},
	409	{
	410	.compatible = "fsl,ipic-msi",
	411	.data = (void *)&ipic_msi_feature,
	412	},
	413	{}
414	};
415
416	static struct of_platform_driver fsl_of_msi_driver = {
417	.name = "fsl-msi",
418	.match_table = fsl_of_msi_ids,
419	.probe = fsl_of_msi_probe,
420	};
421
422	static __init int fsl_of_msi_init(void)
423	{
424	return of_register_platform_driver(&fsl_of_msi_driver);
425	}
426
427	subsys_initcall(fsl_of_msi_init);