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Commit | Line | Data |
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007e8f51 DG |
1 | /* |
2 | * arch/powerpc/platforms/pseries/xics.c | |
1da177e4 LT |
3 | * |
4 | * Copyright 2000 IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
0ebfff14 | 11 | |
1da177e4 LT |
12 | #include <linux/types.h> |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/interrupt.h> | |
1da177e4 | 18 | #include <linux/init.h> |
1da177e4 LT |
19 | #include <linux/radix-tree.h> |
20 | #include <linux/cpu.h> | |
8435b027 | 21 | #include <linux/msi.h> |
188bdddd | 22 | #include <linux/of.h> |
49bd3647 | 23 | #include <linux/percpu.h> |
0ebfff14 | 24 | |
57cfb814 | 25 | #include <asm/firmware.h> |
1da177e4 LT |
26 | #include <asm/io.h> |
27 | #include <asm/pgtable.h> | |
28 | #include <asm/smp.h> | |
29 | #include <asm/rtas.h> | |
1da177e4 LT |
30 | #include <asm/hvcall.h> |
31 | #include <asm/machdep.h> | |
1da177e4 | 32 | |
007e8f51 | 33 | #include "xics.h" |
b9377ffc | 34 | #include "plpar_wrappers.h" |
007e8f51 | 35 | |
0641cc91 MM |
36 | static struct irq_host *xics_host; |
37 | ||
1da177e4 LT |
38 | #define XICS_IPI 2 |
39 | #define XICS_IRQ_SPURIOUS 0 | |
40 | ||
41 | /* Want a priority other than 0. Various HW issues require this. */ | |
42 | #define DEFAULT_PRIORITY 5 | |
43 | ||
007e8f51 | 44 | /* |
1da177e4 | 45 | * Mark IPIs as higher priority so we can take them inside interrupts that |
6714465e | 46 | * arent marked IRQF_DISABLED |
1da177e4 LT |
47 | */ |
48 | #define IPI_PRIORITY 4 | |
49 | ||
49bd3647 MN |
50 | /* The least favored priority */ |
51 | #define LOWEST_PRIORITY 0xFF | |
52 | ||
53 | /* The number of priorities defined above */ | |
54 | #define MAX_NUM_PRIORITIES 3 | |
55 | ||
0641cc91 MM |
56 | static unsigned int default_server = 0xFF; |
57 | static unsigned int default_distrib_server = 0; | |
58 | static unsigned int interrupt_server_size = 8; | |
59 | ||
60 | /* RTAS service tokens */ | |
61 | static int ibm_get_xive; | |
62 | static int ibm_set_xive; | |
63 | static int ibm_int_on; | |
64 | static int ibm_int_off; | |
65 | ||
49bd3647 MN |
66 | struct xics_cppr { |
67 | unsigned char stack[MAX_NUM_PRIORITIES]; | |
68 | int index; | |
69 | }; | |
70 | ||
71 | static DEFINE_PER_CPU(struct xics_cppr, xics_cppr); | |
0641cc91 MM |
72 | |
73 | /* Direct hardware low level accessors */ | |
74 | ||
75 | /* The part of the interrupt presentation layer that we care about */ | |
1da177e4 LT |
76 | struct xics_ipl { |
77 | union { | |
78 | u32 word; | |
79 | u8 bytes[4]; | |
80 | } xirr_poll; | |
81 | union { | |
82 | u32 word; | |
83 | u8 bytes[4]; | |
84 | } xirr; | |
85 | u32 dummy; | |
86 | union { | |
87 | u32 word; | |
88 | u8 bytes[4]; | |
89 | } qirr; | |
90 | }; | |
91 | ||
92 | static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS]; | |
93 | ||
d7cf0edb | 94 | static inline unsigned int direct_xirr_info_get(void) |
1da177e4 | 95 | { |
d7cf0edb MM |
96 | int cpu = smp_processor_id(); |
97 | ||
98 | return in_be32(&xics_per_cpu[cpu]->xirr.word); | |
1da177e4 LT |
99 | } |
100 | ||
9dc2d441 | 101 | static inline void direct_xirr_info_set(unsigned int value) |
1da177e4 | 102 | { |
d7cf0edb MM |
103 | int cpu = smp_processor_id(); |
104 | ||
105 | out_be32(&xics_per_cpu[cpu]->xirr.word, value); | |
1da177e4 LT |
106 | } |
107 | ||
d7cf0edb | 108 | static inline void direct_cppr_info(u8 value) |
1da177e4 | 109 | { |
d7cf0edb MM |
110 | int cpu = smp_processor_id(); |
111 | ||
112 | out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value); | |
1da177e4 LT |
113 | } |
114 | ||
b9e5b4e6 | 115 | static inline void direct_qirr_info(int n_cpu, u8 value) |
1da177e4 LT |
116 | { |
117 | out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value); | |
118 | } | |
119 | ||
1da177e4 | 120 | |
b9e5b4e6 | 121 | /* LPAR low level accessors */ |
1da177e4 | 122 | |
f09b7b2a | 123 | static inline unsigned int lpar_xirr_info_get(unsigned char cppr) |
1da177e4 LT |
124 | { |
125 | unsigned long lpar_rc; | |
007e8f51 | 126 | unsigned long return_value; |
1da177e4 | 127 | |
f09b7b2a | 128 | lpar_rc = plpar_xirr(&return_value, cppr); |
706c8c93 | 129 | if (lpar_rc != H_SUCCESS) |
8354be9c | 130 | panic(" bad return code xirr - rc = %lx\n", lpar_rc); |
0ebfff14 | 131 | return (unsigned int)return_value; |
1da177e4 LT |
132 | } |
133 | ||
9dc2d441 | 134 | static inline void lpar_xirr_info_set(unsigned int value) |
1da177e4 LT |
135 | { |
136 | unsigned long lpar_rc; | |
1da177e4 | 137 | |
9dc2d441 | 138 | lpar_rc = plpar_eoi(value); |
706c8c93 | 139 | if (lpar_rc != H_SUCCESS) |
9dc2d441 MM |
140 | panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc, |
141 | value); | |
1da177e4 LT |
142 | } |
143 | ||
d7cf0edb | 144 | static inline void lpar_cppr_info(u8 value) |
1da177e4 LT |
145 | { |
146 | unsigned long lpar_rc; | |
147 | ||
148 | lpar_rc = plpar_cppr(value); | |
706c8c93 | 149 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 150 | panic("bad return code cppr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
151 | } |
152 | ||
b9e5b4e6 | 153 | static inline void lpar_qirr_info(int n_cpu , u8 value) |
1da177e4 LT |
154 | { |
155 | unsigned long lpar_rc; | |
156 | ||
157 | lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value); | |
706c8c93 | 158 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 159 | panic("bad return code qirr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
160 | } |
161 | ||
1da177e4 | 162 | |
0641cc91 | 163 | /* Interface to generic irq subsystem */ |
1da177e4 LT |
164 | |
165 | #ifdef CONFIG_SMP | |
64fe220c AB |
166 | /* |
167 | * For the moment we only implement delivery to all cpus or one cpu. | |
168 | * | |
169 | * If the requested affinity is cpu_all_mask, we set global affinity. | |
170 | * If not we set it to the first cpu in the mask, even if multiple cpus | |
171 | * are set. This is so things like irqbalance (which set core and package | |
172 | * wide affinities) do the right thing. | |
173 | */ | |
174 | static int get_irq_server(unsigned int virq, const struct cpumask *cpumask, | |
92cb3694 | 175 | unsigned int strict_check) |
1da177e4 | 176 | { |
1da177e4 LT |
177 | |
178 | if (!distribute_irqs) | |
179 | return default_server; | |
180 | ||
64fe220c AB |
181 | if (!cpumask_equal(cpumask, cpu_all_mask)) { |
182 | int server = cpumask_first_and(cpu_online_mask, cpumask); | |
7ccb4a66 | 183 | |
64fe220c | 184 | if (server < nr_cpu_ids) |
7ccb4a66 MK |
185 | return get_hard_smp_processor_id(server); |
186 | ||
187 | if (strict_check) | |
188 | return -1; | |
1da177e4 LT |
189 | } |
190 | ||
64fe220c AB |
191 | /* |
192 | * Workaround issue with some versions of JS20 firmware that | |
193 | * deliver interrupts to cpus which haven't been started. This | |
194 | * happens when using the maxcpus= boot option. | |
195 | */ | |
196 | if (cpumask_equal(cpu_online_mask, cpu_present_mask)) | |
7ccb4a66 | 197 | return default_distrib_server; |
1da177e4 | 198 | |
7ccb4a66 | 199 | return default_server; |
1da177e4 LT |
200 | } |
201 | #else | |
bf647faf | 202 | #define get_irq_server(virq, cpumask, strict_check) (default_server) |
1da177e4 LT |
203 | #endif |
204 | ||
b9e5b4e6 | 205 | static void xics_unmask_irq(unsigned int virq) |
1da177e4 LT |
206 | { |
207 | unsigned int irq; | |
208 | int call_status; | |
7ccb4a66 | 209 | int server; |
1da177e4 | 210 | |
b69e9e93 | 211 | pr_devel("xics: unmask virq %d\n", virq); |
0ebfff14 BH |
212 | |
213 | irq = (unsigned int)irq_map[virq].hwirq; | |
b69e9e93 | 214 | pr_devel(" -> map to hwirq 0x%x\n", irq); |
0ebfff14 | 215 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
1da177e4 LT |
216 | return; |
217 | ||
64fe220c | 218 | server = get_irq_server(virq, irq_to_desc(virq)->affinity, 0); |
b9e5b4e6 | 219 | |
1da177e4 LT |
220 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, |
221 | DEFAULT_PRIORITY); | |
222 | if (call_status != 0) { | |
2172fe87 MM |
223 | printk(KERN_ERR |
224 | "%s: ibm_set_xive irq %u server %x returned %d\n", | |
225 | __func__, irq, server, call_status); | |
1da177e4 LT |
226 | return; |
227 | } | |
228 | ||
229 | /* Now unmask the interrupt (often a no-op) */ | |
230 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); | |
231 | if (call_status != 0) { | |
2172fe87 MM |
232 | printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", |
233 | __func__, irq, call_status); | |
1da177e4 LT |
234 | return; |
235 | } | |
236 | } | |
237 | ||
0641cc91 MM |
238 | static unsigned int xics_startup(unsigned int virq) |
239 | { | |
8435b027 AD |
240 | /* |
241 | * The generic MSI code returns with the interrupt disabled on the | |
242 | * card, using the MSI mask bits. Firmware doesn't appear to unmask | |
243 | * at that level, so we do it here by hand. | |
244 | */ | |
245 | if (irq_to_desc(virq)->msi_desc) | |
246 | unmask_msi_irq(virq); | |
247 | ||
0641cc91 MM |
248 | /* unmask it */ |
249 | xics_unmask_irq(virq); | |
250 | return 0; | |
251 | } | |
252 | ||
b9e5b4e6 | 253 | static void xics_mask_real_irq(unsigned int irq) |
1da177e4 LT |
254 | { |
255 | int call_status; | |
1da177e4 LT |
256 | |
257 | if (irq == XICS_IPI) | |
258 | return; | |
259 | ||
260 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); | |
261 | if (call_status != 0) { | |
2172fe87 MM |
262 | printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", |
263 | __func__, irq, call_status); | |
1da177e4 LT |
264 | return; |
265 | } | |
266 | ||
1da177e4 | 267 | /* Have to set XIVE to 0xff to be able to remove a slot */ |
673aeb76 MO |
268 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, |
269 | default_server, 0xff); | |
1da177e4 | 270 | if (call_status != 0) { |
2172fe87 MM |
271 | printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", |
272 | __func__, irq, call_status); | |
1da177e4 LT |
273 | return; |
274 | } | |
275 | } | |
276 | ||
b9e5b4e6 | 277 | static void xics_mask_irq(unsigned int virq) |
1da177e4 LT |
278 | { |
279 | unsigned int irq; | |
280 | ||
b69e9e93 | 281 | pr_devel("xics: mask virq %d\n", virq); |
0ebfff14 BH |
282 | |
283 | irq = (unsigned int)irq_map[virq].hwirq; | |
284 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
285 | return; | |
286 | xics_mask_real_irq(irq); | |
b9e5b4e6 BH |
287 | } |
288 | ||
0641cc91 | 289 | static void xics_mask_unknown_vec(unsigned int vec) |
1da177e4 | 290 | { |
0641cc91 MM |
291 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); |
292 | xics_mask_real_irq(vec); | |
1da177e4 LT |
293 | } |
294 | ||
8767e9ba | 295 | static inline unsigned int xics_xirr_vector(unsigned int xirr) |
1da177e4 | 296 | { |
8767e9ba MM |
297 | /* |
298 | * The top byte is the old cppr, to be restored on EOI. | |
299 | * The remaining 24 bits are the vector. | |
300 | */ | |
301 | return xirr & 0x00ffffff; | |
302 | } | |
303 | ||
49bd3647 MN |
304 | static void push_cppr(unsigned int vec) |
305 | { | |
306 | struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); | |
307 | ||
308 | if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1)) | |
309 | return; | |
310 | ||
311 | if (vec == XICS_IPI) | |
312 | os_cppr->stack[++os_cppr->index] = IPI_PRIORITY; | |
313 | else | |
314 | os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY; | |
315 | } | |
316 | ||
8767e9ba MM |
317 | static unsigned int xics_get_irq_direct(void) |
318 | { | |
319 | unsigned int xirr = direct_xirr_info_get(); | |
320 | unsigned int vec = xics_xirr_vector(xirr); | |
321 | unsigned int irq; | |
1da177e4 | 322 | |
b9e5b4e6 BH |
323 | if (vec == XICS_IRQ_SPURIOUS) |
324 | return NO_IRQ; | |
8767e9ba | 325 | |
967e012e | 326 | irq = irq_radix_revmap_lookup(xics_host, vec); |
49bd3647 MN |
327 | if (likely(irq != NO_IRQ)) { |
328 | push_cppr(vec); | |
0ebfff14 | 329 | return irq; |
49bd3647 | 330 | } |
b9e5b4e6 | 331 | |
8767e9ba MM |
332 | /* We don't have a linux mapping, so have rtas mask it. */ |
333 | xics_mask_unknown_vec(vec); | |
1da177e4 | 334 | |
8767e9ba MM |
335 | /* We might learn about it later, so EOI it */ |
336 | direct_xirr_info_set(xirr); | |
337 | return NO_IRQ; | |
b9e5b4e6 BH |
338 | } |
339 | ||
35a84c2f | 340 | static unsigned int xics_get_irq_lpar(void) |
1da177e4 | 341 | { |
f09b7b2a MN |
342 | struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); |
343 | unsigned int xirr = lpar_xirr_info_get(os_cppr->stack[os_cppr->index]); | |
8767e9ba MM |
344 | unsigned int vec = xics_xirr_vector(xirr); |
345 | unsigned int irq; | |
346 | ||
347 | if (vec == XICS_IRQ_SPURIOUS) | |
348 | return NO_IRQ; | |
349 | ||
350 | irq = irq_radix_revmap_lookup(xics_host, vec); | |
49bd3647 MN |
351 | if (likely(irq != NO_IRQ)) { |
352 | push_cppr(vec); | |
8767e9ba | 353 | return irq; |
49bd3647 | 354 | } |
8767e9ba MM |
355 | |
356 | /* We don't have a linux mapping, so have RTAS mask it. */ | |
357 | xics_mask_unknown_vec(vec); | |
358 | ||
359 | /* We might learn about it later, so EOI it */ | |
360 | lpar_xirr_info_set(xirr); | |
361 | return NO_IRQ; | |
b9e5b4e6 BH |
362 | } |
363 | ||
49bd3647 MN |
364 | static unsigned char pop_cppr(void) |
365 | { | |
366 | struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); | |
367 | ||
368 | if (WARN_ON(os_cppr->index < 1)) | |
369 | return LOWEST_PRIORITY; | |
370 | ||
371 | return os_cppr->stack[--os_cppr->index]; | |
372 | } | |
373 | ||
0641cc91 | 374 | static void xics_eoi_direct(unsigned int virq) |
b9e5b4e6 | 375 | { |
0641cc91 | 376 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
b9e5b4e6 | 377 | |
0641cc91 | 378 | iosync(); |
49bd3647 | 379 | direct_xirr_info_set((pop_cppr() << 24) | irq); |
b9e5b4e6 BH |
380 | } |
381 | ||
0641cc91 | 382 | static void xics_eoi_lpar(unsigned int virq) |
b9e5b4e6 | 383 | { |
0641cc91 | 384 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
1da177e4 | 385 | |
b9e5b4e6 | 386 | iosync(); |
49bd3647 | 387 | lpar_xirr_info_set((pop_cppr() << 24) | irq); |
b9e5b4e6 BH |
388 | } |
389 | ||
d5dedd45 | 390 | static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) |
b9e5b4e6 BH |
391 | { |
392 | unsigned int irq; | |
393 | int status; | |
394 | int xics_status[2]; | |
7ccb4a66 | 395 | int irq_server; |
b9e5b4e6 | 396 | |
0ebfff14 BH |
397 | irq = (unsigned int)irq_map[virq].hwirq; |
398 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
d5dedd45 | 399 | return -1; |
b9e5b4e6 BH |
400 | |
401 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
402 | ||
403 | if (status) { | |
2172fe87 MM |
404 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
405 | __func__, irq, status); | |
d5dedd45 | 406 | return -1; |
b9e5b4e6 BH |
407 | } |
408 | ||
64fe220c | 409 | irq_server = get_irq_server(virq, cpumask, 1); |
7ccb4a66 MK |
410 | if (irq_server == -1) { |
411 | char cpulist[128]; | |
412 | cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask); | |
2172fe87 MM |
413 | printk(KERN_WARNING |
414 | "%s: No online cpus in the mask %s for irq %d\n", | |
415 | __func__, cpulist, virq); | |
d5dedd45 | 416 | return -1; |
b9e5b4e6 BH |
417 | } |
418 | ||
419 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | |
7ccb4a66 | 420 | irq, irq_server, xics_status[1]); |
b9e5b4e6 BH |
421 | |
422 | if (status) { | |
2172fe87 MM |
423 | printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", |
424 | __func__, irq, status); | |
d5dedd45 | 425 | return -1; |
b9e5b4e6 | 426 | } |
d5dedd45 YL |
427 | |
428 | return 0; | |
b9e5b4e6 BH |
429 | } |
430 | ||
431 | static struct irq_chip xics_pic_direct = { | |
fc380c0c | 432 | .name = "XICS", |
b9e5b4e6 BH |
433 | .startup = xics_startup, |
434 | .mask = xics_mask_irq, | |
435 | .unmask = xics_unmask_irq, | |
436 | .eoi = xics_eoi_direct, | |
437 | .set_affinity = xics_set_affinity | |
438 | }; | |
439 | ||
b9e5b4e6 | 440 | static struct irq_chip xics_pic_lpar = { |
fc380c0c | 441 | .name = "XICS", |
b9e5b4e6 BH |
442 | .startup = xics_startup, |
443 | .mask = xics_mask_irq, | |
444 | .unmask = xics_unmask_irq, | |
445 | .eoi = xics_eoi_lpar, | |
446 | .set_affinity = xics_set_affinity | |
447 | }; | |
448 | ||
0641cc91 MM |
449 | |
450 | /* Interface to arch irq controller subsystem layer */ | |
451 | ||
1af9fa89 ME |
452 | /* Points to the irq_chip we're actually using */ |
453 | static struct irq_chip *xics_irq_chip; | |
b9e5b4e6 | 454 | |
0ebfff14 | 455 | static int xics_host_match(struct irq_host *h, struct device_node *node) |
1da177e4 | 456 | { |
0ebfff14 BH |
457 | /* IBM machines have interrupt parents of various funky types for things |
458 | * like vdevices, events, etc... The trick we use here is to match | |
459 | * everything here except the legacy 8259 which is compatible "chrp,iic" | |
460 | */ | |
55b61fec | 461 | return !of_device_is_compatible(node, "chrp,iic"); |
0ebfff14 | 462 | } |
1da177e4 | 463 | |
1af9fa89 ME |
464 | static int xics_host_map(struct irq_host *h, unsigned int virq, |
465 | irq_hw_number_t hw) | |
0ebfff14 | 466 | { |
b69e9e93 | 467 | pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 468 | |
967e012e SD |
469 | /* Insert the interrupt mapping into the radix tree for fast lookup */ |
470 | irq_radix_revmap_insert(xics_host, virq, hw); | |
471 | ||
6cff46f4 | 472 | irq_to_desc(virq)->status |= IRQ_LEVEL; |
1af9fa89 | 473 | set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); |
0ebfff14 BH |
474 | return 0; |
475 | } | |
476 | ||
477 | static int xics_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 478 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
479 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
480 | ||
481 | { | |
482 | /* Current xics implementation translates everything | |
483 | * to level. It is not technically right for MSIs but this | |
484 | * is irrelevant at this point. We might get smarter in the future | |
6c80a21c | 485 | */ |
0ebfff14 BH |
486 | *out_hwirq = intspec[0]; |
487 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
1af9fa89 | 492 | static struct irq_host_ops xics_host_ops = { |
0ebfff14 | 493 | .match = xics_host_match, |
1af9fa89 | 494 | .map = xics_host_map, |
0ebfff14 BH |
495 | .xlate = xics_host_xlate, |
496 | }; | |
497 | ||
498 | static void __init xics_init_host(void) | |
499 | { | |
0ebfff14 | 500 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
1af9fa89 | 501 | xics_irq_chip = &xics_pic_lpar; |
0ebfff14 | 502 | else |
1af9fa89 ME |
503 | xics_irq_chip = &xics_pic_direct; |
504 | ||
505 | xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops, | |
0ebfff14 BH |
506 | XICS_IRQ_SPURIOUS); |
507 | BUG_ON(xics_host == NULL); | |
508 | irq_set_default_host(xics_host); | |
6c80a21c | 509 | } |
1da177e4 | 510 | |
0641cc91 MM |
511 | |
512 | /* Inter-processor interrupt support */ | |
513 | ||
514 | #ifdef CONFIG_SMP | |
515 | /* | |
516 | * XICS only has a single IPI, so encode the messages per CPU | |
517 | */ | |
fda9d861 | 518 | static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message); |
0641cc91 MM |
519 | |
520 | static inline void smp_xics_do_message(int cpu, int msg) | |
521 | { | |
fda9d861 AB |
522 | unsigned long *tgt = &per_cpu(xics_ipi_message, cpu); |
523 | ||
524 | set_bit(msg, tgt); | |
0641cc91 MM |
525 | mb(); |
526 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
527 | lpar_qirr_info(cpu, IPI_PRIORITY); | |
528 | else | |
529 | direct_qirr_info(cpu, IPI_PRIORITY); | |
530 | } | |
531 | ||
532 | void smp_xics_message_pass(int target, int msg) | |
533 | { | |
534 | unsigned int i; | |
535 | ||
536 | if (target < NR_CPUS) { | |
537 | smp_xics_do_message(target, msg); | |
538 | } else { | |
539 | for_each_online_cpu(i) { | |
540 | if (target == MSG_ALL_BUT_SELF | |
541 | && i == smp_processor_id()) | |
542 | continue; | |
543 | smp_xics_do_message(i, msg); | |
544 | } | |
545 | } | |
546 | } | |
547 | ||
548 | static irqreturn_t xics_ipi_dispatch(int cpu) | |
549 | { | |
fda9d861 AB |
550 | unsigned long *tgt = &per_cpu(xics_ipi_message, cpu); |
551 | ||
0641cc91 MM |
552 | WARN_ON(cpu_is_offline(cpu)); |
553 | ||
199f45c4 | 554 | mb(); /* order mmio clearing qirr */ |
fda9d861 AB |
555 | while (*tgt) { |
556 | if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) { | |
0641cc91 MM |
557 | smp_message_recv(PPC_MSG_CALL_FUNCTION); |
558 | } | |
fda9d861 | 559 | if (test_and_clear_bit(PPC_MSG_RESCHEDULE, tgt)) { |
0641cc91 MM |
560 | smp_message_recv(PPC_MSG_RESCHEDULE); |
561 | } | |
fda9d861 | 562 | if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, tgt)) { |
0641cc91 MM |
563 | smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE); |
564 | } | |
565 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) | |
fda9d861 | 566 | if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, tgt)) { |
0641cc91 MM |
567 | smp_message_recv(PPC_MSG_DEBUGGER_BREAK); |
568 | } | |
569 | #endif | |
570 | } | |
571 | return IRQ_HANDLED; | |
572 | } | |
573 | ||
574 | static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id) | |
575 | { | |
576 | int cpu = smp_processor_id(); | |
577 | ||
578 | direct_qirr_info(cpu, 0xff); | |
579 | ||
580 | return xics_ipi_dispatch(cpu); | |
581 | } | |
582 | ||
583 | static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id) | |
584 | { | |
585 | int cpu = smp_processor_id(); | |
586 | ||
587 | lpar_qirr_info(cpu, 0xff); | |
588 | ||
589 | return xics_ipi_dispatch(cpu); | |
590 | } | |
591 | ||
592 | static void xics_request_ipi(void) | |
593 | { | |
594 | unsigned int ipi; | |
595 | int rc; | |
596 | ||
597 | ipi = irq_create_mapping(xics_host, XICS_IPI); | |
598 | BUG_ON(ipi == NO_IRQ); | |
599 | ||
600 | /* | |
601 | * IPIs are marked IRQF_DISABLED as they must run with irqs | |
602 | * disabled | |
603 | */ | |
604 | set_irq_handler(ipi, handle_percpu_irq); | |
605 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
d879f384 MM |
606 | rc = request_irq(ipi, xics_ipi_action_lpar, |
607 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | |
0641cc91 | 608 | else |
d879f384 MM |
609 | rc = request_irq(ipi, xics_ipi_action_direct, |
610 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | |
0641cc91 MM |
611 | BUG_ON(rc); |
612 | } | |
613 | ||
614 | int __init smp_xics_probe(void) | |
615 | { | |
616 | xics_request_ipi(); | |
617 | ||
64fe220c | 618 | return cpumask_weight(cpu_possible_mask); |
0641cc91 MM |
619 | } |
620 | ||
621 | #endif /* CONFIG_SMP */ | |
622 | ||
623 | ||
624 | /* Initialization */ | |
625 | ||
626 | static void xics_update_irq_servers(void) | |
627 | { | |
628 | int i, j; | |
629 | struct device_node *np; | |
630 | u32 ilen; | |
1ef8014d | 631 | const u32 *ireg; |
0641cc91 MM |
632 | u32 hcpuid; |
633 | ||
634 | /* Find the server numbers for the boot cpu. */ | |
635 | np = of_get_cpu_node(boot_cpuid, NULL); | |
636 | BUG_ON(!np); | |
637 | ||
638 | ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); | |
639 | if (!ireg) { | |
640 | of_node_put(np); | |
641 | return; | |
642 | } | |
643 | ||
644 | i = ilen / sizeof(int); | |
645 | hcpuid = get_hard_smp_processor_id(boot_cpuid); | |
646 | ||
647 | /* Global interrupt distribution server is specified in the last | |
648 | * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last | |
649 | * entry fom this property for current boot cpu id and use it as | |
650 | * default distribution server | |
651 | */ | |
652 | for (j = 0; j < i; j += 2) { | |
653 | if (ireg[j] == hcpuid) { | |
654 | default_server = hcpuid; | |
655 | default_distrib_server = ireg[j+1]; | |
0641cc91 MM |
656 | } |
657 | } | |
658 | ||
659 | of_node_put(np); | |
660 | } | |
661 | ||
0ebfff14 BH |
662 | static void __init xics_map_one_cpu(int hw_id, unsigned long addr, |
663 | unsigned long size) | |
1da177e4 LT |
664 | { |
665 | int i; | |
1da177e4 | 666 | |
0ebfff14 BH |
667 | /* This may look gross but it's good enough for now, we don't quite |
668 | * have a hard -> linux processor id matching. | |
669 | */ | |
670 | for_each_possible_cpu(i) { | |
671 | if (!cpu_present(i)) | |
672 | continue; | |
673 | if (hw_id == get_hard_smp_processor_id(i)) { | |
674 | xics_per_cpu[i] = ioremap(addr, size); | |
675 | return; | |
676 | } | |
677 | } | |
0ebfff14 | 678 | } |
1da177e4 | 679 | |
0ebfff14 BH |
680 | static void __init xics_init_one_node(struct device_node *np, |
681 | unsigned int *indx) | |
682 | { | |
683 | unsigned int ilen; | |
954a46e2 | 684 | const u32 *ireg; |
1da177e4 | 685 | |
0ebfff14 BH |
686 | /* This code does the theorically broken assumption that the interrupt |
687 | * server numbers are the same as the hard CPU numbers. | |
688 | * This happens to be the case so far but we are playing with fire... | |
689 | * should be fixed one of these days. -BenH. | |
690 | */ | |
e2eb6392 | 691 | ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL); |
1da177e4 | 692 | |
0ebfff14 BH |
693 | /* Do that ever happen ? we'll know soon enough... but even good'old |
694 | * f80 does have that property .. | |
695 | */ | |
696 | WARN_ON(ireg == NULL); | |
1da177e4 LT |
697 | if (ireg) { |
698 | /* | |
699 | * set node starting index for this node | |
700 | */ | |
0ebfff14 | 701 | *indx = *ireg; |
1da177e4 | 702 | } |
e2eb6392 | 703 | ireg = of_get_property(np, "reg", &ilen); |
1da177e4 LT |
704 | if (!ireg) |
705 | panic("xics_init_IRQ: can't find interrupt reg property"); | |
007e8f51 | 706 | |
0ebfff14 BH |
707 | while (ilen >= (4 * sizeof(u32))) { |
708 | unsigned long addr, size; | |
709 | ||
710 | /* XXX Use proper OF parsing code here !!! */ | |
711 | addr = (unsigned long)*ireg++ << 32; | |
712 | ilen -= sizeof(u32); | |
713 | addr |= *ireg++; | |
714 | ilen -= sizeof(u32); | |
715 | size = (unsigned long)*ireg++ << 32; | |
716 | ilen -= sizeof(u32); | |
717 | size |= *ireg++; | |
718 | ilen -= sizeof(u32); | |
719 | xics_map_one_cpu(*indx, addr, size); | |
720 | (*indx)++; | |
721 | } | |
722 | } | |
723 | ||
0ebfff14 BH |
724 | void __init xics_init_IRQ(void) |
725 | { | |
0ebfff14 | 726 | struct device_node *np; |
de0723dc | 727 | u32 indx = 0; |
0ebfff14 | 728 | int found = 0; |
1ef8014d | 729 | const u32 *isize; |
0ebfff14 BH |
730 | |
731 | ppc64_boot_msg(0x20, "XICS Init"); | |
732 | ||
733 | ibm_get_xive = rtas_token("ibm,get-xive"); | |
734 | ibm_set_xive = rtas_token("ibm,set-xive"); | |
735 | ibm_int_on = rtas_token("ibm,int-on"); | |
736 | ibm_int_off = rtas_token("ibm,int-off"); | |
737 | ||
738 | for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") { | |
739 | found = 1; | |
a244a957 MM |
740 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
741 | of_node_put(np); | |
0ebfff14 | 742 | break; |
a244a957 | 743 | } |
0ebfff14 BH |
744 | xics_init_one_node(np, &indx); |
745 | } | |
746 | if (found == 0) | |
747 | return; | |
748 | ||
1ef8014d SD |
749 | /* get the bit size of server numbers */ |
750 | found = 0; | |
751 | ||
752 | for_each_compatible_node(np, NULL, "ibm,ppc-xics") { | |
753 | isize = of_get_property(np, "ibm,interrupt-server#-size", NULL); | |
754 | ||
755 | if (!isize) | |
756 | continue; | |
757 | ||
758 | if (!found) { | |
759 | interrupt_server_size = *isize; | |
760 | found = 1; | |
761 | } else if (*isize != interrupt_server_size) { | |
762 | printk(KERN_WARNING "XICS: " | |
763 | "mismatched ibm,interrupt-server#-size\n"); | |
764 | interrupt_server_size = max(*isize, | |
765 | interrupt_server_size); | |
766 | } | |
767 | } | |
768 | ||
de0723dc | 769 | xics_update_irq_servers(); |
302905a3 | 770 | xics_init_host(); |
1da177e4 | 771 | |
0ebfff14 BH |
772 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
773 | ppc_md.get_irq = xics_get_irq_lpar; | |
774 | else | |
b9e5b4e6 | 775 | ppc_md.get_irq = xics_get_irq_direct; |
1da177e4 | 776 | |
6c80a21c | 777 | xics_setup_cpu(); |
1da177e4 | 778 | |
0ebfff14 | 779 | ppc64_boot_msg(0x21, "XICS Done"); |
1da177e4 | 780 | } |
b9e5b4e6 | 781 | |
0641cc91 | 782 | /* Cpu startup, shutdown, and hotplug */ |
1da177e4 | 783 | |
0641cc91 | 784 | static void xics_set_cpu_priority(unsigned char cppr) |
1da177e4 | 785 | { |
49bd3647 MN |
786 | struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); |
787 | ||
36350e00 MN |
788 | /* |
789 | * we only really want to set the priority when there's | |
790 | * just one cppr value on the stack | |
791 | */ | |
792 | WARN_ON(os_cppr->index != 0); | |
49bd3647 | 793 | |
36350e00 | 794 | os_cppr->stack[0] = cppr; |
49bd3647 | 795 | |
b9e5b4e6 | 796 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
0641cc91 | 797 | lpar_cppr_info(cppr); |
b9e5b4e6 | 798 | else |
0641cc91 MM |
799 | direct_cppr_info(cppr); |
800 | iosync(); | |
1da177e4 | 801 | } |
d13f7208 | 802 | |
b4963255 MM |
803 | /* Have the calling processor join or leave the specified global queue */ |
804 | static void xics_set_cpu_giq(unsigned int gserver, unsigned int join) | |
805 | { | |
edc72ac4 NL |
806 | int index; |
807 | int status; | |
808 | ||
809 | if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL)) | |
810 | return; | |
811 | ||
812 | index = (1UL << interrupt_server_size) - 1 - gserver; | |
813 | ||
814 | status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join); | |
815 | ||
816 | WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", | |
817 | GLOBAL_INTERRUPT_QUEUE, index, join, status); | |
b4963255 | 818 | } |
0641cc91 MM |
819 | |
820 | void xics_setup_cpu(void) | |
d13f7208 | 821 | { |
49bd3647 | 822 | xics_set_cpu_priority(LOWEST_PRIORITY); |
d13f7208 | 823 | |
b4963255 | 824 | xics_set_cpu_giq(default_distrib_server, 1); |
d13f7208 MM |
825 | } |
826 | ||
f10095c3 | 827 | void xics_teardown_cpu(void) |
fce0d574 | 828 | { |
36350e00 | 829 | struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); |
fce0d574 | 830 | int cpu = smp_processor_id(); |
fce0d574 | 831 | |
36350e00 MN |
832 | /* |
833 | * we have to reset the cppr index to 0 because we're | |
834 | * not going to return from the IPI | |
835 | */ | |
836 | os_cppr->index = 0; | |
d7cf0edb | 837 | xics_set_cpu_priority(0); |
81bbbe92 | 838 | |
b4963255 | 839 | /* Clear any pending IPI request */ |
6e99e458 BH |
840 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
841 | lpar_qirr_info(cpu, 0xff); | |
842 | else | |
843 | direct_qirr_info(cpu, 0xff); | |
c3e8506c NF |
844 | } |
845 | ||
846 | void xics_kexec_teardown_cpu(int secondary) | |
847 | { | |
c3e8506c | 848 | xics_teardown_cpu(); |
6e99e458 | 849 | |
81bbbe92 | 850 | /* |
1a57c926 MM |
851 | * we take the ipi irq but and never return so we |
852 | * need to EOI the IPI, but want to leave our priority 0 | |
81bbbe92 | 853 | * |
1a57c926 | 854 | * should we check all the other interrupts too? |
81bbbe92 HM |
855 | * should we be flagging idle loop instead? |
856 | * or creating some task to be scheduled? | |
857 | */ | |
0ebfff14 | 858 | |
1a57c926 MM |
859 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
860 | lpar_xirr_info_set((0x00 << 24) | XICS_IPI); | |
861 | else | |
862 | direct_xirr_info_set((0x00 << 24) | XICS_IPI); | |
81bbbe92 | 863 | |
fce0d574 | 864 | /* |
6d22d85a PM |
865 | * Some machines need to have at least one cpu in the GIQ, |
866 | * so leave the master cpu in the group. | |
fce0d574 | 867 | */ |
81bbbe92 | 868 | if (secondary) |
b4963255 | 869 | xics_set_cpu_giq(default_distrib_server, 0); |
fce0d574 S |
870 | } |
871 | ||
1da177e4 LT |
872 | #ifdef CONFIG_HOTPLUG_CPU |
873 | ||
874 | /* Interrupts are disabled. */ | |
875 | void xics_migrate_irqs_away(void) | |
876 | { | |
d7cf0edb MM |
877 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); |
878 | unsigned int irq, virq; | |
1da177e4 | 879 | |
302905a3 MM |
880 | /* If we used to be the default server, move to the new "boot_cpuid" */ |
881 | if (hw_cpu == default_server) | |
882 | xics_update_irq_servers(); | |
883 | ||
1da177e4 | 884 | /* Reject any interrupt that was queued to us... */ |
d7cf0edb | 885 | xics_set_cpu_priority(0); |
1da177e4 | 886 | |
b4963255 MM |
887 | /* Remove ourselves from the global interrupt queue */ |
888 | xics_set_cpu_giq(default_distrib_server, 0); | |
1da177e4 LT |
889 | |
890 | /* Allow IPIs again... */ | |
d7cf0edb | 891 | xics_set_cpu_priority(DEFAULT_PRIORITY); |
1da177e4 LT |
892 | |
893 | for_each_irq(virq) { | |
b9e5b4e6 | 894 | struct irq_desc *desc; |
1da177e4 | 895 | int xics_status[2]; |
b4963255 | 896 | int status; |
1da177e4 LT |
897 | unsigned long flags; |
898 | ||
899 | /* We cant set affinity on ISA interrupts */ | |
0ebfff14 | 900 | if (virq < NUM_ISA_INTERRUPTS) |
1da177e4 | 901 | continue; |
0ebfff14 BH |
902 | if (irq_map[virq].host != xics_host) |
903 | continue; | |
904 | irq = (unsigned int)irq_map[virq].hwirq; | |
1da177e4 | 905 | /* We need to get IPIs still. */ |
0ebfff14 | 906 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
1da177e4 | 907 | continue; |
6cff46f4 | 908 | desc = irq_to_desc(virq); |
1da177e4 LT |
909 | |
910 | /* We only need to migrate enabled IRQS */ | |
d1bef4ed | 911 | if (desc == NULL || desc->chip == NULL |
1da177e4 | 912 | || desc->action == NULL |
d1bef4ed | 913 | || desc->chip->set_affinity == NULL) |
1da177e4 LT |
914 | continue; |
915 | ||
239007b8 | 916 | raw_spin_lock_irqsave(&desc->lock, flags); |
1da177e4 LT |
917 | |
918 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
919 | if (status) { | |
2172fe87 MM |
920 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
921 | __func__, irq, status); | |
1da177e4 LT |
922 | goto unlock; |
923 | } | |
924 | ||
925 | /* | |
926 | * We only support delivery to all cpus or to one cpu. | |
927 | * The irq has to be migrated only in the single cpu | |
928 | * case. | |
929 | */ | |
d7cf0edb | 930 | if (xics_status[0] != hw_cpu) |
1da177e4 LT |
931 | goto unlock; |
932 | ||
26370322 | 933 | printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n", |
1da177e4 LT |
934 | virq, cpu); |
935 | ||
936 | /* Reset affinity to all cpus */ | |
6cff46f4 | 937 | cpumask_setall(irq_to_desc(virq)->affinity); |
0de26520 | 938 | desc->chip->set_affinity(virq, cpu_all_mask); |
1da177e4 | 939 | unlock: |
239007b8 | 940 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
941 | } |
942 | } | |
943 | #endif |