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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2001 Allan Trautman, IBM Corporation |
1dee2026 | 3 | * Copyright (C) 2005,2007 Stephen Rothwell, IBM Corp |
1da177e4 LT |
4 | * |
5 | * iSeries specific routines for PCI. | |
d387899f | 6 | * |
1da177e4 LT |
7 | * Based on code from pci.c and iSeries_pci.c 32bit |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
d387899f | 13 | * |
1da177e4 LT |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
d387899f | 18 | * |
1da177e4 LT |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
50c9bc2f BH |
23 | |
24 | #undef DEBUG | |
25 | ||
1da177e4 | 26 | #include <linux/kernel.h> |
d387899f | 27 | #include <linux/list.h> |
1da177e4 LT |
28 | #include <linux/string.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/module.h> | |
1da177e4 | 31 | #include <linux/pci.h> |
885b86e4 | 32 | #include <linux/of.h> |
1da177e4 | 33 | |
1dee2026 | 34 | #include <asm/types.h> |
1da177e4 LT |
35 | #include <asm/io.h> |
36 | #include <asm/irq.h> | |
37 | #include <asm/prom.h> | |
38 | #include <asm/machdep.h> | |
39 | #include <asm/pci-bridge.h> | |
1da177e4 | 40 | #include <asm/iommu.h> |
426c1a11 | 41 | #include <asm/abs_addr.h> |
caf81329 | 42 | #include <asm/firmware.h> |
1da177e4 | 43 | |
1dee2026 | 44 | #include <asm/iseries/hv_types.h> |
8021b8a7 | 45 | #include <asm/iseries/hv_call_xm.h> |
bbc8b628 | 46 | #include <asm/iseries/mf.h> |
c7f0e8cb | 47 | #include <asm/iseries/iommu.h> |
1da177e4 | 48 | |
d387899f | 49 | #include <asm/ppc-pci.h> |
1da177e4 | 50 | |
b08567cb | 51 | #include "irq.h" |
426c1a11 | 52 | #include "pci.h" |
c6d2ea92 | 53 | #include "call_pci.h" |
b08567cb | 54 | |
b9b1812c SR |
55 | #define PCI_RETRY_MAX 3 |
56 | static int limit_pci_retries = 1; /* Set Retry Error on. */ | |
1da177e4 | 57 | |
1da177e4 LT |
58 | /* |
59 | * Table defines | |
60 | * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. | |
61 | */ | |
62 | #define IOMM_TABLE_MAX_ENTRIES 1024 | |
63 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | |
64 | #define BASE_IO_MEMORY 0xE000000000000000UL | |
50c9bc2f | 65 | #define END_IO_MEMORY 0xEFFFFFFFFFFFFFFFUL |
1da177e4 | 66 | |
b58b7f98 | 67 | static unsigned long max_io_memory = BASE_IO_MEMORY; |
1da177e4 LT |
68 | static long current_iomm_table_entry; |
69 | ||
70 | /* | |
71 | * Lookup Tables. | |
72 | */ | |
b58b7f98 | 73 | static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES]; |
885b86e4 | 74 | static u64 ds_addr_table[IOMM_TABLE_MAX_ENTRIES]; |
1da177e4 | 75 | |
1da177e4 LT |
76 | static DEFINE_SPINLOCK(iomm_table_lock); |
77 | ||
2cd1008c SR |
78 | /* |
79 | * Generate a Direct Select Address for the Hypervisor | |
80 | */ | |
81 | static inline u64 iseries_ds_addr(struct device_node *node) | |
82 | { | |
83 | struct pci_dn *pdn = PCI_DN(node); | |
885b86e4 | 84 | const u32 *sbp = of_get_property(node, "linux,subbus", NULL); |
2cd1008c | 85 | |
885b86e4 | 86 | return ((u64)pdn->busno << 48) + ((u64)(sbp ? *sbp : 0) << 40) |
2cd1008c SR |
87 | + ((u64)0x10 << 32); |
88 | } | |
89 | ||
1dee2026 SR |
90 | /* |
91 | * Size of Bus VPD data | |
92 | */ | |
93 | #define BUS_VPDSIZE 1024 | |
94 | ||
95 | /* | |
96 | * Bus Vpd Tags | |
97 | */ | |
98 | #define VPD_END_OF_AREA 0x79 | |
99 | #define VPD_ID_STRING 0x82 | |
100 | #define VPD_VENDOR_AREA 0x84 | |
101 | ||
102 | /* | |
103 | * Mfg Area Tags | |
104 | */ | |
105 | #define VPD_FRU_FRAME_ID 0x4649 /* "FI" */ | |
106 | #define VPD_SLOT_MAP_FORMAT 0x4D46 /* "MF" */ | |
107 | #define VPD_SLOT_MAP 0x534D /* "SM" */ | |
108 | ||
109 | /* | |
110 | * Structures of the areas | |
111 | */ | |
112 | struct mfg_vpd_area { | |
113 | u16 tag; | |
114 | u8 length; | |
115 | u8 data1; | |
116 | u8 data2; | |
117 | }; | |
118 | #define MFG_ENTRY_SIZE 3 | |
119 | ||
120 | struct slot_map { | |
121 | u8 agent; | |
122 | u8 secondary_agent; | |
123 | u8 phb; | |
124 | char card_location[3]; | |
125 | char parms[8]; | |
126 | char reserved[2]; | |
127 | }; | |
128 | #define SLOT_ENTRY_SIZE 16 | |
129 | ||
130 | /* | |
131 | * Parse the Slot Area | |
132 | */ | |
133 | static void __init iseries_parse_slot_area(struct slot_map *map, int len, | |
134 | HvAgentId agent, u8 *phb, char card[4]) | |
135 | { | |
136 | /* | |
137 | * Parse Slot label until we find the one requested | |
138 | */ | |
139 | while (len > 0) { | |
140 | if (map->agent == agent) { | |
141 | /* | |
142 | * If Phb wasn't found, grab the entry first one found. | |
143 | */ | |
144 | if (*phb == 0xff) | |
145 | *phb = map->phb; | |
146 | /* Found it, extract the data. */ | |
147 | if (map->phb == *phb) { | |
148 | memcpy(card, &map->card_location, 3); | |
149 | card[3] = 0; | |
150 | break; | |
151 | } | |
152 | } | |
153 | /* Point to the next Slot */ | |
154 | map = (struct slot_map *)((char *)map + SLOT_ENTRY_SIZE); | |
155 | len -= SLOT_ENTRY_SIZE; | |
156 | } | |
157 | } | |
158 | ||
159 | /* | |
160 | * Parse the Mfg Area | |
161 | */ | |
162 | static void __init iseries_parse_mfg_area(struct mfg_vpd_area *area, int len, | |
163 | HvAgentId agent, u8 *phb, u8 *frame, char card[4]) | |
164 | { | |
165 | u16 slot_map_fmt = 0; | |
166 | ||
167 | /* Parse Mfg Data */ | |
168 | while (len > 0) { | |
169 | int mfg_tag_len = area->length; | |
170 | /* Frame ID (FI 4649020310 ) */ | |
171 | if (area->tag == VPD_FRU_FRAME_ID) | |
172 | *frame = area->data1; | |
173 | /* Slot Map Format (MF 4D46020004 ) */ | |
174 | else if (area->tag == VPD_SLOT_MAP_FORMAT) | |
175 | slot_map_fmt = (area->data1 * 256) | |
176 | + area->data2; | |
177 | /* Slot Map (SM 534D90 */ | |
178 | else if (area->tag == VPD_SLOT_MAP) { | |
179 | struct slot_map *slot_map; | |
180 | ||
181 | if (slot_map_fmt == 0x1004) | |
182 | slot_map = (struct slot_map *)((char *)area | |
183 | + MFG_ENTRY_SIZE + 1); | |
184 | else | |
185 | slot_map = (struct slot_map *)((char *)area | |
186 | + MFG_ENTRY_SIZE); | |
187 | iseries_parse_slot_area(slot_map, mfg_tag_len, | |
188 | agent, phb, card); | |
189 | } | |
190 | /* | |
191 | * Point to the next Mfg Area | |
192 | * Use defined size, sizeof give wrong answer | |
193 | */ | |
194 | area = (struct mfg_vpd_area *)((char *)area + mfg_tag_len | |
195 | + MFG_ENTRY_SIZE); | |
196 | len -= (mfg_tag_len + MFG_ENTRY_SIZE); | |
197 | } | |
198 | } | |
199 | ||
200 | /* | |
201 | * Look for "BUS".. Data is not Null terminated. | |
202 | * PHBID of 0xFF indicates PHB was not found in VPD Data. | |
203 | */ | |
204 | static u8 __init iseries_parse_phbid(u8 *area, int len) | |
205 | { | |
206 | while (len > 0) { | |
207 | if ((*area == 'B') && (*(area + 1) == 'U') | |
208 | && (*(area + 2) == 'S')) { | |
209 | area += 3; | |
210 | while (*area == ' ') | |
211 | area++; | |
212 | return *area & 0x0F; | |
213 | } | |
214 | area++; | |
215 | len--; | |
216 | } | |
217 | return 0xff; | |
218 | } | |
219 | ||
220 | /* | |
221 | * Parse out the VPD Areas | |
222 | */ | |
223 | static void __init iseries_parse_vpd(u8 *data, int data_len, | |
224 | HvAgentId agent, u8 *frame, char card[4]) | |
225 | { | |
226 | u8 phb = 0xff; | |
227 | ||
228 | while (data_len > 0) { | |
229 | int len; | |
230 | u8 tag = *data; | |
231 | ||
232 | if (tag == VPD_END_OF_AREA) | |
233 | break; | |
234 | len = *(data + 1) + (*(data + 2) * 256); | |
235 | data += 3; | |
236 | data_len -= 3; | |
237 | if (tag == VPD_ID_STRING) | |
238 | phb = iseries_parse_phbid(data, len); | |
239 | else if (tag == VPD_VENDOR_AREA) | |
240 | iseries_parse_mfg_area((struct mfg_vpd_area *)data, len, | |
241 | agent, &phb, frame, card); | |
242 | /* Point to next Area. */ | |
243 | data += len; | |
244 | data_len -= len; | |
245 | } | |
246 | } | |
247 | ||
248 | static int __init iseries_get_location_code(u16 bus, HvAgentId agent, | |
249 | u8 *frame, char card[4]) | |
250 | { | |
251 | int status = 0; | |
252 | int bus_vpd_len = 0; | |
253 | u8 *bus_vpd = kmalloc(BUS_VPDSIZE, GFP_KERNEL); | |
254 | ||
255 | if (bus_vpd == NULL) { | |
256 | printk("PCI: Bus VPD Buffer allocation failure.\n"); | |
257 | return 0; | |
258 | } | |
259 | bus_vpd_len = HvCallPci_getBusVpd(bus, iseries_hv_addr(bus_vpd), | |
260 | BUS_VPDSIZE); | |
261 | if (bus_vpd_len == 0) { | |
262 | printk("PCI: Bus VPD Buffer zero length.\n"); | |
263 | goto out_free; | |
264 | } | |
265 | /* printk("PCI: bus_vpd: %p, %d\n",bus_vpd, bus_vpd_len); */ | |
266 | /* Make sure this is what I think it is */ | |
267 | if (*bus_vpd != VPD_ID_STRING) { | |
268 | printk("PCI: Bus VPD Buffer missing starting tag.\n"); | |
269 | goto out_free; | |
270 | } | |
271 | iseries_parse_vpd(bus_vpd, bus_vpd_len, agent, frame, card); | |
272 | status = 1; | |
273 | out_free: | |
274 | kfree(bus_vpd); | |
275 | return status; | |
276 | } | |
277 | ||
278 | /* | |
279 | * Prints the device information. | |
280 | * - Pass in pci_dev* pointer to the device. | |
281 | * - Pass in the device count | |
282 | * | |
283 | * Format: | |
284 | * PCI: Bus 0, Device 26, Vendor 0x12AE Frame 1, Card C10 Ethernet | |
285 | * controller | |
286 | */ | |
50c9bc2f BH |
287 | static void __init iseries_device_information(struct pci_dev *pdev, |
288 | u16 bus, HvSubBusNumber subbus) | |
1dee2026 SR |
289 | { |
290 | u8 frame = 0; | |
291 | char card[4]; | |
292 | HvAgentId agent; | |
293 | ||
294 | agent = ISERIES_PCI_AGENTID(ISERIES_GET_DEVICE_FROM_SUBBUS(subbus), | |
295 | ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus)); | |
296 | ||
297 | if (iseries_get_location_code(bus, agent, &frame, card)) { | |
50c9bc2f BH |
298 | printk(KERN_INFO "PCI: %s, Vendor %04X Frame%3d, " |
299 | "Card %4s 0x%04X\n", pci_name(pdev), pdev->vendor, | |
300 | frame, card, (int)(pdev->class >> 8)); | |
1dee2026 SR |
301 | } |
302 | } | |
303 | ||
1da177e4 LT |
304 | /* |
305 | * iomm_table_allocate_entry | |
306 | * | |
307 | * Adds pci_dev entry in address translation table | |
308 | * | |
309 | * - Allocates the number of entries required in table base on BAR | |
310 | * size. | |
311 | * - Allocates starting at BASE_IO_MEMORY and increases. | |
312 | * - The size is round up to be a multiple of entry size. | |
313 | * - CurrentIndex is incremented to keep track of the last entry. | |
314 | * - Builds the resource entry for allocated BARs. | |
315 | */ | |
1e105904 | 316 | static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) |
1da177e4 LT |
317 | { |
318 | struct resource *bar_res = &dev->resource[bar_num]; | |
319 | long bar_size = pci_resource_len(dev, bar_num); | |
320 | ||
321 | /* | |
322 | * No space to allocate, quick exit, skip Allocation. | |
323 | */ | |
324 | if (bar_size == 0) | |
325 | return; | |
326 | /* | |
327 | * Set Resource values. | |
328 | */ | |
329 | spin_lock(&iomm_table_lock); | |
b58b7f98 | 330 | bar_res->start = BASE_IO_MEMORY + |
1da177e4 | 331 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
332 | bar_res->end = bar_res->start + bar_size - 1; |
333 | /* | |
334 | * Allocate the number of table entries needed for BAR. | |
335 | */ | |
336 | while (bar_size > 0 ) { | |
337 | iomm_table[current_iomm_table_entry] = dev->sysdata; | |
885b86e4 SR |
338 | ds_addr_table[current_iomm_table_entry] = |
339 | iseries_ds_addr(dev->sysdata) | (bar_num << 24); | |
1da177e4 LT |
340 | bar_size -= IOMM_TABLE_ENTRY_SIZE; |
341 | ++current_iomm_table_entry; | |
342 | } | |
343 | max_io_memory = BASE_IO_MEMORY + | |
b58b7f98 | 344 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
345 | spin_unlock(&iomm_table_lock); |
346 | } | |
347 | ||
348 | /* | |
349 | * allocate_device_bars | |
350 | * | |
351 | * - Allocates ALL pci_dev BAR's and updates the resources with the | |
352 | * BAR value. BARS with zero length will have the resources | |
353 | * The HvCallPci_getBarParms is used to get the size of the BAR | |
354 | * space. It calls iomm_table_allocate_entry to allocate | |
355 | * each entry. | |
356 | * - Loops through The Bar resources(0 - 5) including the ROM | |
357 | * is resource(6). | |
358 | */ | |
1e105904 | 359 | static void __init allocate_device_bars(struct pci_dev *dev) |
1da177e4 | 360 | { |
1da177e4 LT |
361 | int bar_num; |
362 | ||
b58b7f98 | 363 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) |
1da177e4 | 364 | iomm_table_allocate_entry(dev, bar_num); |
1da177e4 LT |
365 | } |
366 | ||
367 | /* | |
368 | * Log error information to system console. | |
369 | * Filter out the device not there errors. | |
370 | * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx | |
371 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | |
372 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | |
373 | */ | |
7a73bd7f SR |
374 | static void pci_log_error(char *error, int bus, int subbus, |
375 | int agent, int hv_res) | |
1da177e4 | 376 | { |
7a73bd7f | 377 | if (hv_res == 0x0302) |
1da177e4 LT |
378 | return; |
379 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | |
7a73bd7f | 380 | error, bus, subbus, agent, hv_res); |
1da177e4 LT |
381 | } |
382 | ||
9103eb7d SR |
383 | /* |
384 | * Look down the chain to find the matching Device Device | |
385 | */ | |
7a73bd7f | 386 | static struct device_node *find_device_node(int bus, int devfn) |
9103eb7d SR |
387 | { |
388 | struct device_node *node; | |
389 | ||
390 | for (node = NULL; (node = of_find_all_nodes(node)); ) { | |
391 | struct pci_dn *pdn = PCI_DN(node); | |
392 | ||
393 | if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn)) | |
394 | return node; | |
395 | } | |
396 | return NULL; | |
397 | } | |
398 | ||
1da177e4 | 399 | /* |
50c9bc2f BH |
400 | * iSeries_pcibios_fixup_resources |
401 | * | |
402 | * Fixes up all resources for devices | |
1da177e4 | 403 | */ |
50c9bc2f | 404 | void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev) |
1da177e4 | 405 | { |
50c9bc2f BH |
406 | const u32 *agent; |
407 | const u32 *sub_bus; | |
408 | unsigned char bus = pdev->bus->number; | |
252e75a5 | 409 | struct device_node *node; |
50c9bc2f BH |
410 | int i; |
411 | ||
412 | node = find_device_node(bus, pdev->devfn); | |
413 | pr_debug("PCI: iSeries %s, pdev %p, node %p\n", | |
414 | pci_name(pdev), pdev, node); | |
415 | if (!node) { | |
416 | printk("PCI: %s disabled, device tree entry not found !\n", | |
417 | pci_name(pdev)); | |
418 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
419 | pdev->resource[i].flags = 0; | |
420 | return; | |
421 | } | |
422 | sub_bus = of_get_property(node, "linux,subbus", NULL); | |
423 | agent = of_get_property(node, "linux,agent-id", NULL); | |
424 | if (agent && sub_bus) { | |
425 | u8 irq = iSeries_allocate_IRQ(bus, 0, *sub_bus); | |
426 | int err; | |
427 | ||
428 | err = HvCallXm_connectBusUnit(bus, *sub_bus, *agent, irq); | |
429 | if (err) | |
430 | pci_log_error("Connect Bus Unit", | |
431 | bus, *sub_bus, *agent, err); | |
432 | else { | |
433 | err = HvCallPci_configStore8(bus, *sub_bus, | |
53761746 | 434 | *agent, PCI_INTERRUPT_LINE, irq); |
50c9bc2f BH |
435 | if (err) |
436 | pci_log_error("PciCfgStore Irq Failed!", | |
53761746 | 437 | bus, *sub_bus, *agent, err); |
50c9bc2f BH |
438 | else |
439 | pdev->irq = irq; | |
3f178632 | 440 | } |
1da177e4 | 441 | } |
50c9bc2f BH |
442 | |
443 | pdev->sysdata = node; | |
50c9bc2f BH |
444 | allocate_device_bars(pdev); |
445 | iseries_device_information(pdev, bus, *sub_bus); | |
446 | iommu_devnode_init_iSeries(pdev, node); | |
447 | } | |
448 | ||
449 | /* | |
450 | * iSeries_pci_final_fixup(void) | |
451 | */ | |
452 | void __init iSeries_pci_final_fixup(void) | |
453 | { | |
454 | /* Fix up at the device node and pci_dev relationship */ | |
455 | mf_display_src(0xC9000100); | |
1da177e4 LT |
456 | iSeries_activate_IRQs(); |
457 | mf_display_src(0xC9000200); | |
458 | } | |
459 | ||
1da177e4 LT |
460 | /* |
461 | * Config space read and write functions. | |
462 | * For now at least, we look for the device node for the bus and devfn | |
463 | * that we are asked to access. It may be possible to translate the devfn | |
464 | * to a subbus and deviceid more directly. | |
465 | */ | |
466 | static u64 hv_cfg_read_func[4] = { | |
467 | HvCallPciConfigLoad8, HvCallPciConfigLoad16, | |
468 | HvCallPciConfigLoad32, HvCallPciConfigLoad32 | |
469 | }; | |
470 | ||
471 | static u64 hv_cfg_write_func[4] = { | |
472 | HvCallPciConfigStore8, HvCallPciConfigStore16, | |
473 | HvCallPciConfigStore32, HvCallPciConfigStore32 | |
474 | }; | |
475 | ||
476 | /* | |
477 | * Read PCI config space | |
478 | */ | |
479 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
480 | int offset, int size, u32 *val) | |
481 | { | |
7a73bd7f | 482 | struct device_node *node = find_device_node(bus->number, devfn); |
1da177e4 LT |
483 | u64 fn; |
484 | struct HvCallPci_LoadReturn ret; | |
485 | ||
486 | if (node == NULL) | |
487 | return PCIBIOS_DEVICE_NOT_FOUND; | |
488 | if (offset > 255) { | |
489 | *val = ~0; | |
490 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
491 | } | |
492 | ||
493 | fn = hv_cfg_read_func[(size - 1) & 3]; | |
20f48ccf | 494 | HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0); |
1da177e4 LT |
495 | |
496 | if (ret.rc != 0) { | |
497 | *val = ~0; | |
498 | return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ | |
499 | } | |
500 | ||
501 | *val = ret.value; | |
502 | return 0; | |
503 | } | |
504 | ||
505 | /* | |
506 | * Write PCI config space | |
507 | */ | |
508 | ||
509 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
510 | int offset, int size, u32 val) | |
511 | { | |
7a73bd7f | 512 | struct device_node *node = find_device_node(bus->number, devfn); |
1da177e4 LT |
513 | u64 fn; |
514 | u64 ret; | |
515 | ||
516 | if (node == NULL) | |
517 | return PCIBIOS_DEVICE_NOT_FOUND; | |
518 | if (offset > 255) | |
519 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
520 | ||
521 | fn = hv_cfg_write_func[(size - 1) & 3]; | |
20f48ccf | 522 | ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0); |
1da177e4 LT |
523 | |
524 | if (ret != 0) | |
525 | return PCIBIOS_DEVICE_NOT_FOUND; | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
530 | static struct pci_ops iSeries_pci_ops = { | |
531 | .read = iSeries_pci_read_config, | |
532 | .write = iSeries_pci_write_config | |
533 | }; | |
534 | ||
535 | /* | |
536 | * Check Return Code | |
537 | * -> On Failure, print and log information. | |
538 | * Increment Retry Count, if exceeds max, panic partition. | |
1da177e4 LT |
539 | * |
540 | * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 | |
541 | * PCI: Device 23.90 ReadL Retry( 1) | |
542 | * PCI: Device 23.90 ReadL Retry Successful(1) | |
543 | */ | |
7a73bd7f | 544 | static int check_return_code(char *type, struct device_node *dn, |
a2ebaf25 | 545 | int *retry, u64 ret) |
1da177e4 LT |
546 | { |
547 | if (ret != 0) { | |
7a73bd7f | 548 | struct pci_dn *pdn = PCI_DN(dn); |
252e75a5 | 549 | |
a2ebaf25 | 550 | (*retry)++; |
1da177e4 | 551 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
7a73bd7f | 552 | type, pdn->busno, pdn->devfn, |
a2ebaf25 | 553 | *retry, (int)ret); |
1da177e4 LT |
554 | /* |
555 | * Bump the retry and check for retry count exceeded. | |
556 | * If, Exceeded, panic the system. | |
557 | */ | |
b9b1812c SR |
558 | if (((*retry) > PCI_RETRY_MAX) && |
559 | (limit_pci_retries > 0)) { | |
1da177e4 | 560 | mf_display_src(0xB6000103); |
a2ebaf25 | 561 | panic_timeout = 0; |
1da177e4 LT |
562 | panic("PCI: Hardware I/O Error, SRC B6000103, " |
563 | "Automatic Reboot Disabled.\n"); | |
564 | } | |
565 | return -1; /* Retry Try */ | |
566 | } | |
a2ebaf25 | 567 | return 0; |
1da177e4 LT |
568 | } |
569 | ||
570 | /* | |
571 | * Translate the I/O Address into a device node, bar, and bar offset. | |
572 | * Note: Make sure the passed variable end up on the stack to avoid | |
573 | * the exposure of being device global. | |
574 | */ | |
252e75a5 | 575 | static inline struct device_node *xlate_iomm_address( |
7a73bd7f | 576 | const volatile void __iomem *addr, |
0d416f2a | 577 | u64 *dsaptr, u64 *bar_offset, const char *func) |
1da177e4 | 578 | { |
7a73bd7f SR |
579 | unsigned long orig_addr; |
580 | unsigned long base_addr; | |
581 | unsigned long ind; | |
582 | struct device_node *dn; | |
1da177e4 | 583 | |
7a73bd7f | 584 | orig_addr = (unsigned long __force)addr; |
0d416f2a SR |
585 | if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) { |
586 | static unsigned long last_jiffies; | |
587 | static int num_printed; | |
588 | ||
589 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
590 | last_jiffies = jiffies; | |
591 | num_printed = 0; | |
592 | } | |
593 | if (num_printed++ < 10) | |
594 | printk(KERN_ERR | |
595 | "iSeries_%s: invalid access at IO address %p\n", | |
596 | func, addr); | |
1da177e4 | 597 | return NULL; |
0d416f2a | 598 | } |
7a73bd7f SR |
599 | base_addr = orig_addr - BASE_IO_MEMORY; |
600 | ind = base_addr / IOMM_TABLE_ENTRY_SIZE; | |
601 | dn = iomm_table[ind]; | |
602 | ||
603 | if (dn != NULL) { | |
885b86e4 | 604 | *dsaptr = ds_addr_table[ind]; |
7a73bd7f | 605 | *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE; |
1da177e4 | 606 | } else |
7a73bd7f SR |
607 | panic("PCI: Invalid PCI IO address detected!\n"); |
608 | return dn; | |
1da177e4 LT |
609 | } |
610 | ||
611 | /* | |
612 | * Read MM I/O Instructions for the iSeries | |
613 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | |
4cb3cee0 | 614 | * else, data is returned in Big Endian format. |
1da177e4 | 615 | */ |
34489388 | 616 | static u8 iseries_readb(const volatile void __iomem *addr) |
1da177e4 | 617 | { |
7a73bd7f | 618 | u64 bar_offset; |
1da177e4 | 619 | u64 dsa; |
a2ebaf25 | 620 | int retry = 0; |
1da177e4 | 621 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 622 | struct device_node *dn = |
0d416f2a | 623 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte"); |
1da177e4 | 624 | |
0d416f2a | 625 | if (dn == NULL) |
1da177e4 | 626 | return 0xff; |
1da177e4 | 627 | do { |
7a73bd7f SR |
628 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0); |
629 | } while (check_return_code("RDB", dn, &retry, ret.rc) != 0); | |
1da177e4 | 630 | |
4cb3cee0 | 631 | return ret.value; |
1da177e4 | 632 | } |
1da177e4 | 633 | |
34489388 | 634 | static u16 iseries_readw_be(const volatile void __iomem *addr) |
1da177e4 | 635 | { |
7a73bd7f | 636 | u64 bar_offset; |
1da177e4 | 637 | u64 dsa; |
a2ebaf25 | 638 | int retry = 0; |
1da177e4 | 639 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 640 | struct device_node *dn = |
0d416f2a | 641 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_word"); |
1da177e4 | 642 | |
0d416f2a | 643 | if (dn == NULL) |
1da177e4 | 644 | return 0xffff; |
1da177e4 | 645 | do { |
1da177e4 | 646 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, |
7a73bd7f SR |
647 | bar_offset, 0); |
648 | } while (check_return_code("RDW", dn, &retry, ret.rc) != 0); | |
1da177e4 | 649 | |
4cb3cee0 | 650 | return ret.value; |
1da177e4 | 651 | } |
1da177e4 | 652 | |
34489388 | 653 | static u32 iseries_readl_be(const volatile void __iomem *addr) |
1da177e4 | 654 | { |
7a73bd7f | 655 | u64 bar_offset; |
1da177e4 | 656 | u64 dsa; |
a2ebaf25 | 657 | int retry = 0; |
1da177e4 | 658 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 659 | struct device_node *dn = |
0d416f2a | 660 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_long"); |
1da177e4 | 661 | |
0d416f2a | 662 | if (dn == NULL) |
1da177e4 | 663 | return 0xffffffff; |
1da177e4 | 664 | do { |
1da177e4 | 665 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, |
7a73bd7f SR |
666 | bar_offset, 0); |
667 | } while (check_return_code("RDL", dn, &retry, ret.rc) != 0); | |
1da177e4 | 668 | |
4cb3cee0 | 669 | return ret.value; |
1da177e4 | 670 | } |
1da177e4 LT |
671 | |
672 | /* | |
673 | * Write MM I/O Instructions for the iSeries | |
674 | * | |
1da177e4 | 675 | */ |
34489388 | 676 | static void iseries_writeb(u8 data, volatile void __iomem *addr) |
1da177e4 | 677 | { |
7a73bd7f | 678 | u64 bar_offset; |
1da177e4 | 679 | u64 dsa; |
a2ebaf25 | 680 | int retry = 0; |
1da177e4 | 681 | u64 rc; |
7a73bd7f | 682 | struct device_node *dn = |
0d416f2a | 683 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte"); |
1da177e4 | 684 | |
0d416f2a | 685 | if (dn == NULL) |
1da177e4 | 686 | return; |
1da177e4 | 687 | do { |
7a73bd7f SR |
688 | rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0); |
689 | } while (check_return_code("WWB", dn, &retry, rc) != 0); | |
1da177e4 | 690 | } |
1da177e4 | 691 | |
34489388 | 692 | static void iseries_writew_be(u16 data, volatile void __iomem *addr) |
1da177e4 | 693 | { |
7a73bd7f | 694 | u64 bar_offset; |
1da177e4 | 695 | u64 dsa; |
a2ebaf25 | 696 | int retry = 0; |
1da177e4 | 697 | u64 rc; |
7a73bd7f | 698 | struct device_node *dn = |
0d416f2a | 699 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_word"); |
1da177e4 | 700 | |
0d416f2a | 701 | if (dn == NULL) |
1da177e4 | 702 | return; |
1da177e4 | 703 | do { |
7a73bd7f SR |
704 | rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0); |
705 | } while (check_return_code("WWW", dn, &retry, rc) != 0); | |
1da177e4 | 706 | } |
1da177e4 | 707 | |
34489388 | 708 | static void iseries_writel_be(u32 data, volatile void __iomem *addr) |
1da177e4 | 709 | { |
7a73bd7f | 710 | u64 bar_offset; |
1da177e4 | 711 | u64 dsa; |
a2ebaf25 | 712 | int retry = 0; |
1da177e4 | 713 | u64 rc; |
7a73bd7f | 714 | struct device_node *dn = |
0d416f2a | 715 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_long"); |
1da177e4 | 716 | |
0d416f2a | 717 | if (dn == NULL) |
1da177e4 | 718 | return; |
1da177e4 | 719 | do { |
7a73bd7f SR |
720 | rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0); |
721 | } while (check_return_code("WWL", dn, &retry, rc) != 0); | |
1da177e4 | 722 | } |
caf81329 | 723 | |
4cb3cee0 | 724 | static u16 iseries_readw(const volatile void __iomem *addr) |
caf81329 | 725 | { |
34489388 | 726 | return le16_to_cpu(iseries_readw_be(addr)); |
caf81329 | 727 | } |
caf81329 | 728 | |
4cb3cee0 | 729 | static u32 iseries_readl(const volatile void __iomem *addr) |
caf81329 | 730 | { |
34489388 | 731 | return le32_to_cpu(iseries_readl_be(addr)); |
caf81329 | 732 | } |
caf81329 | 733 | |
4cb3cee0 | 734 | static void iseries_writew(u16 data, volatile void __iomem *addr) |
caf81329 | 735 | { |
34489388 | 736 | iseries_writew_be(cpu_to_le16(data), addr); |
caf81329 | 737 | } |
caf81329 | 738 | |
4cb3cee0 | 739 | static void iseries_writel(u32 data, volatile void __iomem *addr) |
caf81329 | 740 | { |
34489388 | 741 | iseries_writel(cpu_to_le32(data), addr); |
caf81329 | 742 | } |
caf81329 | 743 | |
4cb3cee0 BH |
744 | static void iseries_readsb(const volatile void __iomem *addr, void *buf, |
745 | unsigned long count) | |
caf81329 | 746 | { |
4cb3cee0 BH |
747 | u8 *dst = buf; |
748 | while(count-- > 0) | |
34489388 | 749 | *(dst++) = iseries_readb(addr); |
caf81329 | 750 | } |
caf81329 | 751 | |
4cb3cee0 BH |
752 | static void iseries_readsw(const volatile void __iomem *addr, void *buf, |
753 | unsigned long count) | |
caf81329 | 754 | { |
4cb3cee0 BH |
755 | u16 *dst = buf; |
756 | while(count-- > 0) | |
34489388 | 757 | *(dst++) = iseries_readw_be(addr); |
caf81329 | 758 | } |
caf81329 | 759 | |
4cb3cee0 BH |
760 | static void iseries_readsl(const volatile void __iomem *addr, void *buf, |
761 | unsigned long count) | |
caf81329 | 762 | { |
4cb3cee0 BH |
763 | u32 *dst = buf; |
764 | while(count-- > 0) | |
34489388 | 765 | *(dst++) = iseries_readl_be(addr); |
caf81329 | 766 | } |
caf81329 | 767 | |
4cb3cee0 BH |
768 | static void iseries_writesb(volatile void __iomem *addr, const void *buf, |
769 | unsigned long count) | |
caf81329 | 770 | { |
4cb3cee0 BH |
771 | const u8 *src = buf; |
772 | while(count-- > 0) | |
34489388 | 773 | iseries_writeb(*(src++), addr); |
caf81329 | 774 | } |
caf81329 | 775 | |
4cb3cee0 BH |
776 | static void iseries_writesw(volatile void __iomem *addr, const void *buf, |
777 | unsigned long count) | |
caf81329 | 778 | { |
4cb3cee0 BH |
779 | const u16 *src = buf; |
780 | while(count-- > 0) | |
34489388 | 781 | iseries_writew_be(*(src++), addr); |
caf81329 | 782 | } |
caf81329 | 783 | |
4cb3cee0 BH |
784 | static void iseries_writesl(volatile void __iomem *addr, const void *buf, |
785 | unsigned long count) | |
caf81329 | 786 | { |
4cb3cee0 BH |
787 | const u32 *src = buf; |
788 | while(count-- > 0) | |
34489388 | 789 | iseries_writel_be(*(src++), addr); |
caf81329 | 790 | } |
caf81329 | 791 | |
4cb3cee0 BH |
792 | static void iseries_memset_io(volatile void __iomem *addr, int c, |
793 | unsigned long n) | |
caf81329 | 794 | { |
4cb3cee0 | 795 | volatile char __iomem *d = addr; |
caf81329 | 796 | |
4cb3cee0 | 797 | while (n-- > 0) |
34489388 | 798 | iseries_writeb(c, d++); |
caf81329 | 799 | } |
caf81329 | 800 | |
4cb3cee0 BH |
801 | static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, |
802 | unsigned long n) | |
caf81329 | 803 | { |
4cb3cee0 BH |
804 | char *d = dest; |
805 | const volatile char __iomem *s = src; | |
caf81329 | 806 | |
4cb3cee0 | 807 | while (n-- > 0) |
34489388 | 808 | *d++ = iseries_readb(s++); |
caf81329 | 809 | } |
caf81329 | 810 | |
4cb3cee0 BH |
811 | static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, |
812 | unsigned long n) | |
caf81329 | 813 | { |
4cb3cee0 BH |
814 | const char *s = src; |
815 | volatile char __iomem *d = dest; | |
caf81329 | 816 | |
4cb3cee0 | 817 | while (n-- > 0) |
34489388 | 818 | iseries_writeb(*s++, d++); |
caf81329 | 819 | } |
caf81329 | 820 | |
4cb3cee0 BH |
821 | /* We only set MMIO ops. The default PIO ops will be default |
822 | * to the MMIO ops + pci_io_base which is 0 on iSeries as | |
823 | * expected so both should work. | |
824 | * | |
825 | * Note that we don't implement the readq/writeq versions as | |
826 | * I don't know of an HV call for doing so. Thus, the default | |
827 | * operation will be used instead, which will fault a the value | |
828 | * return by iSeries for MMIO addresses always hits a non mapped | |
829 | * area. This is as good as the BUG() we used to have there. | |
830 | */ | |
831 | static struct ppc_pci_io __initdata iseries_pci_io = { | |
832 | .readb = iseries_readb, | |
833 | .readw = iseries_readw, | |
834 | .readl = iseries_readl, | |
835 | .readw_be = iseries_readw_be, | |
836 | .readl_be = iseries_readl_be, | |
837 | .writeb = iseries_writeb, | |
838 | .writew = iseries_writew, | |
839 | .writel = iseries_writel, | |
840 | .writew_be = iseries_writew_be, | |
841 | .writel_be = iseries_writel_be, | |
842 | .readsb = iseries_readsb, | |
843 | .readsw = iseries_readsw, | |
844 | .readsl = iseries_readsl, | |
845 | .writesb = iseries_writesb, | |
846 | .writesw = iseries_writesw, | |
847 | .writesl = iseries_writesl, | |
848 | .memset_io = iseries_memset_io, | |
849 | .memcpy_fromio = iseries_memcpy_fromio, | |
850 | .memcpy_toio = iseries_memcpy_toio, | |
851 | }; | |
caf81329 | 852 | |
4cb3cee0 BH |
853 | /* |
854 | * iSeries_pcibios_init | |
855 | * | |
856 | * Description: | |
857 | * This function checks for all possible system PCI host bridges that connect | |
858 | * PCI buses. The system hypervisor is queried as to the guest partition | |
859 | * ownership status. A pci_controller is built for any bus which is partially | |
860 | * owned or fully owned by this guest partition. | |
861 | */ | |
862 | void __init iSeries_pcibios_init(void) | |
caf81329 | 863 | { |
4cb3cee0 BH |
864 | struct pci_controller *phb; |
865 | struct device_node *root = of_find_node_by_path("/"); | |
866 | struct device_node *node = NULL; | |
caf81329 | 867 | |
4cb3cee0 BH |
868 | /* Install IO hooks */ |
869 | ppc_pci_io = iseries_pci_io; | |
caf81329 | 870 | |
9ccc4fd2 SR |
871 | pci_probe_only = 1; |
872 | ||
3d5134ee BH |
873 | /* iSeries has no IO space in the common sense, it needs to set |
874 | * the IO base to 0 | |
875 | */ | |
876 | pci_io_base = 0; | |
877 | ||
4cb3cee0 BH |
878 | if (root == NULL) { |
879 | printk(KERN_CRIT "iSeries_pcibios_init: can't find root " | |
880 | "of device tree\n"); | |
881 | return; | |
882 | } | |
883 | while ((node = of_get_next_child(root, node)) != NULL) { | |
884 | HvBusNumber bus; | |
885 | const u32 *busp; | |
caf81329 | 886 | |
4cb3cee0 BH |
887 | if ((node->type == NULL) || (strcmp(node->type, "pci") != 0)) |
888 | continue; | |
caf81329 | 889 | |
e2eb6392 | 890 | busp = of_get_property(node, "bus-range", NULL); |
4cb3cee0 BH |
891 | if (busp == NULL) |
892 | continue; | |
893 | bus = *busp; | |
894 | printk("bus %d appears to exist\n", bus); | |
895 | phb = pcibios_alloc_controller(node); | |
896 | if (phb == NULL) | |
897 | continue; | |
6207e816 SR |
898 | /* All legacy iSeries PHBs are in domain zero */ |
899 | phb->global_number = 0; | |
caf81329 | 900 | |
4cb3cee0 BH |
901 | phb->first_busno = bus; |
902 | phb->last_busno = bus; | |
903 | phb->ops = &iSeries_pci_ops; | |
50c9bc2f BH |
904 | phb->io_base_virt = (void __iomem *)_IO_BASE; |
905 | phb->io_resource.flags = IORESOURCE_IO; | |
906 | phb->io_resource.start = BASE_IO_MEMORY; | |
907 | phb->io_resource.end = END_IO_MEMORY; | |
908 | phb->io_resource.name = "iSeries PCI IO"; | |
909 | phb->mem_resources[0].flags = IORESOURCE_MEM; | |
910 | phb->mem_resources[0].start = BASE_IO_MEMORY; | |
911 | phb->mem_resources[0].end = END_IO_MEMORY; | |
912 | phb->mem_resources[0].name = "Series PCI MEM"; | |
4cb3cee0 | 913 | } |
caf81329 | 914 | |
4cb3cee0 | 915 | of_node_put(root); |
caf81329 | 916 | |
4cb3cee0 | 917 | pci_devs_phb_init(); |
caf81329 | 918 | } |
4cb3cee0 | 919 |