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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Allan Trautman, IBM Corporation |
3 | * | |
4 | * iSeries specific routines for PCI. | |
d387899f | 5 | * |
1da177e4 LT |
6 | * Based on code from pci.c and iSeries_pci.c 32bit |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
d387899f | 12 | * |
1da177e4 LT |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
d387899f | 17 | * |
1da177e4 LT |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/kernel.h> | |
d387899f | 23 | #include <linux/list.h> |
1da177e4 LT |
24 | #include <linux/string.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
1da177e4 LT |
27 | #include <linux/pci.h> |
28 | ||
29 | #include <asm/io.h> | |
30 | #include <asm/irq.h> | |
31 | #include <asm/prom.h> | |
32 | #include <asm/machdep.h> | |
33 | #include <asm/pci-bridge.h> | |
1da177e4 | 34 | #include <asm/iommu.h> |
426c1a11 | 35 | #include <asm/abs_addr.h> |
caf81329 | 36 | #include <asm/firmware.h> |
1da177e4 | 37 | |
8021b8a7 | 38 | #include <asm/iseries/hv_call_xm.h> |
bbc8b628 | 39 | #include <asm/iseries/mf.h> |
c7f0e8cb | 40 | #include <asm/iseries/iommu.h> |
1da177e4 | 41 | |
d387899f | 42 | #include <asm/ppc-pci.h> |
1da177e4 | 43 | |
b08567cb | 44 | #include "irq.h" |
426c1a11 | 45 | #include "pci.h" |
c6d2ea92 | 46 | #include "call_pci.h" |
b08567cb | 47 | |
1da177e4 | 48 | /* |
d387899f | 49 | * Forward declares of prototypes. |
1da177e4 | 50 | */ |
252e75a5 | 51 | static struct device_node *find_Device_Node(int bus, int devfn); |
1da177e4 | 52 | |
d387899f | 53 | static int Pci_Retry_Max = 3; /* Only retry 3 times */ |
1da177e4 LT |
54 | static int Pci_Error_Flag = 1; /* Set Retry Error on. */ |
55 | ||
56 | static struct pci_ops iSeries_pci_ops; | |
57 | ||
58 | /* | |
59 | * Table defines | |
60 | * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. | |
61 | */ | |
62 | #define IOMM_TABLE_MAX_ENTRIES 1024 | |
63 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | |
64 | #define BASE_IO_MEMORY 0xE000000000000000UL | |
65 | ||
b58b7f98 | 66 | static unsigned long max_io_memory = BASE_IO_MEMORY; |
1da177e4 LT |
67 | static long current_iomm_table_entry; |
68 | ||
69 | /* | |
70 | * Lookup Tables. | |
71 | */ | |
b58b7f98 SR |
72 | static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES]; |
73 | static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES]; | |
1da177e4 | 74 | |
b58b7f98 | 75 | static const char pci_io_text[] = "iSeries PCI I/O"; |
1da177e4 LT |
76 | static DEFINE_SPINLOCK(iomm_table_lock); |
77 | ||
1da177e4 LT |
78 | /* |
79 | * iomm_table_allocate_entry | |
80 | * | |
81 | * Adds pci_dev entry in address translation table | |
82 | * | |
83 | * - Allocates the number of entries required in table base on BAR | |
84 | * size. | |
85 | * - Allocates starting at BASE_IO_MEMORY and increases. | |
86 | * - The size is round up to be a multiple of entry size. | |
87 | * - CurrentIndex is incremented to keep track of the last entry. | |
88 | * - Builds the resource entry for allocated BARs. | |
89 | */ | |
1e105904 | 90 | static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) |
1da177e4 LT |
91 | { |
92 | struct resource *bar_res = &dev->resource[bar_num]; | |
93 | long bar_size = pci_resource_len(dev, bar_num); | |
94 | ||
95 | /* | |
96 | * No space to allocate, quick exit, skip Allocation. | |
97 | */ | |
98 | if (bar_size == 0) | |
99 | return; | |
100 | /* | |
101 | * Set Resource values. | |
102 | */ | |
103 | spin_lock(&iomm_table_lock); | |
104 | bar_res->name = pci_io_text; | |
b58b7f98 | 105 | bar_res->start = BASE_IO_MEMORY + |
1da177e4 | 106 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
107 | bar_res->end = bar_res->start + bar_size - 1; |
108 | /* | |
109 | * Allocate the number of table entries needed for BAR. | |
110 | */ | |
111 | while (bar_size > 0 ) { | |
112 | iomm_table[current_iomm_table_entry] = dev->sysdata; | |
113 | iobar_table[current_iomm_table_entry] = bar_num; | |
114 | bar_size -= IOMM_TABLE_ENTRY_SIZE; | |
115 | ++current_iomm_table_entry; | |
116 | } | |
117 | max_io_memory = BASE_IO_MEMORY + | |
b58b7f98 | 118 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
119 | spin_unlock(&iomm_table_lock); |
120 | } | |
121 | ||
122 | /* | |
123 | * allocate_device_bars | |
124 | * | |
125 | * - Allocates ALL pci_dev BAR's and updates the resources with the | |
126 | * BAR value. BARS with zero length will have the resources | |
127 | * The HvCallPci_getBarParms is used to get the size of the BAR | |
128 | * space. It calls iomm_table_allocate_entry to allocate | |
129 | * each entry. | |
130 | * - Loops through The Bar resources(0 - 5) including the ROM | |
131 | * is resource(6). | |
132 | */ | |
1e105904 | 133 | static void __init allocate_device_bars(struct pci_dev *dev) |
1da177e4 | 134 | { |
1da177e4 LT |
135 | int bar_num; |
136 | ||
b58b7f98 | 137 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) |
1da177e4 | 138 | iomm_table_allocate_entry(dev, bar_num); |
1da177e4 LT |
139 | } |
140 | ||
141 | /* | |
142 | * Log error information to system console. | |
143 | * Filter out the device not there errors. | |
144 | * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx | |
145 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | |
146 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | |
147 | */ | |
148 | static void pci_Log_Error(char *Error_Text, int Bus, int SubBus, | |
149 | int AgentId, int HvRc) | |
150 | { | |
151 | if (HvRc == 0x0302) | |
152 | return; | |
153 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | |
154 | Error_Text, Bus, SubBus, AgentId, HvRc); | |
155 | } | |
156 | ||
1da177e4 | 157 | /* |
d387899f | 158 | * iSeries_pci_final_fixup(void) |
1da177e4 LT |
159 | */ |
160 | void __init iSeries_pci_final_fixup(void) | |
161 | { | |
162 | struct pci_dev *pdev = NULL; | |
252e75a5 | 163 | struct device_node *node; |
d387899f | 164 | int DeviceCount = 0; |
1da177e4 | 165 | |
1da177e4 LT |
166 | /* Fix up at the device node and pci_dev relationship */ |
167 | mf_display_src(0xC9000100); | |
168 | ||
169 | printk("pcibios_final_fixup\n"); | |
170 | for_each_pci_dev(pdev) { | |
171 | node = find_Device_Node(pdev->bus->number, pdev->devfn); | |
172 | printk("pci dev %p (%x.%x), node %p\n", pdev, | |
173 | pdev->bus->number, pdev->devfn, node); | |
174 | ||
175 | if (node != NULL) { | |
b0252793 | 176 | struct pci_dn *pdn = PCI_DN(node); |
c4c7cba9 | 177 | const u32 *agent; |
b0252793 | 178 | |
e2eb6392 | 179 | agent = of_get_property(node, "linux,agent-id", NULL); |
b0252793 SR |
180 | if ((pdn != NULL) && (agent != NULL)) { |
181 | u8 irq = iSeries_allocate_IRQ(pdn->busno, 0, | |
182 | pdn->bussubno); | |
183 | int err; | |
184 | ||
185 | err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno, | |
186 | *agent, irq); | |
187 | if (err) | |
188 | pci_Log_Error("Connect Bus Unit", | |
189 | pdn->busno, pdn->bussubno, *agent, err); | |
190 | else { | |
191 | err = HvCallPci_configStore8(pdn->busno, pdn->bussubno, | |
192 | *agent, | |
193 | PCI_INTERRUPT_LINE, | |
194 | irq); | |
195 | if (err) | |
196 | pci_Log_Error("PciCfgStore Irq Failed!", | |
197 | pdn->busno, pdn->bussubno, *agent, err); | |
198 | } | |
199 | if (!err) | |
200 | pdev->irq = irq; | |
201 | } | |
202 | ||
1da177e4 LT |
203 | ++DeviceCount; |
204 | pdev->sysdata = (void *)node; | |
252e75a5 | 205 | PCI_DN(node)->pcidev = pdev; |
1da177e4 | 206 | allocate_device_bars(pdev); |
061c063e | 207 | iSeries_Device_Information(pdev, DeviceCount); |
12d04eef | 208 | iommu_devnode_init_iSeries(pdev, node); |
1da177e4 LT |
209 | } else |
210 | printk("PCI: Device Tree not found for 0x%016lX\n", | |
211 | (unsigned long)pdev); | |
1da177e4 LT |
212 | } |
213 | iSeries_activate_IRQs(); | |
214 | mf_display_src(0xC9000200); | |
215 | } | |
216 | ||
1da177e4 LT |
217 | /* |
218 | * Look down the chain to find the matching Device Device | |
219 | */ | |
252e75a5 | 220 | static struct device_node *find_Device_Node(int bus, int devfn) |
1da177e4 | 221 | { |
96ff6afa SR |
222 | struct device_node *node; |
223 | ||
224 | for (node = NULL; (node = of_find_all_nodes(node)); ) { | |
225 | struct pci_dn *pdn = PCI_DN(node); | |
1da177e4 | 226 | |
96ff6afa SR |
227 | if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn)) |
228 | return node; | |
1da177e4 LT |
229 | } |
230 | return NULL; | |
231 | } | |
232 | ||
233 | #if 0 | |
234 | /* | |
235 | * Returns the device node for the passed pci_dev | |
236 | * Sanity Check Node PciDev to passed pci_dev | |
237 | * If none is found, returns a NULL which the client must handle. | |
238 | */ | |
252e75a5 | 239 | static struct device_node *get_Device_Node(struct pci_dev *pdev) |
1da177e4 | 240 | { |
252e75a5 | 241 | struct device_node *node; |
1da177e4 LT |
242 | |
243 | node = pdev->sysdata; | |
252e75a5 | 244 | if (node == NULL || PCI_DN(node)->pcidev != pdev) |
1da177e4 LT |
245 | node = find_Device_Node(pdev->bus->number, pdev->devfn); |
246 | return node; | |
247 | } | |
248 | #endif | |
249 | ||
250 | /* | |
251 | * Config space read and write functions. | |
252 | * For now at least, we look for the device node for the bus and devfn | |
253 | * that we are asked to access. It may be possible to translate the devfn | |
254 | * to a subbus and deviceid more directly. | |
255 | */ | |
256 | static u64 hv_cfg_read_func[4] = { | |
257 | HvCallPciConfigLoad8, HvCallPciConfigLoad16, | |
258 | HvCallPciConfigLoad32, HvCallPciConfigLoad32 | |
259 | }; | |
260 | ||
261 | static u64 hv_cfg_write_func[4] = { | |
262 | HvCallPciConfigStore8, HvCallPciConfigStore16, | |
263 | HvCallPciConfigStore32, HvCallPciConfigStore32 | |
264 | }; | |
265 | ||
266 | /* | |
267 | * Read PCI config space | |
268 | */ | |
269 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
270 | int offset, int size, u32 *val) | |
271 | { | |
252e75a5 | 272 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
273 | u64 fn; |
274 | struct HvCallPci_LoadReturn ret; | |
275 | ||
276 | if (node == NULL) | |
277 | return PCIBIOS_DEVICE_NOT_FOUND; | |
278 | if (offset > 255) { | |
279 | *val = ~0; | |
280 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
281 | } | |
282 | ||
283 | fn = hv_cfg_read_func[(size - 1) & 3]; | |
20f48ccf | 284 | HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0); |
1da177e4 LT |
285 | |
286 | if (ret.rc != 0) { | |
287 | *val = ~0; | |
288 | return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ | |
289 | } | |
290 | ||
291 | *val = ret.value; | |
292 | return 0; | |
293 | } | |
294 | ||
295 | /* | |
296 | * Write PCI config space | |
297 | */ | |
298 | ||
299 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
300 | int offset, int size, u32 val) | |
301 | { | |
252e75a5 | 302 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
303 | u64 fn; |
304 | u64 ret; | |
305 | ||
306 | if (node == NULL) | |
307 | return PCIBIOS_DEVICE_NOT_FOUND; | |
308 | if (offset > 255) | |
309 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
310 | ||
311 | fn = hv_cfg_write_func[(size - 1) & 3]; | |
20f48ccf | 312 | ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0); |
1da177e4 LT |
313 | |
314 | if (ret != 0) | |
315 | return PCIBIOS_DEVICE_NOT_FOUND; | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static struct pci_ops iSeries_pci_ops = { | |
321 | .read = iSeries_pci_read_config, | |
322 | .write = iSeries_pci_write_config | |
323 | }; | |
324 | ||
325 | /* | |
326 | * Check Return Code | |
327 | * -> On Failure, print and log information. | |
328 | * Increment Retry Count, if exceeds max, panic partition. | |
1da177e4 LT |
329 | * |
330 | * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 | |
331 | * PCI: Device 23.90 ReadL Retry( 1) | |
332 | * PCI: Device 23.90 ReadL Retry Successful(1) | |
333 | */ | |
252e75a5 | 334 | static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, |
a2ebaf25 | 335 | int *retry, u64 ret) |
1da177e4 LT |
336 | { |
337 | if (ret != 0) { | |
252e75a5 SR |
338 | struct pci_dn *pdn = PCI_DN(DevNode); |
339 | ||
a2ebaf25 | 340 | (*retry)++; |
1da177e4 | 341 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
20f48ccf | 342 | TextHdr, pdn->busno, pdn->devfn, |
a2ebaf25 | 343 | *retry, (int)ret); |
1da177e4 LT |
344 | /* |
345 | * Bump the retry and check for retry count exceeded. | |
346 | * If, Exceeded, panic the system. | |
347 | */ | |
a2ebaf25 | 348 | if (((*retry) > Pci_Retry_Max) && |
1da177e4 LT |
349 | (Pci_Error_Flag > 0)) { |
350 | mf_display_src(0xB6000103); | |
a2ebaf25 | 351 | panic_timeout = 0; |
1da177e4 LT |
352 | panic("PCI: Hardware I/O Error, SRC B6000103, " |
353 | "Automatic Reboot Disabled.\n"); | |
354 | } | |
355 | return -1; /* Retry Try */ | |
356 | } | |
a2ebaf25 | 357 | return 0; |
1da177e4 LT |
358 | } |
359 | ||
360 | /* | |
361 | * Translate the I/O Address into a device node, bar, and bar offset. | |
362 | * Note: Make sure the passed variable end up on the stack to avoid | |
363 | * the exposure of being device global. | |
364 | */ | |
252e75a5 | 365 | static inline struct device_node *xlate_iomm_address( |
1da177e4 LT |
366 | const volatile void __iomem *IoAddress, |
367 | u64 *dsaptr, u64 *BarOffsetPtr) | |
368 | { | |
369 | unsigned long OrigIoAddr; | |
370 | unsigned long BaseIoAddr; | |
371 | unsigned long TableIndex; | |
252e75a5 | 372 | struct device_node *DevNode; |
1da177e4 LT |
373 | |
374 | OrigIoAddr = (unsigned long __force)IoAddress; | |
375 | if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory)) | |
376 | return NULL; | |
377 | BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY; | |
378 | TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE; | |
379 | DevNode = iomm_table[TableIndex]; | |
380 | ||
381 | if (DevNode != NULL) { | |
382 | int barnum = iobar_table[TableIndex]; | |
20f48ccf | 383 | *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24); |
1da177e4 LT |
384 | *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE; |
385 | } else | |
386 | panic("PCI: Invalid PCI IoAddress detected!\n"); | |
387 | return DevNode; | |
388 | } | |
389 | ||
390 | /* | |
391 | * Read MM I/O Instructions for the iSeries | |
392 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | |
4cb3cee0 | 393 | * else, data is returned in Big Endian format. |
1da177e4 | 394 | */ |
caf81329 | 395 | static u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) |
1da177e4 LT |
396 | { |
397 | u64 BarOffset; | |
398 | u64 dsa; | |
a2ebaf25 | 399 | int retry = 0; |
1da177e4 | 400 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 401 | struct device_node *DevNode = |
1da177e4 LT |
402 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
403 | ||
404 | if (DevNode == NULL) { | |
405 | static unsigned long last_jiffies; | |
406 | static int num_printed; | |
407 | ||
408 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
409 | last_jiffies = jiffies; | |
410 | num_printed = 0; | |
411 | } | |
412 | if (num_printed++ < 10) | |
4cb3cee0 BH |
413 | printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", |
414 | IoAddress); | |
1da177e4 LT |
415 | return 0xff; |
416 | } | |
417 | do { | |
1da177e4 | 418 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); |
a2ebaf25 | 419 | } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); |
1da177e4 | 420 | |
4cb3cee0 | 421 | return ret.value; |
1da177e4 | 422 | } |
1da177e4 | 423 | |
caf81329 | 424 | static u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) |
1da177e4 LT |
425 | { |
426 | u64 BarOffset; | |
427 | u64 dsa; | |
a2ebaf25 | 428 | int retry = 0; |
1da177e4 | 429 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 430 | struct device_node *DevNode = |
1da177e4 LT |
431 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
432 | ||
433 | if (DevNode == NULL) { | |
434 | static unsigned long last_jiffies; | |
435 | static int num_printed; | |
436 | ||
437 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
438 | last_jiffies = jiffies; | |
439 | num_printed = 0; | |
440 | } | |
441 | if (num_printed++ < 10) | |
4cb3cee0 BH |
442 | printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", |
443 | IoAddress); | |
1da177e4 LT |
444 | return 0xffff; |
445 | } | |
446 | do { | |
1da177e4 LT |
447 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, |
448 | BarOffset, 0); | |
a2ebaf25 | 449 | } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); |
1da177e4 | 450 | |
4cb3cee0 | 451 | return ret.value; |
1da177e4 | 452 | } |
1da177e4 | 453 | |
caf81329 | 454 | static u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) |
1da177e4 LT |
455 | { |
456 | u64 BarOffset; | |
457 | u64 dsa; | |
a2ebaf25 | 458 | int retry = 0; |
1da177e4 | 459 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 460 | struct device_node *DevNode = |
1da177e4 LT |
461 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
462 | ||
463 | if (DevNode == NULL) { | |
464 | static unsigned long last_jiffies; | |
465 | static int num_printed; | |
466 | ||
467 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
468 | last_jiffies = jiffies; | |
469 | num_printed = 0; | |
470 | } | |
471 | if (num_printed++ < 10) | |
4cb3cee0 BH |
472 | printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", |
473 | IoAddress); | |
1da177e4 LT |
474 | return 0xffffffff; |
475 | } | |
476 | do { | |
1da177e4 LT |
477 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, |
478 | BarOffset, 0); | |
a2ebaf25 | 479 | } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); |
1da177e4 | 480 | |
4cb3cee0 | 481 | return ret.value; |
1da177e4 | 482 | } |
1da177e4 LT |
483 | |
484 | /* | |
485 | * Write MM I/O Instructions for the iSeries | |
486 | * | |
1da177e4 | 487 | */ |
caf81329 | 488 | static void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) |
1da177e4 LT |
489 | { |
490 | u64 BarOffset; | |
491 | u64 dsa; | |
a2ebaf25 | 492 | int retry = 0; |
1da177e4 | 493 | u64 rc; |
252e75a5 | 494 | struct device_node *DevNode = |
1da177e4 LT |
495 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
496 | ||
497 | if (DevNode == NULL) { | |
498 | static unsigned long last_jiffies; | |
499 | static int num_printed; | |
500 | ||
501 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
502 | last_jiffies = jiffies; | |
503 | num_printed = 0; | |
504 | } | |
505 | if (num_printed++ < 10) | |
506 | printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress); | |
507 | return; | |
508 | } | |
509 | do { | |
1da177e4 | 510 | rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); |
a2ebaf25 | 511 | } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); |
1da177e4 | 512 | } |
1da177e4 | 513 | |
caf81329 | 514 | static void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) |
1da177e4 LT |
515 | { |
516 | u64 BarOffset; | |
517 | u64 dsa; | |
a2ebaf25 | 518 | int retry = 0; |
1da177e4 | 519 | u64 rc; |
252e75a5 | 520 | struct device_node *DevNode = |
1da177e4 LT |
521 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
522 | ||
523 | if (DevNode == NULL) { | |
524 | static unsigned long last_jiffies; | |
525 | static int num_printed; | |
526 | ||
527 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
528 | last_jiffies = jiffies; | |
529 | num_printed = 0; | |
530 | } | |
531 | if (num_printed++ < 10) | |
4cb3cee0 BH |
532 | printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", |
533 | IoAddress); | |
1da177e4 LT |
534 | return; |
535 | } | |
536 | do { | |
4cb3cee0 | 537 | rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, data, 0); |
a2ebaf25 | 538 | } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); |
1da177e4 | 539 | } |
1da177e4 | 540 | |
caf81329 | 541 | static void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) |
1da177e4 LT |
542 | { |
543 | u64 BarOffset; | |
544 | u64 dsa; | |
a2ebaf25 | 545 | int retry = 0; |
1da177e4 | 546 | u64 rc; |
252e75a5 | 547 | struct device_node *DevNode = |
1da177e4 LT |
548 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
549 | ||
550 | if (DevNode == NULL) { | |
551 | static unsigned long last_jiffies; | |
552 | static int num_printed; | |
553 | ||
554 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
555 | last_jiffies = jiffies; | |
556 | num_printed = 0; | |
557 | } | |
558 | if (num_printed++ < 10) | |
4cb3cee0 BH |
559 | printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", |
560 | IoAddress); | |
1da177e4 LT |
561 | return; |
562 | } | |
563 | do { | |
4cb3cee0 | 564 | rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, data, 0); |
a2ebaf25 | 565 | } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); |
1da177e4 | 566 | } |
caf81329 | 567 | |
4cb3cee0 | 568 | static u8 iseries_readb(const volatile void __iomem *addr) |
caf81329 | 569 | { |
4cb3cee0 | 570 | return iSeries_Read_Byte(addr); |
caf81329 | 571 | } |
caf81329 | 572 | |
4cb3cee0 | 573 | static u16 iseries_readw(const volatile void __iomem *addr) |
caf81329 | 574 | { |
4cb3cee0 | 575 | return le16_to_cpu(iSeries_Read_Word(addr)); |
caf81329 | 576 | } |
caf81329 | 577 | |
4cb3cee0 | 578 | static u32 iseries_readl(const volatile void __iomem *addr) |
caf81329 | 579 | { |
4cb3cee0 | 580 | return le32_to_cpu(iSeries_Read_Long(addr)); |
caf81329 | 581 | } |
caf81329 | 582 | |
4cb3cee0 | 583 | static u16 iseries_readw_be(const volatile void __iomem *addr) |
caf81329 | 584 | { |
4cb3cee0 | 585 | return iSeries_Read_Word(addr); |
caf81329 | 586 | } |
caf81329 | 587 | |
4cb3cee0 | 588 | static u32 iseries_readl_be(const volatile void __iomem *addr) |
caf81329 | 589 | { |
4cb3cee0 | 590 | return iSeries_Read_Long(addr); |
caf81329 | 591 | } |
caf81329 | 592 | |
4cb3cee0 | 593 | static void iseries_writeb(u8 data, volatile void __iomem *addr) |
caf81329 | 594 | { |
4cb3cee0 | 595 | iSeries_Write_Byte(data, addr); |
caf81329 | 596 | } |
caf81329 | 597 | |
4cb3cee0 | 598 | static void iseries_writew(u16 data, volatile void __iomem *addr) |
caf81329 | 599 | { |
4cb3cee0 | 600 | iSeries_Write_Word(cpu_to_le16(data), addr); |
caf81329 | 601 | } |
caf81329 | 602 | |
4cb3cee0 | 603 | static void iseries_writel(u32 data, volatile void __iomem *addr) |
caf81329 | 604 | { |
4cb3cee0 | 605 | iSeries_Write_Long(cpu_to_le32(data), addr); |
caf81329 | 606 | } |
caf81329 | 607 | |
4cb3cee0 | 608 | static void iseries_writew_be(u16 data, volatile void __iomem *addr) |
caf81329 | 609 | { |
4cb3cee0 | 610 | iSeries_Write_Word(data, addr); |
caf81329 | 611 | } |
caf81329 | 612 | |
4cb3cee0 | 613 | static void iseries_writel_be(u32 data, volatile void __iomem *addr) |
caf81329 | 614 | { |
4cb3cee0 | 615 | iSeries_Write_Long(data, addr); |
caf81329 | 616 | } |
caf81329 | 617 | |
4cb3cee0 BH |
618 | static void iseries_readsb(const volatile void __iomem *addr, void *buf, |
619 | unsigned long count) | |
caf81329 | 620 | { |
4cb3cee0 BH |
621 | u8 *dst = buf; |
622 | while(count-- > 0) | |
623 | *(dst++) = iSeries_Read_Byte(addr); | |
caf81329 | 624 | } |
caf81329 | 625 | |
4cb3cee0 BH |
626 | static void iseries_readsw(const volatile void __iomem *addr, void *buf, |
627 | unsigned long count) | |
caf81329 | 628 | { |
4cb3cee0 BH |
629 | u16 *dst = buf; |
630 | while(count-- > 0) | |
631 | *(dst++) = iSeries_Read_Word(addr); | |
caf81329 | 632 | } |
caf81329 | 633 | |
4cb3cee0 BH |
634 | static void iseries_readsl(const volatile void __iomem *addr, void *buf, |
635 | unsigned long count) | |
caf81329 | 636 | { |
4cb3cee0 BH |
637 | u32 *dst = buf; |
638 | while(count-- > 0) | |
639 | *(dst++) = iSeries_Read_Long(addr); | |
caf81329 | 640 | } |
caf81329 | 641 | |
4cb3cee0 BH |
642 | static void iseries_writesb(volatile void __iomem *addr, const void *buf, |
643 | unsigned long count) | |
caf81329 | 644 | { |
4cb3cee0 BH |
645 | const u8 *src = buf; |
646 | while(count-- > 0) | |
647 | iSeries_Write_Byte(*(src++), addr); | |
caf81329 | 648 | } |
caf81329 | 649 | |
4cb3cee0 BH |
650 | static void iseries_writesw(volatile void __iomem *addr, const void *buf, |
651 | unsigned long count) | |
caf81329 | 652 | { |
4cb3cee0 BH |
653 | const u16 *src = buf; |
654 | while(count-- > 0) | |
655 | iSeries_Write_Word(*(src++), addr); | |
caf81329 | 656 | } |
caf81329 | 657 | |
4cb3cee0 BH |
658 | static void iseries_writesl(volatile void __iomem *addr, const void *buf, |
659 | unsigned long count) | |
caf81329 | 660 | { |
4cb3cee0 BH |
661 | const u32 *src = buf; |
662 | while(count-- > 0) | |
663 | iSeries_Write_Long(*(src++), addr); | |
caf81329 | 664 | } |
caf81329 | 665 | |
4cb3cee0 BH |
666 | static void iseries_memset_io(volatile void __iomem *addr, int c, |
667 | unsigned long n) | |
caf81329 | 668 | { |
4cb3cee0 | 669 | volatile char __iomem *d = addr; |
caf81329 | 670 | |
4cb3cee0 BH |
671 | while (n-- > 0) |
672 | iSeries_Write_Byte(c, d++); | |
caf81329 | 673 | } |
caf81329 | 674 | |
4cb3cee0 BH |
675 | static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, |
676 | unsigned long n) | |
caf81329 | 677 | { |
4cb3cee0 BH |
678 | char *d = dest; |
679 | const volatile char __iomem *s = src; | |
caf81329 | 680 | |
4cb3cee0 BH |
681 | while (n-- > 0) |
682 | *d++ = iSeries_Read_Byte(s++); | |
caf81329 | 683 | } |
caf81329 | 684 | |
4cb3cee0 BH |
685 | static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, |
686 | unsigned long n) | |
caf81329 | 687 | { |
4cb3cee0 BH |
688 | const char *s = src; |
689 | volatile char __iomem *d = dest; | |
caf81329 | 690 | |
4cb3cee0 BH |
691 | while (n-- > 0) |
692 | iSeries_Write_Byte(*s++, d++); | |
caf81329 | 693 | } |
caf81329 | 694 | |
4cb3cee0 BH |
695 | /* We only set MMIO ops. The default PIO ops will be default |
696 | * to the MMIO ops + pci_io_base which is 0 on iSeries as | |
697 | * expected so both should work. | |
698 | * | |
699 | * Note that we don't implement the readq/writeq versions as | |
700 | * I don't know of an HV call for doing so. Thus, the default | |
701 | * operation will be used instead, which will fault a the value | |
702 | * return by iSeries for MMIO addresses always hits a non mapped | |
703 | * area. This is as good as the BUG() we used to have there. | |
704 | */ | |
705 | static struct ppc_pci_io __initdata iseries_pci_io = { | |
706 | .readb = iseries_readb, | |
707 | .readw = iseries_readw, | |
708 | .readl = iseries_readl, | |
709 | .readw_be = iseries_readw_be, | |
710 | .readl_be = iseries_readl_be, | |
711 | .writeb = iseries_writeb, | |
712 | .writew = iseries_writew, | |
713 | .writel = iseries_writel, | |
714 | .writew_be = iseries_writew_be, | |
715 | .writel_be = iseries_writel_be, | |
716 | .readsb = iseries_readsb, | |
717 | .readsw = iseries_readsw, | |
718 | .readsl = iseries_readsl, | |
719 | .writesb = iseries_writesb, | |
720 | .writesw = iseries_writesw, | |
721 | .writesl = iseries_writesl, | |
722 | .memset_io = iseries_memset_io, | |
723 | .memcpy_fromio = iseries_memcpy_fromio, | |
724 | .memcpy_toio = iseries_memcpy_toio, | |
725 | }; | |
caf81329 | 726 | |
4cb3cee0 BH |
727 | /* |
728 | * iSeries_pcibios_init | |
729 | * | |
730 | * Description: | |
731 | * This function checks for all possible system PCI host bridges that connect | |
732 | * PCI buses. The system hypervisor is queried as to the guest partition | |
733 | * ownership status. A pci_controller is built for any bus which is partially | |
734 | * owned or fully owned by this guest partition. | |
735 | */ | |
736 | void __init iSeries_pcibios_init(void) | |
caf81329 | 737 | { |
4cb3cee0 BH |
738 | struct pci_controller *phb; |
739 | struct device_node *root = of_find_node_by_path("/"); | |
740 | struct device_node *node = NULL; | |
caf81329 | 741 | |
4cb3cee0 BH |
742 | /* Install IO hooks */ |
743 | ppc_pci_io = iseries_pci_io; | |
caf81329 | 744 | |
3d5134ee BH |
745 | /* iSeries has no IO space in the common sense, it needs to set |
746 | * the IO base to 0 | |
747 | */ | |
748 | pci_io_base = 0; | |
749 | ||
4cb3cee0 BH |
750 | if (root == NULL) { |
751 | printk(KERN_CRIT "iSeries_pcibios_init: can't find root " | |
752 | "of device tree\n"); | |
753 | return; | |
754 | } | |
755 | while ((node = of_get_next_child(root, node)) != NULL) { | |
756 | HvBusNumber bus; | |
757 | const u32 *busp; | |
caf81329 | 758 | |
4cb3cee0 BH |
759 | if ((node->type == NULL) || (strcmp(node->type, "pci") != 0)) |
760 | continue; | |
caf81329 | 761 | |
e2eb6392 | 762 | busp = of_get_property(node, "bus-range", NULL); |
4cb3cee0 BH |
763 | if (busp == NULL) |
764 | continue; | |
765 | bus = *busp; | |
766 | printk("bus %d appears to exist\n", bus); | |
767 | phb = pcibios_alloc_controller(node); | |
768 | if (phb == NULL) | |
769 | continue; | |
caf81329 | 770 | |
bf440b71 | 771 | phb->pci_mem_offset = bus; |
4cb3cee0 BH |
772 | phb->first_busno = bus; |
773 | phb->last_busno = bus; | |
774 | phb->ops = &iSeries_pci_ops; | |
775 | } | |
caf81329 | 776 | |
4cb3cee0 | 777 | of_node_put(root); |
caf81329 | 778 | |
4cb3cee0 | 779 | pci_devs_phb_init(); |
caf81329 | 780 | } |
4cb3cee0 | 781 |