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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2001 Allan Trautman, IBM Corporation |
1dee2026 | 3 | * Copyright (C) 2005,2007 Stephen Rothwell, IBM Corp |
1da177e4 LT |
4 | * |
5 | * iSeries specific routines for PCI. | |
d387899f | 6 | * |
1da177e4 LT |
7 | * Based on code from pci.c and iSeries_pci.c 32bit |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
d387899f | 13 | * |
1da177e4 LT |
14 | * This program is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
d387899f | 18 | * |
1da177e4 LT |
19 | * You should have received a copy of the GNU General Public License |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
50c9bc2f BH |
23 | |
24 | #undef DEBUG | |
25 | ||
59861bc6 | 26 | #include <linux/jiffies.h> |
1da177e4 | 27 | #include <linux/kernel.h> |
d387899f | 28 | #include <linux/list.h> |
1da177e4 | 29 | #include <linux/string.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include <linux/init.h> |
32 | #include <linux/module.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
885b86e4 | 34 | #include <linux/of.h> |
8260cf6f | 35 | #include <linux/ratelimit.h> |
1da177e4 | 36 | |
1dee2026 | 37 | #include <asm/types.h> |
1da177e4 LT |
38 | #include <asm/io.h> |
39 | #include <asm/irq.h> | |
40 | #include <asm/prom.h> | |
41 | #include <asm/machdep.h> | |
42 | #include <asm/pci-bridge.h> | |
1da177e4 | 43 | #include <asm/iommu.h> |
426c1a11 | 44 | #include <asm/abs_addr.h> |
caf81329 | 45 | #include <asm/firmware.h> |
1da177e4 | 46 | |
1dee2026 | 47 | #include <asm/iseries/hv_types.h> |
8021b8a7 | 48 | #include <asm/iseries/hv_call_xm.h> |
bbc8b628 | 49 | #include <asm/iseries/mf.h> |
c7f0e8cb | 50 | #include <asm/iseries/iommu.h> |
1da177e4 | 51 | |
d387899f | 52 | #include <asm/ppc-pci.h> |
1da177e4 | 53 | |
b08567cb | 54 | #include "irq.h" |
426c1a11 | 55 | #include "pci.h" |
c6d2ea92 | 56 | #include "call_pci.h" |
b08567cb | 57 | |
b9b1812c SR |
58 | #define PCI_RETRY_MAX 3 |
59 | static int limit_pci_retries = 1; /* Set Retry Error on. */ | |
1da177e4 | 60 | |
1da177e4 LT |
61 | /* |
62 | * Table defines | |
63 | * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. | |
64 | */ | |
65 | #define IOMM_TABLE_MAX_ENTRIES 1024 | |
66 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | |
67 | #define BASE_IO_MEMORY 0xE000000000000000UL | |
50c9bc2f | 68 | #define END_IO_MEMORY 0xEFFFFFFFFFFFFFFFUL |
1da177e4 | 69 | |
b58b7f98 | 70 | static unsigned long max_io_memory = BASE_IO_MEMORY; |
1da177e4 LT |
71 | static long current_iomm_table_entry; |
72 | ||
73 | /* | |
74 | * Lookup Tables. | |
75 | */ | |
b58b7f98 | 76 | static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES]; |
885b86e4 | 77 | static u64 ds_addr_table[IOMM_TABLE_MAX_ENTRIES]; |
1da177e4 | 78 | |
1da177e4 LT |
79 | static DEFINE_SPINLOCK(iomm_table_lock); |
80 | ||
2cd1008c SR |
81 | /* |
82 | * Generate a Direct Select Address for the Hypervisor | |
83 | */ | |
84 | static inline u64 iseries_ds_addr(struct device_node *node) | |
85 | { | |
86 | struct pci_dn *pdn = PCI_DN(node); | |
885b86e4 | 87 | const u32 *sbp = of_get_property(node, "linux,subbus", NULL); |
2cd1008c | 88 | |
885b86e4 | 89 | return ((u64)pdn->busno << 48) + ((u64)(sbp ? *sbp : 0) << 40) |
2cd1008c SR |
90 | + ((u64)0x10 << 32); |
91 | } | |
92 | ||
1dee2026 SR |
93 | /* |
94 | * Size of Bus VPD data | |
95 | */ | |
96 | #define BUS_VPDSIZE 1024 | |
97 | ||
98 | /* | |
99 | * Bus Vpd Tags | |
100 | */ | |
101 | #define VPD_END_OF_AREA 0x79 | |
102 | #define VPD_ID_STRING 0x82 | |
103 | #define VPD_VENDOR_AREA 0x84 | |
104 | ||
105 | /* | |
106 | * Mfg Area Tags | |
107 | */ | |
108 | #define VPD_FRU_FRAME_ID 0x4649 /* "FI" */ | |
109 | #define VPD_SLOT_MAP_FORMAT 0x4D46 /* "MF" */ | |
110 | #define VPD_SLOT_MAP 0x534D /* "SM" */ | |
111 | ||
112 | /* | |
113 | * Structures of the areas | |
114 | */ | |
115 | struct mfg_vpd_area { | |
116 | u16 tag; | |
117 | u8 length; | |
118 | u8 data1; | |
119 | u8 data2; | |
120 | }; | |
121 | #define MFG_ENTRY_SIZE 3 | |
122 | ||
123 | struct slot_map { | |
124 | u8 agent; | |
125 | u8 secondary_agent; | |
126 | u8 phb; | |
127 | char card_location[3]; | |
128 | char parms[8]; | |
129 | char reserved[2]; | |
130 | }; | |
131 | #define SLOT_ENTRY_SIZE 16 | |
132 | ||
133 | /* | |
134 | * Parse the Slot Area | |
135 | */ | |
136 | static void __init iseries_parse_slot_area(struct slot_map *map, int len, | |
137 | HvAgentId agent, u8 *phb, char card[4]) | |
138 | { | |
139 | /* | |
140 | * Parse Slot label until we find the one requested | |
141 | */ | |
142 | while (len > 0) { | |
143 | if (map->agent == agent) { | |
144 | /* | |
145 | * If Phb wasn't found, grab the entry first one found. | |
146 | */ | |
147 | if (*phb == 0xff) | |
148 | *phb = map->phb; | |
149 | /* Found it, extract the data. */ | |
150 | if (map->phb == *phb) { | |
151 | memcpy(card, &map->card_location, 3); | |
152 | card[3] = 0; | |
153 | break; | |
154 | } | |
155 | } | |
156 | /* Point to the next Slot */ | |
157 | map = (struct slot_map *)((char *)map + SLOT_ENTRY_SIZE); | |
158 | len -= SLOT_ENTRY_SIZE; | |
159 | } | |
160 | } | |
161 | ||
162 | /* | |
163 | * Parse the Mfg Area | |
164 | */ | |
165 | static void __init iseries_parse_mfg_area(struct mfg_vpd_area *area, int len, | |
166 | HvAgentId agent, u8 *phb, u8 *frame, char card[4]) | |
167 | { | |
168 | u16 slot_map_fmt = 0; | |
169 | ||
170 | /* Parse Mfg Data */ | |
171 | while (len > 0) { | |
172 | int mfg_tag_len = area->length; | |
173 | /* Frame ID (FI 4649020310 ) */ | |
174 | if (area->tag == VPD_FRU_FRAME_ID) | |
175 | *frame = area->data1; | |
176 | /* Slot Map Format (MF 4D46020004 ) */ | |
177 | else if (area->tag == VPD_SLOT_MAP_FORMAT) | |
178 | slot_map_fmt = (area->data1 * 256) | |
179 | + area->data2; | |
180 | /* Slot Map (SM 534D90 */ | |
181 | else if (area->tag == VPD_SLOT_MAP) { | |
182 | struct slot_map *slot_map; | |
183 | ||
184 | if (slot_map_fmt == 0x1004) | |
185 | slot_map = (struct slot_map *)((char *)area | |
186 | + MFG_ENTRY_SIZE + 1); | |
187 | else | |
188 | slot_map = (struct slot_map *)((char *)area | |
189 | + MFG_ENTRY_SIZE); | |
190 | iseries_parse_slot_area(slot_map, mfg_tag_len, | |
191 | agent, phb, card); | |
192 | } | |
193 | /* | |
194 | * Point to the next Mfg Area | |
195 | * Use defined size, sizeof give wrong answer | |
196 | */ | |
197 | area = (struct mfg_vpd_area *)((char *)area + mfg_tag_len | |
198 | + MFG_ENTRY_SIZE); | |
199 | len -= (mfg_tag_len + MFG_ENTRY_SIZE); | |
200 | } | |
201 | } | |
202 | ||
203 | /* | |
204 | * Look for "BUS".. Data is not Null terminated. | |
205 | * PHBID of 0xFF indicates PHB was not found in VPD Data. | |
206 | */ | |
207 | static u8 __init iseries_parse_phbid(u8 *area, int len) | |
208 | { | |
209 | while (len > 0) { | |
210 | if ((*area == 'B') && (*(area + 1) == 'U') | |
211 | && (*(area + 2) == 'S')) { | |
212 | area += 3; | |
213 | while (*area == ' ') | |
214 | area++; | |
215 | return *area & 0x0F; | |
216 | } | |
217 | area++; | |
218 | len--; | |
219 | } | |
220 | return 0xff; | |
221 | } | |
222 | ||
223 | /* | |
224 | * Parse out the VPD Areas | |
225 | */ | |
226 | static void __init iseries_parse_vpd(u8 *data, int data_len, | |
227 | HvAgentId agent, u8 *frame, char card[4]) | |
228 | { | |
229 | u8 phb = 0xff; | |
230 | ||
231 | while (data_len > 0) { | |
232 | int len; | |
233 | u8 tag = *data; | |
234 | ||
235 | if (tag == VPD_END_OF_AREA) | |
236 | break; | |
237 | len = *(data + 1) + (*(data + 2) * 256); | |
238 | data += 3; | |
239 | data_len -= 3; | |
240 | if (tag == VPD_ID_STRING) | |
241 | phb = iseries_parse_phbid(data, len); | |
242 | else if (tag == VPD_VENDOR_AREA) | |
243 | iseries_parse_mfg_area((struct mfg_vpd_area *)data, len, | |
244 | agent, &phb, frame, card); | |
245 | /* Point to next Area. */ | |
246 | data += len; | |
247 | data_len -= len; | |
248 | } | |
249 | } | |
250 | ||
251 | static int __init iseries_get_location_code(u16 bus, HvAgentId agent, | |
252 | u8 *frame, char card[4]) | |
253 | { | |
254 | int status = 0; | |
255 | int bus_vpd_len = 0; | |
256 | u8 *bus_vpd = kmalloc(BUS_VPDSIZE, GFP_KERNEL); | |
257 | ||
258 | if (bus_vpd == NULL) { | |
259 | printk("PCI: Bus VPD Buffer allocation failure.\n"); | |
260 | return 0; | |
261 | } | |
262 | bus_vpd_len = HvCallPci_getBusVpd(bus, iseries_hv_addr(bus_vpd), | |
263 | BUS_VPDSIZE); | |
264 | if (bus_vpd_len == 0) { | |
265 | printk("PCI: Bus VPD Buffer zero length.\n"); | |
266 | goto out_free; | |
267 | } | |
268 | /* printk("PCI: bus_vpd: %p, %d\n",bus_vpd, bus_vpd_len); */ | |
269 | /* Make sure this is what I think it is */ | |
270 | if (*bus_vpd != VPD_ID_STRING) { | |
271 | printk("PCI: Bus VPD Buffer missing starting tag.\n"); | |
272 | goto out_free; | |
273 | } | |
274 | iseries_parse_vpd(bus_vpd, bus_vpd_len, agent, frame, card); | |
275 | status = 1; | |
276 | out_free: | |
277 | kfree(bus_vpd); | |
278 | return status; | |
279 | } | |
280 | ||
281 | /* | |
282 | * Prints the device information. | |
283 | * - Pass in pci_dev* pointer to the device. | |
284 | * - Pass in the device count | |
285 | * | |
286 | * Format: | |
287 | * PCI: Bus 0, Device 26, Vendor 0x12AE Frame 1, Card C10 Ethernet | |
288 | * controller | |
289 | */ | |
50c9bc2f BH |
290 | static void __init iseries_device_information(struct pci_dev *pdev, |
291 | u16 bus, HvSubBusNumber subbus) | |
1dee2026 SR |
292 | { |
293 | u8 frame = 0; | |
294 | char card[4]; | |
295 | HvAgentId agent; | |
296 | ||
297 | agent = ISERIES_PCI_AGENTID(ISERIES_GET_DEVICE_FROM_SUBBUS(subbus), | |
298 | ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus)); | |
299 | ||
300 | if (iseries_get_location_code(bus, agent, &frame, card)) { | |
50c9bc2f BH |
301 | printk(KERN_INFO "PCI: %s, Vendor %04X Frame%3d, " |
302 | "Card %4s 0x%04X\n", pci_name(pdev), pdev->vendor, | |
303 | frame, card, (int)(pdev->class >> 8)); | |
1dee2026 SR |
304 | } |
305 | } | |
306 | ||
1da177e4 LT |
307 | /* |
308 | * iomm_table_allocate_entry | |
309 | * | |
310 | * Adds pci_dev entry in address translation table | |
311 | * | |
312 | * - Allocates the number of entries required in table base on BAR | |
313 | * size. | |
314 | * - Allocates starting at BASE_IO_MEMORY and increases. | |
315 | * - The size is round up to be a multiple of entry size. | |
316 | * - CurrentIndex is incremented to keep track of the last entry. | |
317 | * - Builds the resource entry for allocated BARs. | |
318 | */ | |
1e105904 | 319 | static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) |
1da177e4 LT |
320 | { |
321 | struct resource *bar_res = &dev->resource[bar_num]; | |
322 | long bar_size = pci_resource_len(dev, bar_num); | |
d7b41b1f | 323 | struct device_node *dn = pci_device_to_OF_node(dev); |
1da177e4 LT |
324 | |
325 | /* | |
326 | * No space to allocate, quick exit, skip Allocation. | |
327 | */ | |
328 | if (bar_size == 0) | |
329 | return; | |
330 | /* | |
331 | * Set Resource values. | |
332 | */ | |
333 | spin_lock(&iomm_table_lock); | |
b58b7f98 | 334 | bar_res->start = BASE_IO_MEMORY + |
1da177e4 | 335 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
336 | bar_res->end = bar_res->start + bar_size - 1; |
337 | /* | |
338 | * Allocate the number of table entries needed for BAR. | |
339 | */ | |
340 | while (bar_size > 0 ) { | |
d7b41b1f | 341 | iomm_table[current_iomm_table_entry] = dn; |
885b86e4 | 342 | ds_addr_table[current_iomm_table_entry] = |
d7b41b1f | 343 | iseries_ds_addr(dn) | (bar_num << 24); |
1da177e4 LT |
344 | bar_size -= IOMM_TABLE_ENTRY_SIZE; |
345 | ++current_iomm_table_entry; | |
346 | } | |
347 | max_io_memory = BASE_IO_MEMORY + | |
b58b7f98 | 348 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
1da177e4 LT |
349 | spin_unlock(&iomm_table_lock); |
350 | } | |
351 | ||
352 | /* | |
353 | * allocate_device_bars | |
354 | * | |
355 | * - Allocates ALL pci_dev BAR's and updates the resources with the | |
356 | * BAR value. BARS with zero length will have the resources | |
357 | * The HvCallPci_getBarParms is used to get the size of the BAR | |
358 | * space. It calls iomm_table_allocate_entry to allocate | |
359 | * each entry. | |
360 | * - Loops through The Bar resources(0 - 5) including the ROM | |
361 | * is resource(6). | |
362 | */ | |
1e105904 | 363 | static void __init allocate_device_bars(struct pci_dev *dev) |
1da177e4 | 364 | { |
1da177e4 LT |
365 | int bar_num; |
366 | ||
b58b7f98 | 367 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) |
1da177e4 | 368 | iomm_table_allocate_entry(dev, bar_num); |
1da177e4 LT |
369 | } |
370 | ||
371 | /* | |
372 | * Log error information to system console. | |
373 | * Filter out the device not there errors. | |
374 | * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx | |
375 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | |
376 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | |
377 | */ | |
7a73bd7f SR |
378 | static void pci_log_error(char *error, int bus, int subbus, |
379 | int agent, int hv_res) | |
1da177e4 | 380 | { |
7a73bd7f | 381 | if (hv_res == 0x0302) |
1da177e4 LT |
382 | return; |
383 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | |
7a73bd7f | 384 | error, bus, subbus, agent, hv_res); |
1da177e4 LT |
385 | } |
386 | ||
9103eb7d SR |
387 | /* |
388 | * Look down the chain to find the matching Device Device | |
389 | */ | |
7a73bd7f | 390 | static struct device_node *find_device_node(int bus, int devfn) |
9103eb7d SR |
391 | { |
392 | struct device_node *node; | |
393 | ||
394 | for (node = NULL; (node = of_find_all_nodes(node)); ) { | |
395 | struct pci_dn *pdn = PCI_DN(node); | |
396 | ||
397 | if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn)) | |
398 | return node; | |
399 | } | |
400 | return NULL; | |
401 | } | |
402 | ||
1da177e4 | 403 | /* |
50c9bc2f BH |
404 | * iSeries_pcibios_fixup_resources |
405 | * | |
406 | * Fixes up all resources for devices | |
1da177e4 | 407 | */ |
50c9bc2f | 408 | void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev) |
1da177e4 | 409 | { |
50c9bc2f BH |
410 | const u32 *agent; |
411 | const u32 *sub_bus; | |
412 | unsigned char bus = pdev->bus->number; | |
252e75a5 | 413 | struct device_node *node; |
50c9bc2f BH |
414 | int i; |
415 | ||
d7b41b1f | 416 | node = pci_device_to_OF_node(pdev); |
50c9bc2f BH |
417 | pr_debug("PCI: iSeries %s, pdev %p, node %p\n", |
418 | pci_name(pdev), pdev, node); | |
419 | if (!node) { | |
420 | printk("PCI: %s disabled, device tree entry not found !\n", | |
421 | pci_name(pdev)); | |
422 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
423 | pdev->resource[i].flags = 0; | |
424 | return; | |
425 | } | |
426 | sub_bus = of_get_property(node, "linux,subbus", NULL); | |
427 | agent = of_get_property(node, "linux,agent-id", NULL); | |
428 | if (agent && sub_bus) { | |
429 | u8 irq = iSeries_allocate_IRQ(bus, 0, *sub_bus); | |
430 | int err; | |
431 | ||
432 | err = HvCallXm_connectBusUnit(bus, *sub_bus, *agent, irq); | |
433 | if (err) | |
434 | pci_log_error("Connect Bus Unit", | |
435 | bus, *sub_bus, *agent, err); | |
436 | else { | |
437 | err = HvCallPci_configStore8(bus, *sub_bus, | |
53761746 | 438 | *agent, PCI_INTERRUPT_LINE, irq); |
50c9bc2f BH |
439 | if (err) |
440 | pci_log_error("PciCfgStore Irq Failed!", | |
53761746 | 441 | bus, *sub_bus, *agent, err); |
50c9bc2f BH |
442 | else |
443 | pdev->irq = irq; | |
3f178632 | 444 | } |
1da177e4 | 445 | } |
50c9bc2f | 446 | |
50c9bc2f BH |
447 | allocate_device_bars(pdev); |
448 | iseries_device_information(pdev, bus, *sub_bus); | |
50c9bc2f BH |
449 | } |
450 | ||
451 | /* | |
452 | * iSeries_pci_final_fixup(void) | |
453 | */ | |
454 | void __init iSeries_pci_final_fixup(void) | |
455 | { | |
456 | /* Fix up at the device node and pci_dev relationship */ | |
457 | mf_display_src(0xC9000100); | |
1da177e4 LT |
458 | iSeries_activate_IRQs(); |
459 | mf_display_src(0xC9000200); | |
460 | } | |
461 | ||
1da177e4 LT |
462 | /* |
463 | * Config space read and write functions. | |
464 | * For now at least, we look for the device node for the bus and devfn | |
465 | * that we are asked to access. It may be possible to translate the devfn | |
466 | * to a subbus and deviceid more directly. | |
467 | */ | |
468 | static u64 hv_cfg_read_func[4] = { | |
469 | HvCallPciConfigLoad8, HvCallPciConfigLoad16, | |
470 | HvCallPciConfigLoad32, HvCallPciConfigLoad32 | |
471 | }; | |
472 | ||
473 | static u64 hv_cfg_write_func[4] = { | |
474 | HvCallPciConfigStore8, HvCallPciConfigStore16, | |
475 | HvCallPciConfigStore32, HvCallPciConfigStore32 | |
476 | }; | |
477 | ||
478 | /* | |
479 | * Read PCI config space | |
480 | */ | |
481 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
482 | int offset, int size, u32 *val) | |
483 | { | |
7a73bd7f | 484 | struct device_node *node = find_device_node(bus->number, devfn); |
1da177e4 LT |
485 | u64 fn; |
486 | struct HvCallPci_LoadReturn ret; | |
487 | ||
488 | if (node == NULL) | |
489 | return PCIBIOS_DEVICE_NOT_FOUND; | |
490 | if (offset > 255) { | |
491 | *val = ~0; | |
492 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
493 | } | |
494 | ||
495 | fn = hv_cfg_read_func[(size - 1) & 3]; | |
20f48ccf | 496 | HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0); |
1da177e4 LT |
497 | |
498 | if (ret.rc != 0) { | |
499 | *val = ~0; | |
500 | return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ | |
501 | } | |
502 | ||
503 | *val = ret.value; | |
504 | return 0; | |
505 | } | |
506 | ||
507 | /* | |
508 | * Write PCI config space | |
509 | */ | |
510 | ||
511 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
512 | int offset, int size, u32 val) | |
513 | { | |
7a73bd7f | 514 | struct device_node *node = find_device_node(bus->number, devfn); |
1da177e4 LT |
515 | u64 fn; |
516 | u64 ret; | |
517 | ||
518 | if (node == NULL) | |
519 | return PCIBIOS_DEVICE_NOT_FOUND; | |
520 | if (offset > 255) | |
521 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
522 | ||
523 | fn = hv_cfg_write_func[(size - 1) & 3]; | |
20f48ccf | 524 | ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0); |
1da177e4 LT |
525 | |
526 | if (ret != 0) | |
527 | return PCIBIOS_DEVICE_NOT_FOUND; | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
532 | static struct pci_ops iSeries_pci_ops = { | |
533 | .read = iSeries_pci_read_config, | |
534 | .write = iSeries_pci_write_config | |
535 | }; | |
536 | ||
537 | /* | |
538 | * Check Return Code | |
539 | * -> On Failure, print and log information. | |
540 | * Increment Retry Count, if exceeds max, panic partition. | |
1da177e4 LT |
541 | * |
542 | * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 | |
543 | * PCI: Device 23.90 ReadL Retry( 1) | |
544 | * PCI: Device 23.90 ReadL Retry Successful(1) | |
545 | */ | |
7a73bd7f | 546 | static int check_return_code(char *type, struct device_node *dn, |
a2ebaf25 | 547 | int *retry, u64 ret) |
1da177e4 LT |
548 | { |
549 | if (ret != 0) { | |
7a73bd7f | 550 | struct pci_dn *pdn = PCI_DN(dn); |
252e75a5 | 551 | |
a2ebaf25 | 552 | (*retry)++; |
1da177e4 | 553 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
7a73bd7f | 554 | type, pdn->busno, pdn->devfn, |
a2ebaf25 | 555 | *retry, (int)ret); |
1da177e4 LT |
556 | /* |
557 | * Bump the retry and check for retry count exceeded. | |
558 | * If, Exceeded, panic the system. | |
559 | */ | |
b9b1812c SR |
560 | if (((*retry) > PCI_RETRY_MAX) && |
561 | (limit_pci_retries > 0)) { | |
1da177e4 | 562 | mf_display_src(0xB6000103); |
a2ebaf25 | 563 | panic_timeout = 0; |
1da177e4 LT |
564 | panic("PCI: Hardware I/O Error, SRC B6000103, " |
565 | "Automatic Reboot Disabled.\n"); | |
566 | } | |
567 | return -1; /* Retry Try */ | |
568 | } | |
a2ebaf25 | 569 | return 0; |
1da177e4 LT |
570 | } |
571 | ||
572 | /* | |
573 | * Translate the I/O Address into a device node, bar, and bar offset. | |
574 | * Note: Make sure the passed variable end up on the stack to avoid | |
575 | * the exposure of being device global. | |
576 | */ | |
252e75a5 | 577 | static inline struct device_node *xlate_iomm_address( |
7a73bd7f | 578 | const volatile void __iomem *addr, |
0d416f2a | 579 | u64 *dsaptr, u64 *bar_offset, const char *func) |
1da177e4 | 580 | { |
7a73bd7f SR |
581 | unsigned long orig_addr; |
582 | unsigned long base_addr; | |
583 | unsigned long ind; | |
584 | struct device_node *dn; | |
1da177e4 | 585 | |
7a73bd7f | 586 | orig_addr = (unsigned long __force)addr; |
0d416f2a | 587 | if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) { |
8260cf6f | 588 | static DEFINE_RATELIMIT_STATE(ratelimit, 60 * HZ, 10); |
0d416f2a | 589 | |
8260cf6f | 590 | if (__ratelimit(&ratelimit)) |
0d416f2a SR |
591 | printk(KERN_ERR |
592 | "iSeries_%s: invalid access at IO address %p\n", | |
593 | func, addr); | |
1da177e4 | 594 | return NULL; |
0d416f2a | 595 | } |
7a73bd7f SR |
596 | base_addr = orig_addr - BASE_IO_MEMORY; |
597 | ind = base_addr / IOMM_TABLE_ENTRY_SIZE; | |
598 | dn = iomm_table[ind]; | |
599 | ||
600 | if (dn != NULL) { | |
885b86e4 | 601 | *dsaptr = ds_addr_table[ind]; |
7a73bd7f | 602 | *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE; |
1da177e4 | 603 | } else |
7a73bd7f SR |
604 | panic("PCI: Invalid PCI IO address detected!\n"); |
605 | return dn; | |
1da177e4 LT |
606 | } |
607 | ||
608 | /* | |
609 | * Read MM I/O Instructions for the iSeries | |
610 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | |
4cb3cee0 | 611 | * else, data is returned in Big Endian format. |
1da177e4 | 612 | */ |
34489388 | 613 | static u8 iseries_readb(const volatile void __iomem *addr) |
1da177e4 | 614 | { |
7a73bd7f | 615 | u64 bar_offset; |
1da177e4 | 616 | u64 dsa; |
a2ebaf25 | 617 | int retry = 0; |
1da177e4 | 618 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 619 | struct device_node *dn = |
0d416f2a | 620 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte"); |
1da177e4 | 621 | |
0d416f2a | 622 | if (dn == NULL) |
1da177e4 | 623 | return 0xff; |
1da177e4 | 624 | do { |
7a73bd7f SR |
625 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0); |
626 | } while (check_return_code("RDB", dn, &retry, ret.rc) != 0); | |
1da177e4 | 627 | |
4cb3cee0 | 628 | return ret.value; |
1da177e4 | 629 | } |
1da177e4 | 630 | |
34489388 | 631 | static u16 iseries_readw_be(const volatile void __iomem *addr) |
1da177e4 | 632 | { |
7a73bd7f | 633 | u64 bar_offset; |
1da177e4 | 634 | u64 dsa; |
a2ebaf25 | 635 | int retry = 0; |
1da177e4 | 636 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 637 | struct device_node *dn = |
0d416f2a | 638 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_word"); |
1da177e4 | 639 | |
0d416f2a | 640 | if (dn == NULL) |
1da177e4 | 641 | return 0xffff; |
1da177e4 | 642 | do { |
1da177e4 | 643 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, |
7a73bd7f SR |
644 | bar_offset, 0); |
645 | } while (check_return_code("RDW", dn, &retry, ret.rc) != 0); | |
1da177e4 | 646 | |
4cb3cee0 | 647 | return ret.value; |
1da177e4 | 648 | } |
1da177e4 | 649 | |
34489388 | 650 | static u32 iseries_readl_be(const volatile void __iomem *addr) |
1da177e4 | 651 | { |
7a73bd7f | 652 | u64 bar_offset; |
1da177e4 | 653 | u64 dsa; |
a2ebaf25 | 654 | int retry = 0; |
1da177e4 | 655 | struct HvCallPci_LoadReturn ret; |
7a73bd7f | 656 | struct device_node *dn = |
0d416f2a | 657 | xlate_iomm_address(addr, &dsa, &bar_offset, "read_long"); |
1da177e4 | 658 | |
0d416f2a | 659 | if (dn == NULL) |
1da177e4 | 660 | return 0xffffffff; |
1da177e4 | 661 | do { |
1da177e4 | 662 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, |
7a73bd7f SR |
663 | bar_offset, 0); |
664 | } while (check_return_code("RDL", dn, &retry, ret.rc) != 0); | |
1da177e4 | 665 | |
4cb3cee0 | 666 | return ret.value; |
1da177e4 | 667 | } |
1da177e4 LT |
668 | |
669 | /* | |
670 | * Write MM I/O Instructions for the iSeries | |
671 | * | |
1da177e4 | 672 | */ |
34489388 | 673 | static void iseries_writeb(u8 data, volatile void __iomem *addr) |
1da177e4 | 674 | { |
7a73bd7f | 675 | u64 bar_offset; |
1da177e4 | 676 | u64 dsa; |
a2ebaf25 | 677 | int retry = 0; |
1da177e4 | 678 | u64 rc; |
7a73bd7f | 679 | struct device_node *dn = |
0d416f2a | 680 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte"); |
1da177e4 | 681 | |
0d416f2a | 682 | if (dn == NULL) |
1da177e4 | 683 | return; |
1da177e4 | 684 | do { |
7a73bd7f SR |
685 | rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0); |
686 | } while (check_return_code("WWB", dn, &retry, rc) != 0); | |
1da177e4 | 687 | } |
1da177e4 | 688 | |
34489388 | 689 | static void iseries_writew_be(u16 data, volatile void __iomem *addr) |
1da177e4 | 690 | { |
7a73bd7f | 691 | u64 bar_offset; |
1da177e4 | 692 | u64 dsa; |
a2ebaf25 | 693 | int retry = 0; |
1da177e4 | 694 | u64 rc; |
7a73bd7f | 695 | struct device_node *dn = |
0d416f2a | 696 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_word"); |
1da177e4 | 697 | |
0d416f2a | 698 | if (dn == NULL) |
1da177e4 | 699 | return; |
1da177e4 | 700 | do { |
7a73bd7f SR |
701 | rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0); |
702 | } while (check_return_code("WWW", dn, &retry, rc) != 0); | |
1da177e4 | 703 | } |
1da177e4 | 704 | |
34489388 | 705 | static void iseries_writel_be(u32 data, volatile void __iomem *addr) |
1da177e4 | 706 | { |
7a73bd7f | 707 | u64 bar_offset; |
1da177e4 | 708 | u64 dsa; |
a2ebaf25 | 709 | int retry = 0; |
1da177e4 | 710 | u64 rc; |
7a73bd7f | 711 | struct device_node *dn = |
0d416f2a | 712 | xlate_iomm_address(addr, &dsa, &bar_offset, "write_long"); |
1da177e4 | 713 | |
0d416f2a | 714 | if (dn == NULL) |
1da177e4 | 715 | return; |
1da177e4 | 716 | do { |
7a73bd7f SR |
717 | rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0); |
718 | } while (check_return_code("WWL", dn, &retry, rc) != 0); | |
1da177e4 | 719 | } |
caf81329 | 720 | |
4cb3cee0 | 721 | static u16 iseries_readw(const volatile void __iomem *addr) |
caf81329 | 722 | { |
34489388 | 723 | return le16_to_cpu(iseries_readw_be(addr)); |
caf81329 | 724 | } |
caf81329 | 725 | |
4cb3cee0 | 726 | static u32 iseries_readl(const volatile void __iomem *addr) |
caf81329 | 727 | { |
34489388 | 728 | return le32_to_cpu(iseries_readl_be(addr)); |
caf81329 | 729 | } |
caf81329 | 730 | |
4cb3cee0 | 731 | static void iseries_writew(u16 data, volatile void __iomem *addr) |
caf81329 | 732 | { |
34489388 | 733 | iseries_writew_be(cpu_to_le16(data), addr); |
caf81329 | 734 | } |
caf81329 | 735 | |
4cb3cee0 | 736 | static void iseries_writel(u32 data, volatile void __iomem *addr) |
caf81329 | 737 | { |
34489388 | 738 | iseries_writel(cpu_to_le32(data), addr); |
caf81329 | 739 | } |
caf81329 | 740 | |
4cb3cee0 BH |
741 | static void iseries_readsb(const volatile void __iomem *addr, void *buf, |
742 | unsigned long count) | |
caf81329 | 743 | { |
4cb3cee0 BH |
744 | u8 *dst = buf; |
745 | while(count-- > 0) | |
34489388 | 746 | *(dst++) = iseries_readb(addr); |
caf81329 | 747 | } |
caf81329 | 748 | |
4cb3cee0 BH |
749 | static void iseries_readsw(const volatile void __iomem *addr, void *buf, |
750 | unsigned long count) | |
caf81329 | 751 | { |
4cb3cee0 BH |
752 | u16 *dst = buf; |
753 | while(count-- > 0) | |
34489388 | 754 | *(dst++) = iseries_readw_be(addr); |
caf81329 | 755 | } |
caf81329 | 756 | |
4cb3cee0 BH |
757 | static void iseries_readsl(const volatile void __iomem *addr, void *buf, |
758 | unsigned long count) | |
caf81329 | 759 | { |
4cb3cee0 BH |
760 | u32 *dst = buf; |
761 | while(count-- > 0) | |
34489388 | 762 | *(dst++) = iseries_readl_be(addr); |
caf81329 | 763 | } |
caf81329 | 764 | |
4cb3cee0 BH |
765 | static void iseries_writesb(volatile void __iomem *addr, const void *buf, |
766 | unsigned long count) | |
caf81329 | 767 | { |
4cb3cee0 BH |
768 | const u8 *src = buf; |
769 | while(count-- > 0) | |
34489388 | 770 | iseries_writeb(*(src++), addr); |
caf81329 | 771 | } |
caf81329 | 772 | |
4cb3cee0 BH |
773 | static void iseries_writesw(volatile void __iomem *addr, const void *buf, |
774 | unsigned long count) | |
caf81329 | 775 | { |
4cb3cee0 BH |
776 | const u16 *src = buf; |
777 | while(count-- > 0) | |
34489388 | 778 | iseries_writew_be(*(src++), addr); |
caf81329 | 779 | } |
caf81329 | 780 | |
4cb3cee0 BH |
781 | static void iseries_writesl(volatile void __iomem *addr, const void *buf, |
782 | unsigned long count) | |
caf81329 | 783 | { |
4cb3cee0 BH |
784 | const u32 *src = buf; |
785 | while(count-- > 0) | |
34489388 | 786 | iseries_writel_be(*(src++), addr); |
caf81329 | 787 | } |
caf81329 | 788 | |
4cb3cee0 BH |
789 | static void iseries_memset_io(volatile void __iomem *addr, int c, |
790 | unsigned long n) | |
caf81329 | 791 | { |
4cb3cee0 | 792 | volatile char __iomem *d = addr; |
caf81329 | 793 | |
4cb3cee0 | 794 | while (n-- > 0) |
34489388 | 795 | iseries_writeb(c, d++); |
caf81329 | 796 | } |
caf81329 | 797 | |
4cb3cee0 BH |
798 | static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, |
799 | unsigned long n) | |
caf81329 | 800 | { |
4cb3cee0 BH |
801 | char *d = dest; |
802 | const volatile char __iomem *s = src; | |
caf81329 | 803 | |
4cb3cee0 | 804 | while (n-- > 0) |
34489388 | 805 | *d++ = iseries_readb(s++); |
caf81329 | 806 | } |
caf81329 | 807 | |
4cb3cee0 BH |
808 | static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, |
809 | unsigned long n) | |
caf81329 | 810 | { |
4cb3cee0 BH |
811 | const char *s = src; |
812 | volatile char __iomem *d = dest; | |
caf81329 | 813 | |
4cb3cee0 | 814 | while (n-- > 0) |
34489388 | 815 | iseries_writeb(*s++, d++); |
caf81329 | 816 | } |
caf81329 | 817 | |
4cb3cee0 BH |
818 | /* We only set MMIO ops. The default PIO ops will be default |
819 | * to the MMIO ops + pci_io_base which is 0 on iSeries as | |
820 | * expected so both should work. | |
821 | * | |
822 | * Note that we don't implement the readq/writeq versions as | |
823 | * I don't know of an HV call for doing so. Thus, the default | |
824 | * operation will be used instead, which will fault a the value | |
825 | * return by iSeries for MMIO addresses always hits a non mapped | |
826 | * area. This is as good as the BUG() we used to have there. | |
827 | */ | |
828 | static struct ppc_pci_io __initdata iseries_pci_io = { | |
829 | .readb = iseries_readb, | |
830 | .readw = iseries_readw, | |
831 | .readl = iseries_readl, | |
832 | .readw_be = iseries_readw_be, | |
833 | .readl_be = iseries_readl_be, | |
834 | .writeb = iseries_writeb, | |
835 | .writew = iseries_writew, | |
836 | .writel = iseries_writel, | |
837 | .writew_be = iseries_writew_be, | |
838 | .writel_be = iseries_writel_be, | |
839 | .readsb = iseries_readsb, | |
840 | .readsw = iseries_readsw, | |
841 | .readsl = iseries_readsl, | |
842 | .writesb = iseries_writesb, | |
843 | .writesw = iseries_writesw, | |
844 | .writesl = iseries_writesl, | |
845 | .memset_io = iseries_memset_io, | |
846 | .memcpy_fromio = iseries_memcpy_fromio, | |
847 | .memcpy_toio = iseries_memcpy_toio, | |
848 | }; | |
caf81329 | 849 | |
4cb3cee0 BH |
850 | /* |
851 | * iSeries_pcibios_init | |
852 | * | |
853 | * Description: | |
854 | * This function checks for all possible system PCI host bridges that connect | |
855 | * PCI buses. The system hypervisor is queried as to the guest partition | |
856 | * ownership status. A pci_controller is built for any bus which is partially | |
857 | * owned or fully owned by this guest partition. | |
858 | */ | |
859 | void __init iSeries_pcibios_init(void) | |
caf81329 | 860 | { |
4cb3cee0 BH |
861 | struct pci_controller *phb; |
862 | struct device_node *root = of_find_node_by_path("/"); | |
863 | struct device_node *node = NULL; | |
caf81329 | 864 | |
4cb3cee0 BH |
865 | /* Install IO hooks */ |
866 | ppc_pci_io = iseries_pci_io; | |
caf81329 | 867 | |
9ccc4fd2 SR |
868 | pci_probe_only = 1; |
869 | ||
3d5134ee BH |
870 | /* iSeries has no IO space in the common sense, it needs to set |
871 | * the IO base to 0 | |
872 | */ | |
873 | pci_io_base = 0; | |
874 | ||
4cb3cee0 BH |
875 | if (root == NULL) { |
876 | printk(KERN_CRIT "iSeries_pcibios_init: can't find root " | |
877 | "of device tree\n"); | |
878 | return; | |
879 | } | |
880 | while ((node = of_get_next_child(root, node)) != NULL) { | |
881 | HvBusNumber bus; | |
882 | const u32 *busp; | |
caf81329 | 883 | |
4cb3cee0 BH |
884 | if ((node->type == NULL) || (strcmp(node->type, "pci") != 0)) |
885 | continue; | |
caf81329 | 886 | |
e2eb6392 | 887 | busp = of_get_property(node, "bus-range", NULL); |
4cb3cee0 BH |
888 | if (busp == NULL) |
889 | continue; | |
890 | bus = *busp; | |
891 | printk("bus %d appears to exist\n", bus); | |
892 | phb = pcibios_alloc_controller(node); | |
893 | if (phb == NULL) | |
894 | continue; | |
6207e816 SR |
895 | /* All legacy iSeries PHBs are in domain zero */ |
896 | phb->global_number = 0; | |
caf81329 | 897 | |
4cb3cee0 BH |
898 | phb->first_busno = bus; |
899 | phb->last_busno = bus; | |
900 | phb->ops = &iSeries_pci_ops; | |
50c9bc2f BH |
901 | phb->io_base_virt = (void __iomem *)_IO_BASE; |
902 | phb->io_resource.flags = IORESOURCE_IO; | |
903 | phb->io_resource.start = BASE_IO_MEMORY; | |
904 | phb->io_resource.end = END_IO_MEMORY; | |
905 | phb->io_resource.name = "iSeries PCI IO"; | |
906 | phb->mem_resources[0].flags = IORESOURCE_MEM; | |
907 | phb->mem_resources[0].start = BASE_IO_MEMORY; | |
908 | phb->mem_resources[0].end = END_IO_MEMORY; | |
909 | phb->mem_resources[0].name = "Series PCI MEM"; | |
4cb3cee0 | 910 | } |
caf81329 | 911 | |
4cb3cee0 | 912 | of_node_put(root); |
caf81329 | 913 | |
4cb3cee0 | 914 | pci_devs_phb_init(); |
caf81329 | 915 | } |
4cb3cee0 | 916 |