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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Allan Trautman, IBM Corporation |
3 | * | |
4 | * iSeries specific routines for PCI. | |
d387899f | 5 | * |
1da177e4 LT |
6 | * Based on code from pci.c and iSeries_pci.c 32bit |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
d387899f | 12 | * |
1da177e4 LT |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
d387899f | 17 | * |
1da177e4 LT |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/kernel.h> | |
d387899f | 23 | #include <linux/list.h> |
1da177e4 LT |
24 | #include <linux/string.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/ide.h> | |
28 | #include <linux/pci.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/pci-bridge.h> | |
35 | #include <asm/ppcdebug.h> | |
36 | #include <asm/iommu.h> | |
37 | ||
38 | #include <asm/iSeries/HvCallPci.h> | |
1da177e4 | 39 | #include <asm/iSeries/HvCallXm.h> |
1da177e4 LT |
40 | #include <asm/iSeries/iSeries_pci.h> |
41 | #include <asm/iSeries/mf.h> | |
42 | ||
d387899f | 43 | #include <asm/ppc-pci.h> |
1da177e4 | 44 | |
b08567cb SR |
45 | #include "irq.h" |
46 | ||
1da177e4 LT |
47 | extern unsigned long io_page_mask; |
48 | ||
49 | /* | |
d387899f | 50 | * Forward declares of prototypes. |
1da177e4 | 51 | */ |
252e75a5 | 52 | static struct device_node *find_Device_Node(int bus, int devfn); |
1da177e4 LT |
53 | static void scan_PHB_slots(struct pci_controller *Phb); |
54 | static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel); | |
55 | static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info); | |
56 | ||
57 | LIST_HEAD(iSeries_Global_Device_List); | |
58 | ||
59 | static int DeviceCount; | |
60 | ||
61 | /* Counters and control flags. */ | |
62 | static long Pci_Io_Read_Count; | |
63 | static long Pci_Io_Write_Count; | |
64 | #if 0 | |
65 | static long Pci_Cfg_Read_Count; | |
66 | static long Pci_Cfg_Write_Count; | |
67 | #endif | |
68 | static long Pci_Error_Count; | |
69 | ||
d387899f | 70 | static int Pci_Retry_Max = 3; /* Only retry 3 times */ |
1da177e4 LT |
71 | static int Pci_Error_Flag = 1; /* Set Retry Error on. */ |
72 | ||
73 | static struct pci_ops iSeries_pci_ops; | |
74 | ||
75 | /* | |
76 | * Table defines | |
77 | * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. | |
78 | */ | |
79 | #define IOMM_TABLE_MAX_ENTRIES 1024 | |
80 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | |
81 | #define BASE_IO_MEMORY 0xE000000000000000UL | |
82 | ||
83 | static unsigned long max_io_memory = 0xE000000000000000UL; | |
84 | static long current_iomm_table_entry; | |
85 | ||
86 | /* | |
87 | * Lookup Tables. | |
88 | */ | |
252e75a5 | 89 | static struct device_node **iomm_table; |
1da177e4 LT |
90 | static u8 *iobar_table; |
91 | ||
92 | /* | |
93 | * Static and Global variables | |
94 | */ | |
95 | static char *pci_io_text = "iSeries PCI I/O"; | |
96 | static DEFINE_SPINLOCK(iomm_table_lock); | |
97 | ||
98 | /* | |
99 | * iomm_table_initialize | |
100 | * | |
101 | * Allocates and initalizes the Address Translation Table and Bar | |
102 | * Tables to get them ready for use. Must be called before any | |
103 | * I/O space is handed out to the device BARs. | |
104 | */ | |
105 | static void iomm_table_initialize(void) | |
106 | { | |
107 | spin_lock(&iomm_table_lock); | |
108 | iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES, | |
109 | GFP_KERNEL); | |
110 | iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES, | |
111 | GFP_KERNEL); | |
112 | spin_unlock(&iomm_table_lock); | |
113 | if ((iomm_table == NULL) || (iobar_table == NULL)) | |
114 | panic("PCI: I/O tables allocation failed.\n"); | |
115 | } | |
116 | ||
117 | /* | |
118 | * iomm_table_allocate_entry | |
119 | * | |
120 | * Adds pci_dev entry in address translation table | |
121 | * | |
122 | * - Allocates the number of entries required in table base on BAR | |
123 | * size. | |
124 | * - Allocates starting at BASE_IO_MEMORY and increases. | |
125 | * - The size is round up to be a multiple of entry size. | |
126 | * - CurrentIndex is incremented to keep track of the last entry. | |
127 | * - Builds the resource entry for allocated BARs. | |
128 | */ | |
129 | static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |
130 | { | |
131 | struct resource *bar_res = &dev->resource[bar_num]; | |
132 | long bar_size = pci_resource_len(dev, bar_num); | |
133 | ||
134 | /* | |
135 | * No space to allocate, quick exit, skip Allocation. | |
136 | */ | |
137 | if (bar_size == 0) | |
138 | return; | |
139 | /* | |
140 | * Set Resource values. | |
141 | */ | |
142 | spin_lock(&iomm_table_lock); | |
143 | bar_res->name = pci_io_text; | |
144 | bar_res->start = | |
145 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; | |
146 | bar_res->start += BASE_IO_MEMORY; | |
147 | bar_res->end = bar_res->start + bar_size - 1; | |
148 | /* | |
149 | * Allocate the number of table entries needed for BAR. | |
150 | */ | |
151 | while (bar_size > 0 ) { | |
152 | iomm_table[current_iomm_table_entry] = dev->sysdata; | |
153 | iobar_table[current_iomm_table_entry] = bar_num; | |
154 | bar_size -= IOMM_TABLE_ENTRY_SIZE; | |
155 | ++current_iomm_table_entry; | |
156 | } | |
157 | max_io_memory = BASE_IO_MEMORY + | |
158 | (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry); | |
159 | spin_unlock(&iomm_table_lock); | |
160 | } | |
161 | ||
162 | /* | |
163 | * allocate_device_bars | |
164 | * | |
165 | * - Allocates ALL pci_dev BAR's and updates the resources with the | |
166 | * BAR value. BARS with zero length will have the resources | |
167 | * The HvCallPci_getBarParms is used to get the size of the BAR | |
168 | * space. It calls iomm_table_allocate_entry to allocate | |
169 | * each entry. | |
170 | * - Loops through The Bar resources(0 - 5) including the ROM | |
171 | * is resource(6). | |
172 | */ | |
173 | static void allocate_device_bars(struct pci_dev *dev) | |
174 | { | |
175 | struct resource *bar_res; | |
176 | int bar_num; | |
177 | ||
178 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) { | |
179 | bar_res = &dev->resource[bar_num]; | |
180 | iomm_table_allocate_entry(dev, bar_num); | |
d387899f | 181 | } |
1da177e4 LT |
182 | } |
183 | ||
184 | /* | |
185 | * Log error information to system console. | |
186 | * Filter out the device not there errors. | |
187 | * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx | |
188 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | |
189 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | |
190 | */ | |
191 | static void pci_Log_Error(char *Error_Text, int Bus, int SubBus, | |
192 | int AgentId, int HvRc) | |
193 | { | |
194 | if (HvRc == 0x0302) | |
195 | return; | |
196 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | |
197 | Error_Text, Bus, SubBus, AgentId, HvRc); | |
198 | } | |
199 | ||
200 | /* | |
201 | * build_device_node(u16 Bus, int SubBus, u8 DevFn) | |
202 | */ | |
252e75a5 | 203 | static struct device_node *build_device_node(HvBusNumber Bus, |
1da177e4 LT |
204 | HvSubBusNumber SubBus, int AgentId, int Function) |
205 | { | |
252e75a5 SR |
206 | struct device_node *node; |
207 | struct pci_dn *pdn; | |
1da177e4 LT |
208 | |
209 | PPCDBG(PPCDBG_BUSWALK, | |
210 | "-build_device_node 0x%02X.%02X.%02X Function: %02X\n", | |
211 | Bus, SubBus, AgentId, Function); | |
212 | ||
252e75a5 | 213 | node = kmalloc(sizeof(struct device_node), GFP_KERNEL); |
1da177e4 LT |
214 | if (node == NULL) |
215 | return NULL; | |
252e75a5 SR |
216 | memset(node, 0, sizeof(struct device_node)); |
217 | pdn = kzalloc(sizeof(*pdn), GFP_KERNEL); | |
218 | if (pdn == NULL) { | |
219 | kfree(node); | |
220 | return NULL; | |
221 | } | |
222 | node->data = pdn; | |
f255f0dd | 223 | pdn->node = node; |
76f9f87f | 224 | list_add_tail(&pdn->Device_List, &iSeries_Global_Device_List); |
1da177e4 | 225 | #if 0 |
252e75a5 | 226 | pdn->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32); |
1da177e4 | 227 | #endif |
252e75a5 SR |
228 | pdn->DsaAddr.DsaAddr = 0; |
229 | pdn->DsaAddr.Dsa.busNumber = Bus; | |
230 | pdn->DsaAddr.Dsa.subBusNumber = SubBus; | |
231 | pdn->DsaAddr.Dsa.deviceId = 0x10; | |
232 | pdn->devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function); | |
1da177e4 LT |
233 | return node; |
234 | } | |
235 | ||
236 | /* | |
237 | * unsigned long __init find_and_init_phbs(void) | |
238 | * | |
239 | * Description: | |
240 | * This function checks for all possible system PCI host bridges that connect | |
241 | * PCI buses. The system hypervisor is queried as to the guest partition | |
242 | * ownership status. A pci_controller is built for any bus which is partially | |
243 | * owned or fully owned by this guest partition. | |
244 | */ | |
245 | unsigned long __init find_and_init_phbs(void) | |
246 | { | |
247 | struct pci_controller *phb; | |
248 | HvBusNumber bus; | |
249 | ||
250 | PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n"); | |
251 | ||
252 | /* Check all possible buses. */ | |
253 | for (bus = 0; bus < 256; bus++) { | |
254 | int ret = HvCallXm_testBus(bus); | |
255 | if (ret == 0) { | |
256 | printk("bus %d appears to exist\n", bus); | |
257 | ||
258 | phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL); | |
259 | if (phb == NULL) | |
260 | return -ENOMEM; | |
3238e9c9 | 261 | pci_setup_pci_controller(phb); |
1da177e4 LT |
262 | |
263 | phb->pci_mem_offset = phb->local_number = bus; | |
264 | phb->first_busno = bus; | |
265 | phb->last_busno = bus; | |
266 | phb->ops = &iSeries_pci_ops; | |
267 | ||
268 | PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n", | |
269 | phb, bus); | |
270 | ||
271 | /* Find and connect the devices. */ | |
272 | scan_PHB_slots(phb); | |
273 | } | |
274 | /* | |
275 | * Check for Unexpected Return code, a clue that something | |
276 | * has gone wrong. | |
277 | */ | |
278 | else if (ret != 0x0301) | |
279 | printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X", | |
280 | bus, ret); | |
281 | } | |
282 | return 0; | |
283 | } | |
284 | ||
285 | /* | |
286 | * iSeries_pcibios_init | |
d387899f | 287 | * |
1da177e4 LT |
288 | * Chance to initialize and structures or variable before PCI Bus walk. |
289 | */ | |
290 | void iSeries_pcibios_init(void) | |
291 | { | |
d387899f | 292 | PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n"); |
1da177e4 LT |
293 | iomm_table_initialize(); |
294 | find_and_init_phbs(); | |
295 | io_page_mask = -1; | |
d387899f | 296 | PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n"); |
1da177e4 LT |
297 | } |
298 | ||
299 | /* | |
d387899f | 300 | * iSeries_pci_final_fixup(void) |
1da177e4 LT |
301 | */ |
302 | void __init iSeries_pci_final_fixup(void) | |
303 | { | |
304 | struct pci_dev *pdev = NULL; | |
252e75a5 | 305 | struct device_node *node; |
d387899f | 306 | int DeviceCount = 0; |
1da177e4 | 307 | |
d387899f | 308 | PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n"); |
1da177e4 LT |
309 | |
310 | /* Fix up at the device node and pci_dev relationship */ | |
311 | mf_display_src(0xC9000100); | |
312 | ||
313 | printk("pcibios_final_fixup\n"); | |
314 | for_each_pci_dev(pdev) { | |
315 | node = find_Device_Node(pdev->bus->number, pdev->devfn); | |
316 | printk("pci dev %p (%x.%x), node %p\n", pdev, | |
317 | pdev->bus->number, pdev->devfn, node); | |
318 | ||
319 | if (node != NULL) { | |
320 | ++DeviceCount; | |
321 | pdev->sysdata = (void *)node; | |
252e75a5 | 322 | PCI_DN(node)->pcidev = pdev; |
1da177e4 LT |
323 | PPCDBG(PPCDBG_BUSWALK, |
324 | "pdev 0x%p <==> DevNode 0x%p\n", | |
325 | pdev, node); | |
326 | allocate_device_bars(pdev); | |
061c063e | 327 | iSeries_Device_Information(pdev, DeviceCount); |
1da177e4 LT |
328 | iommu_devnode_init_iSeries(node); |
329 | } else | |
330 | printk("PCI: Device Tree not found for 0x%016lX\n", | |
331 | (unsigned long)pdev); | |
252e75a5 | 332 | pdev->irq = PCI_DN(node)->Irq; |
1da177e4 LT |
333 | } |
334 | iSeries_activate_IRQs(); | |
335 | mf_display_src(0xC9000200); | |
336 | } | |
337 | ||
338 | void pcibios_fixup_bus(struct pci_bus *PciBus) | |
339 | { | |
340 | PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n", | |
d387899f | 341 | PciBus->number); |
1da177e4 LT |
342 | } |
343 | ||
344 | void pcibios_fixup_resources(struct pci_dev *pdev) | |
345 | { | |
346 | PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev); | |
d387899f | 347 | } |
1da177e4 LT |
348 | |
349 | /* | |
d387899f | 350 | * Loop through each node function to find usable EADs bridges. |
1da177e4 LT |
351 | */ |
352 | static void scan_PHB_slots(struct pci_controller *Phb) | |
353 | { | |
354 | struct HvCallPci_DeviceInfo *DevInfo; | |
d387899f | 355 | HvBusNumber bus = Phb->local_number; /* System Bus */ |
1da177e4 LT |
356 | const HvSubBusNumber SubBus = 0; /* EADs is always 0. */ |
357 | int HvRc = 0; | |
d387899f | 358 | int IdSel; |
1da177e4 LT |
359 | const int MaxAgents = 8; |
360 | ||
361 | DevInfo = (struct HvCallPci_DeviceInfo*) | |
362 | kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL); | |
363 | if (DevInfo == NULL) | |
364 | return; | |
365 | ||
366 | /* | |
d387899f | 367 | * Probe for EADs Bridges |
1da177e4 LT |
368 | */ |
369 | for (IdSel = 1; IdSel < MaxAgents; ++IdSel) { | |
d387899f | 370 | HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel, |
1da177e4 LT |
371 | ISERIES_HV_ADDR(DevInfo), |
372 | sizeof(struct HvCallPci_DeviceInfo)); | |
373 | if (HvRc == 0) { | |
374 | if (DevInfo->deviceType == HvCallPci_NodeDevice) | |
375 | scan_EADS_bridge(bus, SubBus, IdSel); | |
376 | else | |
377 | printk("PCI: Invalid System Configuration(0x%02X)" | |
378 | " for bus 0x%02x id 0x%02x.\n", | |
379 | DevInfo->deviceType, bus, IdSel); | |
380 | } | |
381 | else | |
382 | pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc); | |
383 | } | |
384 | kfree(DevInfo); | |
385 | } | |
386 | ||
387 | static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus, | |
388 | int IdSel) | |
389 | { | |
390 | struct HvCallPci_BridgeInfo *BridgeInfo; | |
391 | HvAgentId AgentId; | |
392 | int Function; | |
393 | int HvRc; | |
394 | ||
395 | BridgeInfo = (struct HvCallPci_BridgeInfo *) | |
396 | kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL); | |
397 | if (BridgeInfo == NULL) | |
398 | return; | |
399 | ||
400 | /* Note: hvSubBus and irq is always be 0 at this level! */ | |
401 | for (Function = 0; Function < 8; ++Function) { | |
d387899f | 402 | AgentId = ISERIES_PCI_AGENTID(IdSel, Function); |
1da177e4 | 403 | HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0); |
d387899f | 404 | if (HvRc == 0) { |
1da177e4 LT |
405 | printk("found device at bus %d idsel %d func %d (AgentId %x)\n", |
406 | bus, IdSel, Function, AgentId); | |
d387899f | 407 | /* Connect EADs: 0x18.00.12 = 0x00 */ |
1da177e4 LT |
408 | PPCDBG(PPCDBG_BUSWALK, |
409 | "PCI:Connect EADs: 0x%02X.%02X.%02X\n", | |
410 | bus, SubBus, AgentId); | |
d387899f | 411 | HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId, |
1da177e4 LT |
412 | ISERIES_HV_ADDR(BridgeInfo), |
413 | sizeof(struct HvCallPci_BridgeInfo)); | |
d387899f | 414 | if (HvRc == 0) { |
1da177e4 LT |
415 | printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n", |
416 | BridgeInfo->busUnitInfo.deviceType, | |
417 | BridgeInfo->subBusNumber, | |
418 | BridgeInfo->maxAgents, | |
419 | BridgeInfo->maxSubBusNumber, | |
420 | BridgeInfo->logicalSlotNumber); | |
421 | PPCDBG(PPCDBG_BUSWALK, | |
422 | "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n", | |
423 | BridgeInfo->busUnitInfo.deviceType, | |
424 | BridgeInfo->subBusNumber, | |
425 | BridgeInfo->maxAgents, | |
426 | BridgeInfo->maxSubBusNumber, | |
427 | BridgeInfo->logicalSlotNumber); | |
428 | ||
429 | if (BridgeInfo->busUnitInfo.deviceType == | |
430 | HvCallPci_BridgeDevice) { | |
431 | /* Scan_Bridge_Slot...: 0x18.00.12 */ | |
432 | scan_bridge_slot(bus, BridgeInfo); | |
433 | } else | |
434 | printk("PCI: Invalid Bridge Configuration(0x%02X)", | |
435 | BridgeInfo->busUnitInfo.deviceType); | |
436 | } | |
d387899f | 437 | } else if (HvRc != 0x000B) |
1da177e4 LT |
438 | pci_Log_Error("EADs Connect", |
439 | bus, SubBus, AgentId, HvRc); | |
440 | } | |
441 | kfree(BridgeInfo); | |
442 | } | |
443 | ||
444 | /* | |
445 | * This assumes that the node slot is always on the primary bus! | |
446 | */ | |
447 | static int scan_bridge_slot(HvBusNumber Bus, | |
448 | struct HvCallPci_BridgeInfo *BridgeInfo) | |
449 | { | |
252e75a5 | 450 | struct device_node *node; |
1da177e4 LT |
451 | HvSubBusNumber SubBus = BridgeInfo->subBusNumber; |
452 | u16 VendorId = 0; | |
453 | int HvRc = 0; | |
454 | u8 Irq = 0; | |
455 | int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus); | |
456 | int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus); | |
457 | HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function); | |
458 | ||
459 | /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */ | |
d387899f | 460 | Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel); |
1da177e4 LT |
461 | PPCDBG(PPCDBG_BUSWALK, |
462 | "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n", | |
463 | Bus, 0, EADsIdSel, Irq); | |
464 | ||
465 | /* | |
d387899f | 466 | * Connect all functions of any device found. |
1da177e4 | 467 | */ |
d387899f SR |
468 | for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) { |
469 | for (Function = 0; Function < 8; ++Function) { | |
1da177e4 LT |
470 | HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function); |
471 | HvRc = HvCallXm_connectBusUnit(Bus, SubBus, | |
472 | AgentId, Irq); | |
473 | if (HvRc != 0) { | |
474 | pci_Log_Error("Connect Bus Unit", | |
475 | Bus, SubBus, AgentId, HvRc); | |
476 | continue; | |
477 | } | |
478 | ||
479 | HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId, | |
480 | PCI_VENDOR_ID, &VendorId); | |
481 | if (HvRc != 0) { | |
482 | pci_Log_Error("Read Vendor", | |
483 | Bus, SubBus, AgentId, HvRc); | |
484 | continue; | |
485 | } | |
486 | printk("read vendor ID: %x\n", VendorId); | |
487 | ||
488 | /* FoundDevice: 0x18.28.10 = 0x12AE */ | |
489 | PPCDBG(PPCDBG_BUSWALK, | |
490 | "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n", | |
491 | Bus, SubBus, AgentId, VendorId, Irq); | |
492 | HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId, | |
d387899f | 493 | PCI_INTERRUPT_LINE, Irq); |
1da177e4 LT |
494 | if (HvRc != 0) |
495 | pci_Log_Error("PciCfgStore Irq Failed!", | |
496 | Bus, SubBus, AgentId, HvRc); | |
497 | ||
498 | ++DeviceCount; | |
499 | node = build_device_node(Bus, SubBus, EADsIdSel, Function); | |
252e75a5 SR |
500 | PCI_DN(node)->Irq = Irq; |
501 | PCI_DN(node)->LogicalSlot = BridgeInfo->logicalSlotNumber; | |
1da177e4 LT |
502 | |
503 | } /* for (Function = 0; Function < 8; ++Function) */ | |
504 | } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */ | |
505 | return HvRc; | |
506 | } | |
507 | ||
508 | /* | |
509 | * I/0 Memory copy MUST use mmio commands on iSeries | |
510 | * To do; For performance, include the hv call directly | |
511 | */ | |
512 | void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count) | |
513 | { | |
514 | u8 ByteValue = c; | |
515 | long NumberOfBytes = Count; | |
516 | ||
517 | while (NumberOfBytes > 0) { | |
518 | iSeries_Write_Byte(ByteValue, dest++); | |
519 | -- NumberOfBytes; | |
520 | } | |
521 | } | |
522 | EXPORT_SYMBOL(iSeries_memset_io); | |
523 | ||
524 | void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count) | |
525 | { | |
526 | char *src = source; | |
527 | long NumberOfBytes = count; | |
528 | ||
529 | while (NumberOfBytes > 0) { | |
530 | iSeries_Write_Byte(*src++, dest++); | |
531 | -- NumberOfBytes; | |
532 | } | |
533 | } | |
534 | EXPORT_SYMBOL(iSeries_memcpy_toio); | |
535 | ||
536 | void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count) | |
537 | { | |
538 | char *dst = dest; | |
539 | long NumberOfBytes = count; | |
540 | ||
541 | while (NumberOfBytes > 0) { | |
542 | *dst++ = iSeries_Read_Byte(src++); | |
543 | -- NumberOfBytes; | |
544 | } | |
545 | } | |
546 | EXPORT_SYMBOL(iSeries_memcpy_fromio); | |
547 | ||
548 | /* | |
549 | * Look down the chain to find the matching Device Device | |
550 | */ | |
252e75a5 | 551 | static struct device_node *find_Device_Node(int bus, int devfn) |
1da177e4 | 552 | { |
76f9f87f | 553 | struct pci_dn *pdn; |
1da177e4 | 554 | |
76f9f87f PM |
555 | list_for_each_entry(pdn, &iSeries_Global_Device_List, Device_List) { |
556 | if ((bus == pdn->DsaAddr.Dsa.busNumber) && | |
557 | (devfn == pdn->devfn)) | |
558 | return pdn->node; | |
1da177e4 LT |
559 | } |
560 | return NULL; | |
561 | } | |
562 | ||
563 | #if 0 | |
564 | /* | |
565 | * Returns the device node for the passed pci_dev | |
566 | * Sanity Check Node PciDev to passed pci_dev | |
567 | * If none is found, returns a NULL which the client must handle. | |
568 | */ | |
252e75a5 | 569 | static struct device_node *get_Device_Node(struct pci_dev *pdev) |
1da177e4 | 570 | { |
252e75a5 | 571 | struct device_node *node; |
1da177e4 LT |
572 | |
573 | node = pdev->sysdata; | |
252e75a5 | 574 | if (node == NULL || PCI_DN(node)->pcidev != pdev) |
1da177e4 LT |
575 | node = find_Device_Node(pdev->bus->number, pdev->devfn); |
576 | return node; | |
577 | } | |
578 | #endif | |
579 | ||
580 | /* | |
581 | * Config space read and write functions. | |
582 | * For now at least, we look for the device node for the bus and devfn | |
583 | * that we are asked to access. It may be possible to translate the devfn | |
584 | * to a subbus and deviceid more directly. | |
585 | */ | |
586 | static u64 hv_cfg_read_func[4] = { | |
587 | HvCallPciConfigLoad8, HvCallPciConfigLoad16, | |
588 | HvCallPciConfigLoad32, HvCallPciConfigLoad32 | |
589 | }; | |
590 | ||
591 | static u64 hv_cfg_write_func[4] = { | |
592 | HvCallPciConfigStore8, HvCallPciConfigStore16, | |
593 | HvCallPciConfigStore32, HvCallPciConfigStore32 | |
594 | }; | |
595 | ||
596 | /* | |
597 | * Read PCI config space | |
598 | */ | |
599 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
600 | int offset, int size, u32 *val) | |
601 | { | |
252e75a5 | 602 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
603 | u64 fn; |
604 | struct HvCallPci_LoadReturn ret; | |
605 | ||
606 | if (node == NULL) | |
607 | return PCIBIOS_DEVICE_NOT_FOUND; | |
608 | if (offset > 255) { | |
609 | *val = ~0; | |
610 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
611 | } | |
612 | ||
613 | fn = hv_cfg_read_func[(size - 1) & 3]; | |
252e75a5 | 614 | HvCall3Ret16(fn, &ret, PCI_DN(node)->DsaAddr.DsaAddr, offset, 0); |
1da177e4 LT |
615 | |
616 | if (ret.rc != 0) { | |
617 | *val = ~0; | |
618 | return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ | |
619 | } | |
620 | ||
621 | *val = ret.value; | |
622 | return 0; | |
623 | } | |
624 | ||
625 | /* | |
626 | * Write PCI config space | |
627 | */ | |
628 | ||
629 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
630 | int offset, int size, u32 val) | |
631 | { | |
252e75a5 | 632 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
633 | u64 fn; |
634 | u64 ret; | |
635 | ||
636 | if (node == NULL) | |
637 | return PCIBIOS_DEVICE_NOT_FOUND; | |
638 | if (offset > 255) | |
639 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
640 | ||
641 | fn = hv_cfg_write_func[(size - 1) & 3]; | |
252e75a5 | 642 | ret = HvCall4(fn, PCI_DN(node)->DsaAddr.DsaAddr, offset, val, 0); |
1da177e4 LT |
643 | |
644 | if (ret != 0) | |
645 | return PCIBIOS_DEVICE_NOT_FOUND; | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
650 | static struct pci_ops iSeries_pci_ops = { | |
651 | .read = iSeries_pci_read_config, | |
652 | .write = iSeries_pci_write_config | |
653 | }; | |
654 | ||
655 | /* | |
656 | * Check Return Code | |
657 | * -> On Failure, print and log information. | |
658 | * Increment Retry Count, if exceeds max, panic partition. | |
1da177e4 LT |
659 | * |
660 | * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 | |
661 | * PCI: Device 23.90 ReadL Retry( 1) | |
662 | * PCI: Device 23.90 ReadL Retry Successful(1) | |
663 | */ | |
252e75a5 | 664 | static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, |
a2ebaf25 | 665 | int *retry, u64 ret) |
1da177e4 LT |
666 | { |
667 | if (ret != 0) { | |
252e75a5 SR |
668 | struct pci_dn *pdn = PCI_DN(DevNode); |
669 | ||
1da177e4 | 670 | ++Pci_Error_Count; |
a2ebaf25 | 671 | (*retry)++; |
1da177e4 | 672 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
252e75a5 | 673 | TextHdr, pdn->DsaAddr.Dsa.busNumber, pdn->devfn, |
a2ebaf25 | 674 | *retry, (int)ret); |
1da177e4 LT |
675 | /* |
676 | * Bump the retry and check for retry count exceeded. | |
677 | * If, Exceeded, panic the system. | |
678 | */ | |
a2ebaf25 | 679 | if (((*retry) > Pci_Retry_Max) && |
1da177e4 LT |
680 | (Pci_Error_Flag > 0)) { |
681 | mf_display_src(0xB6000103); | |
a2ebaf25 | 682 | panic_timeout = 0; |
1da177e4 LT |
683 | panic("PCI: Hardware I/O Error, SRC B6000103, " |
684 | "Automatic Reboot Disabled.\n"); | |
685 | } | |
686 | return -1; /* Retry Try */ | |
687 | } | |
a2ebaf25 | 688 | return 0; |
1da177e4 LT |
689 | } |
690 | ||
691 | /* | |
692 | * Translate the I/O Address into a device node, bar, and bar offset. | |
693 | * Note: Make sure the passed variable end up on the stack to avoid | |
694 | * the exposure of being device global. | |
695 | */ | |
252e75a5 | 696 | static inline struct device_node *xlate_iomm_address( |
1da177e4 LT |
697 | const volatile void __iomem *IoAddress, |
698 | u64 *dsaptr, u64 *BarOffsetPtr) | |
699 | { | |
700 | unsigned long OrigIoAddr; | |
701 | unsigned long BaseIoAddr; | |
702 | unsigned long TableIndex; | |
252e75a5 | 703 | struct device_node *DevNode; |
1da177e4 LT |
704 | |
705 | OrigIoAddr = (unsigned long __force)IoAddress; | |
706 | if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory)) | |
707 | return NULL; | |
708 | BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY; | |
709 | TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE; | |
710 | DevNode = iomm_table[TableIndex]; | |
711 | ||
712 | if (DevNode != NULL) { | |
713 | int barnum = iobar_table[TableIndex]; | |
252e75a5 | 714 | *dsaptr = PCI_DN(DevNode)->DsaAddr.DsaAddr | (barnum << 24); |
1da177e4 LT |
715 | *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE; |
716 | } else | |
717 | panic("PCI: Invalid PCI IoAddress detected!\n"); | |
718 | return DevNode; | |
719 | } | |
720 | ||
721 | /* | |
722 | * Read MM I/O Instructions for the iSeries | |
723 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | |
724 | * else, data is returned in big Endian format. | |
725 | * | |
726 | * iSeries_Read_Byte = Read Byte ( 8 bit) | |
727 | * iSeries_Read_Word = Read Word (16 bit) | |
728 | * iSeries_Read_Long = Read Long (32 bit) | |
729 | */ | |
730 | u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) | |
731 | { | |
732 | u64 BarOffset; | |
733 | u64 dsa; | |
a2ebaf25 | 734 | int retry = 0; |
1da177e4 | 735 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 736 | struct device_node *DevNode = |
1da177e4 LT |
737 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
738 | ||
739 | if (DevNode == NULL) { | |
740 | static unsigned long last_jiffies; | |
741 | static int num_printed; | |
742 | ||
743 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
744 | last_jiffies = jiffies; | |
745 | num_printed = 0; | |
746 | } | |
747 | if (num_printed++ < 10) | |
748 | printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress); | |
749 | return 0xff; | |
750 | } | |
751 | do { | |
752 | ++Pci_Io_Read_Count; | |
753 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); | |
a2ebaf25 | 754 | } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
755 | |
756 | return (u8)ret.value; | |
757 | } | |
758 | EXPORT_SYMBOL(iSeries_Read_Byte); | |
759 | ||
760 | u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) | |
761 | { | |
762 | u64 BarOffset; | |
763 | u64 dsa; | |
a2ebaf25 | 764 | int retry = 0; |
1da177e4 | 765 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 766 | struct device_node *DevNode = |
1da177e4 LT |
767 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
768 | ||
769 | if (DevNode == NULL) { | |
770 | static unsigned long last_jiffies; | |
771 | static int num_printed; | |
772 | ||
773 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
774 | last_jiffies = jiffies; | |
775 | num_printed = 0; | |
776 | } | |
777 | if (num_printed++ < 10) | |
778 | printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress); | |
779 | return 0xffff; | |
780 | } | |
781 | do { | |
782 | ++Pci_Io_Read_Count; | |
783 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, | |
784 | BarOffset, 0); | |
a2ebaf25 | 785 | } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
786 | |
787 | return swab16((u16)ret.value); | |
788 | } | |
789 | EXPORT_SYMBOL(iSeries_Read_Word); | |
790 | ||
791 | u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) | |
792 | { | |
793 | u64 BarOffset; | |
794 | u64 dsa; | |
a2ebaf25 | 795 | int retry = 0; |
1da177e4 | 796 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 797 | struct device_node *DevNode = |
1da177e4 LT |
798 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
799 | ||
800 | if (DevNode == NULL) { | |
801 | static unsigned long last_jiffies; | |
802 | static int num_printed; | |
803 | ||
804 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
805 | last_jiffies = jiffies; | |
806 | num_printed = 0; | |
807 | } | |
808 | if (num_printed++ < 10) | |
809 | printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress); | |
810 | return 0xffffffff; | |
811 | } | |
812 | do { | |
813 | ++Pci_Io_Read_Count; | |
814 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, | |
815 | BarOffset, 0); | |
a2ebaf25 | 816 | } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
817 | |
818 | return swab32((u32)ret.value); | |
819 | } | |
820 | EXPORT_SYMBOL(iSeries_Read_Long); | |
821 | ||
822 | /* | |
823 | * Write MM I/O Instructions for the iSeries | |
824 | * | |
825 | * iSeries_Write_Byte = Write Byte (8 bit) | |
826 | * iSeries_Write_Word = Write Word(16 bit) | |
827 | * iSeries_Write_Long = Write Long(32 bit) | |
828 | */ | |
829 | void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) | |
830 | { | |
831 | u64 BarOffset; | |
832 | u64 dsa; | |
a2ebaf25 | 833 | int retry = 0; |
1da177e4 | 834 | u64 rc; |
252e75a5 | 835 | struct device_node *DevNode = |
1da177e4 LT |
836 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
837 | ||
838 | if (DevNode == NULL) { | |
839 | static unsigned long last_jiffies; | |
840 | static int num_printed; | |
841 | ||
842 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
843 | last_jiffies = jiffies; | |
844 | num_printed = 0; | |
845 | } | |
846 | if (num_printed++ < 10) | |
847 | printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress); | |
848 | return; | |
849 | } | |
850 | do { | |
851 | ++Pci_Io_Write_Count; | |
852 | rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); | |
a2ebaf25 | 853 | } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); |
1da177e4 LT |
854 | } |
855 | EXPORT_SYMBOL(iSeries_Write_Byte); | |
856 | ||
857 | void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) | |
858 | { | |
859 | u64 BarOffset; | |
860 | u64 dsa; | |
a2ebaf25 | 861 | int retry = 0; |
1da177e4 | 862 | u64 rc; |
252e75a5 | 863 | struct device_node *DevNode = |
1da177e4 LT |
864 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
865 | ||
866 | if (DevNode == NULL) { | |
867 | static unsigned long last_jiffies; | |
868 | static int num_printed; | |
869 | ||
870 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
871 | last_jiffies = jiffies; | |
872 | num_printed = 0; | |
873 | } | |
874 | if (num_printed++ < 10) | |
875 | printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress); | |
876 | return; | |
877 | } | |
878 | do { | |
879 | ++Pci_Io_Write_Count; | |
880 | rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0); | |
a2ebaf25 | 881 | } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); |
1da177e4 LT |
882 | } |
883 | EXPORT_SYMBOL(iSeries_Write_Word); | |
884 | ||
885 | void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) | |
886 | { | |
887 | u64 BarOffset; | |
888 | u64 dsa; | |
a2ebaf25 | 889 | int retry = 0; |
1da177e4 | 890 | u64 rc; |
252e75a5 | 891 | struct device_node *DevNode = |
1da177e4 LT |
892 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
893 | ||
894 | if (DevNode == NULL) { | |
895 | static unsigned long last_jiffies; | |
896 | static int num_printed; | |
897 | ||
898 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
899 | last_jiffies = jiffies; | |
900 | num_printed = 0; | |
901 | } | |
902 | if (num_printed++ < 10) | |
903 | printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress); | |
904 | return; | |
905 | } | |
906 | do { | |
907 | ++Pci_Io_Write_Count; | |
908 | rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0); | |
a2ebaf25 | 909 | } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); |
1da177e4 LT |
910 | } |
911 | EXPORT_SYMBOL(iSeries_Write_Long); |