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Commit | Line | Data |
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bbf45ba5 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2007 | |
16 | * | |
17 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
18 | */ | |
19 | ||
20 | #include <linux/jiffies.h> | |
544c6761 | 21 | #include <linux/hrtimer.h> |
bbf45ba5 HB |
22 | #include <linux/types.h> |
23 | #include <linux/string.h> | |
24 | #include <linux/kvm_host.h> | |
25 | ||
75f74f0d | 26 | #include <asm/reg.h> |
bbf45ba5 HB |
27 | #include <asm/time.h> |
28 | #include <asm/byteorder.h> | |
29 | #include <asm/kvm_ppc.h> | |
c381a043 | 30 | #include <asm/disassemble.h> |
73e75b41 | 31 | #include "timing.h" |
46f43c6e | 32 | #include "trace.h" |
bbf45ba5 | 33 | |
cea5d8c9 | 34 | #define OP_TRAP 3 |
513579e3 | 35 | #define OP_TRAP_64 2 |
cea5d8c9 HB |
36 | |
37 | #define OP_31_XOP_LWZX 23 | |
38 | #define OP_31_XOP_LBZX 87 | |
39 | #define OP_31_XOP_STWX 151 | |
40 | #define OP_31_XOP_STBX 215 | |
1c85e733 | 41 | #define OP_31_XOP_LBZUX 119 |
cea5d8c9 HB |
42 | #define OP_31_XOP_STBUX 247 |
43 | #define OP_31_XOP_LHZX 279 | |
44 | #define OP_31_XOP_LHZUX 311 | |
45 | #define OP_31_XOP_MFSPR 339 | |
1c85e733 | 46 | #define OP_31_XOP_LHAX 343 |
cea5d8c9 HB |
47 | #define OP_31_XOP_STHX 407 |
48 | #define OP_31_XOP_STHUX 439 | |
49 | #define OP_31_XOP_MTSPR 467 | |
50 | #define OP_31_XOP_DCBI 470 | |
51 | #define OP_31_XOP_LWBRX 534 | |
52 | #define OP_31_XOP_TLBSYNC 566 | |
53 | #define OP_31_XOP_STWBRX 662 | |
54 | #define OP_31_XOP_LHBRX 790 | |
55 | #define OP_31_XOP_STHBRX 918 | |
56 | ||
57 | #define OP_LWZ 32 | |
58 | #define OP_LWZU 33 | |
59 | #define OP_LBZ 34 | |
60 | #define OP_LBZU 35 | |
61 | #define OP_STW 36 | |
62 | #define OP_STWU 37 | |
63 | #define OP_STB 38 | |
64 | #define OP_STBU 39 | |
65 | #define OP_LHZ 40 | |
66 | #define OP_LHZU 41 | |
3587d534 AG |
67 | #define OP_LHA 42 |
68 | #define OP_LHAU 43 | |
cea5d8c9 HB |
69 | #define OP_STH 44 |
70 | #define OP_STHU 45 | |
71 | ||
00c3a37c | 72 | #ifdef CONFIG_PPC_BOOK3S |
513579e3 AG |
73 | static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu) |
74 | { | |
75 | return 1; | |
76 | } | |
77 | #else | |
78 | static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu) | |
79 | { | |
80 | return vcpu->arch.tcr & TCR_DIE; | |
81 | } | |
82 | #endif | |
83 | ||
75f74f0d | 84 | void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) |
bbf45ba5 | 85 | { |
544c6761 | 86 | unsigned long dec_nsec; |
9a7a9b09 | 87 | |
544c6761 | 88 | pr_debug("mtDEC: %x\n", vcpu->arch.dec); |
00c3a37c | 89 | #ifdef CONFIG_PPC_BOOK3S |
7706664d AG |
90 | /* mtdec lowers the interrupt line when positive. */ |
91 | kvmppc_core_dequeue_dec(vcpu); | |
92 | ||
513579e3 AG |
93 | /* POWER4+ triggers a dec interrupt if the value is < 0 */ |
94 | if (vcpu->arch.dec & 0x80000000) { | |
544c6761 | 95 | hrtimer_try_to_cancel(&vcpu->arch.dec_timer); |
513579e3 AG |
96 | kvmppc_core_queue_dec(vcpu); |
97 | return; | |
98 | } | |
99 | #endif | |
100 | if (kvmppc_dec_enabled(vcpu)) { | |
bbf45ba5 HB |
101 | /* The decrementer ticks at the same rate as the timebase, so |
102 | * that's how we convert the guest DEC value to the number of | |
103 | * host ticks. */ | |
bbf45ba5 | 104 | |
544c6761 AG |
105 | hrtimer_try_to_cancel(&vcpu->arch.dec_timer); |
106 | dec_nsec = vcpu->arch.dec; | |
107 | dec_nsec *= 1000; | |
108 | dec_nsec /= tb_ticks_per_usec; | |
109 | hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec), | |
110 | HRTIMER_MODE_REL); | |
513579e3 | 111 | vcpu->arch.dec_jiffies = get_tb(); |
bbf45ba5 | 112 | } else { |
544c6761 | 113 | hrtimer_try_to_cancel(&vcpu->arch.dec_timer); |
bbf45ba5 HB |
114 | } |
115 | } | |
116 | ||
bbf45ba5 HB |
117 | /* XXX to do: |
118 | * lhax | |
119 | * lhaux | |
120 | * lswx | |
121 | * lswi | |
122 | * stswx | |
123 | * stswi | |
124 | * lha | |
125 | * lhau | |
126 | * lmw | |
127 | * stmw | |
128 | * | |
129 | * XXX is_bigendian should depend on MMU mapping or MSR[LE] | |
130 | */ | |
75f74f0d HB |
131 | /* XXX Should probably auto-generate instruction decoding for a particular core |
132 | * from opcode tables in the future. */ | |
bbf45ba5 HB |
133 | int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) |
134 | { | |
c7f38f46 | 135 | u32 inst = kvmppc_get_last_inst(vcpu); |
bbf45ba5 HB |
136 | u32 ea; |
137 | int ra; | |
138 | int rb; | |
bbf45ba5 HB |
139 | int rs; |
140 | int rt; | |
141 | int sprn; | |
bbf45ba5 HB |
142 | enum emulation_result emulated = EMULATE_DONE; |
143 | int advance = 1; | |
144 | ||
73e75b41 HB |
145 | /* this default type might be overwritten by subcategories */ |
146 | kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS); | |
147 | ||
689fd14a | 148 | pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); |
513579e3 | 149 | |
bbf45ba5 | 150 | switch (get_op(inst)) { |
cea5d8c9 | 151 | case OP_TRAP: |
00c3a37c | 152 | #ifdef CONFIG_PPC_BOOK3S |
513579e3 | 153 | case OP_TRAP_64: |
daf5e271 | 154 | kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); |
513579e3 | 155 | #else |
daf5e271 | 156 | kvmppc_core_queue_program(vcpu, vcpu->arch.esr | ESR_PTR); |
513579e3 | 157 | #endif |
bbf45ba5 HB |
158 | advance = 0; |
159 | break; | |
160 | ||
bbf45ba5 HB |
161 | case 31: |
162 | switch (get_xop(inst)) { | |
163 | ||
cea5d8c9 | 164 | case OP_31_XOP_LWZX: |
ac3cd34e HB |
165 | rt = get_rt(inst); |
166 | emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); | |
167 | break; | |
168 | ||
cea5d8c9 | 169 | case OP_31_XOP_LBZX: |
bbf45ba5 HB |
170 | rt = get_rt(inst); |
171 | emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); | |
172 | break; | |
173 | ||
1c85e733 AG |
174 | case OP_31_XOP_LBZUX: |
175 | rt = get_rt(inst); | |
176 | ra = get_ra(inst); | |
177 | rb = get_rb(inst); | |
178 | ||
179 | ea = kvmppc_get_gpr(vcpu, rb); | |
180 | if (ra) | |
181 | ea += kvmppc_get_gpr(vcpu, ra); | |
182 | ||
183 | emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); | |
184 | kvmppc_set_gpr(vcpu, ra, ea); | |
185 | break; | |
186 | ||
cea5d8c9 | 187 | case OP_31_XOP_STWX: |
ac3cd34e HB |
188 | rs = get_rs(inst); |
189 | emulated = kvmppc_handle_store(run, vcpu, | |
8e5b26b5 | 190 | kvmppc_get_gpr(vcpu, rs), |
ac3cd34e HB |
191 | 4, 1); |
192 | break; | |
193 | ||
cea5d8c9 | 194 | case OP_31_XOP_STBX: |
bbf45ba5 HB |
195 | rs = get_rs(inst); |
196 | emulated = kvmppc_handle_store(run, vcpu, | |
8e5b26b5 | 197 | kvmppc_get_gpr(vcpu, rs), |
bbf45ba5 HB |
198 | 1, 1); |
199 | break; | |
200 | ||
cea5d8c9 | 201 | case OP_31_XOP_STBUX: |
bbf45ba5 HB |
202 | rs = get_rs(inst); |
203 | ra = get_ra(inst); | |
204 | rb = get_rb(inst); | |
205 | ||
8e5b26b5 | 206 | ea = kvmppc_get_gpr(vcpu, rb); |
bbf45ba5 | 207 | if (ra) |
8e5b26b5 | 208 | ea += kvmppc_get_gpr(vcpu, ra); |
bbf45ba5 HB |
209 | |
210 | emulated = kvmppc_handle_store(run, vcpu, | |
8e5b26b5 | 211 | kvmppc_get_gpr(vcpu, rs), |
bbf45ba5 | 212 | 1, 1); |
8e5b26b5 | 213 | kvmppc_set_gpr(vcpu, rs, ea); |
bbf45ba5 HB |
214 | break; |
215 | ||
1c85e733 AG |
216 | case OP_31_XOP_LHAX: |
217 | rt = get_rt(inst); | |
218 | emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); | |
219 | break; | |
220 | ||
cea5d8c9 | 221 | case OP_31_XOP_LHZX: |
bbf45ba5 HB |
222 | rt = get_rt(inst); |
223 | emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); | |
224 | break; | |
225 | ||
cea5d8c9 | 226 | case OP_31_XOP_LHZUX: |
bbf45ba5 HB |
227 | rt = get_rt(inst); |
228 | ra = get_ra(inst); | |
229 | rb = get_rb(inst); | |
230 | ||
8e5b26b5 | 231 | ea = kvmppc_get_gpr(vcpu, rb); |
bbf45ba5 | 232 | if (ra) |
8e5b26b5 | 233 | ea += kvmppc_get_gpr(vcpu, ra); |
bbf45ba5 HB |
234 | |
235 | emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); | |
8e5b26b5 | 236 | kvmppc_set_gpr(vcpu, ra, ea); |
bbf45ba5 HB |
237 | break; |
238 | ||
cea5d8c9 | 239 | case OP_31_XOP_MFSPR: |
bbf45ba5 HB |
240 | sprn = get_sprn(inst); |
241 | rt = get_rt(inst); | |
242 | ||
243 | switch (sprn) { | |
244 | case SPRN_SRR0: | |
de7906c3 AG |
245 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->srr0); |
246 | break; | |
bbf45ba5 | 247 | case SPRN_SRR1: |
de7906c3 AG |
248 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->srr1); |
249 | break; | |
bbf45ba5 | 250 | case SPRN_PVR: |
8e5b26b5 | 251 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break; |
06579dd9 | 252 | case SPRN_PIR: |
8e5b26b5 | 253 | kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break; |
513579e3 | 254 | case SPRN_MSSSR0: |
8e5b26b5 | 255 | kvmppc_set_gpr(vcpu, rt, 0); break; |
bbf45ba5 HB |
256 | |
257 | /* Note: mftb and TBRL/TBWL are user-accessible, so | |
258 | * the guest can always access the real TB anyways. | |
259 | * In fact, we probably will never see these traps. */ | |
260 | case SPRN_TBWL: | |
8e5b26b5 | 261 | kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break; |
bbf45ba5 | 262 | case SPRN_TBWU: |
8e5b26b5 | 263 | kvmppc_set_gpr(vcpu, rt, get_tb()); break; |
bbf45ba5 HB |
264 | |
265 | case SPRN_SPRG0: | |
a73a9599 AG |
266 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg0); |
267 | break; | |
bbf45ba5 | 268 | case SPRN_SPRG1: |
a73a9599 AG |
269 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg1); |
270 | break; | |
bbf45ba5 | 271 | case SPRN_SPRG2: |
a73a9599 AG |
272 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg2); |
273 | break; | |
bbf45ba5 | 274 | case SPRN_SPRG3: |
a73a9599 AG |
275 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg3); |
276 | break; | |
bbf45ba5 HB |
277 | /* Note: SPRG4-7 are user-readable, so we don't get |
278 | * a trap. */ | |
279 | ||
9a7a9b09 AG |
280 | case SPRN_DEC: |
281 | { | |
513579e3 | 282 | u64 jd = get_tb() - vcpu->arch.dec_jiffies; |
8e5b26b5 | 283 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.dec - jd); |
689fd14a | 284 | pr_debug("mfDEC: %x - %llx = %lx\n", |
8e5b26b5 AG |
285 | vcpu->arch.dec, jd, |
286 | kvmppc_get_gpr(vcpu, rt)); | |
9a7a9b09 AG |
287 | break; |
288 | } | |
bbf45ba5 | 289 | default: |
75f74f0d HB |
290 | emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt); |
291 | if (emulated == EMULATE_FAIL) { | |
292 | printk("mfspr: unknown spr %x\n", sprn); | |
8e5b26b5 | 293 | kvmppc_set_gpr(vcpu, rt, 0); |
75f74f0d | 294 | } |
bbf45ba5 HB |
295 | break; |
296 | } | |
297 | break; | |
298 | ||
cea5d8c9 | 299 | case OP_31_XOP_STHX: |
bbf45ba5 HB |
300 | rs = get_rs(inst); |
301 | ra = get_ra(inst); | |
302 | rb = get_rb(inst); | |
303 | ||
304 | emulated = kvmppc_handle_store(run, vcpu, | |
8e5b26b5 | 305 | kvmppc_get_gpr(vcpu, rs), |
bbf45ba5 HB |
306 | 2, 1); |
307 | break; | |
308 | ||
cea5d8c9 | 309 | case OP_31_XOP_STHUX: |
bbf45ba5 HB |
310 | rs = get_rs(inst); |
311 | ra = get_ra(inst); | |
312 | rb = get_rb(inst); | |
313 | ||
8e5b26b5 | 314 | ea = kvmppc_get_gpr(vcpu, rb); |
bbf45ba5 | 315 | if (ra) |
8e5b26b5 | 316 | ea += kvmppc_get_gpr(vcpu, ra); |
bbf45ba5 HB |
317 | |
318 | emulated = kvmppc_handle_store(run, vcpu, | |
8e5b26b5 | 319 | kvmppc_get_gpr(vcpu, rs), |
bbf45ba5 | 320 | 2, 1); |
8e5b26b5 | 321 | kvmppc_set_gpr(vcpu, ra, ea); |
bbf45ba5 HB |
322 | break; |
323 | ||
cea5d8c9 | 324 | case OP_31_XOP_MTSPR: |
bbf45ba5 HB |
325 | sprn = get_sprn(inst); |
326 | rs = get_rs(inst); | |
327 | switch (sprn) { | |
328 | case SPRN_SRR0: | |
de7906c3 AG |
329 | vcpu->arch.shared->srr0 = kvmppc_get_gpr(vcpu, rs); |
330 | break; | |
bbf45ba5 | 331 | case SPRN_SRR1: |
de7906c3 AG |
332 | vcpu->arch.shared->srr1 = kvmppc_get_gpr(vcpu, rs); |
333 | break; | |
bbf45ba5 HB |
334 | |
335 | /* XXX We need to context-switch the timebase for | |
336 | * watchdog and FIT. */ | |
337 | case SPRN_TBWL: break; | |
338 | case SPRN_TBWU: break; | |
339 | ||
513579e3 AG |
340 | case SPRN_MSSSR0: break; |
341 | ||
bbf45ba5 | 342 | case SPRN_DEC: |
8e5b26b5 | 343 | vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs); |
bbf45ba5 HB |
344 | kvmppc_emulate_dec(vcpu); |
345 | break; | |
346 | ||
bbf45ba5 | 347 | case SPRN_SPRG0: |
a73a9599 AG |
348 | vcpu->arch.shared->sprg0 = kvmppc_get_gpr(vcpu, rs); |
349 | break; | |
bbf45ba5 | 350 | case SPRN_SPRG1: |
a73a9599 AG |
351 | vcpu->arch.shared->sprg1 = kvmppc_get_gpr(vcpu, rs); |
352 | break; | |
bbf45ba5 | 353 | case SPRN_SPRG2: |
a73a9599 AG |
354 | vcpu->arch.shared->sprg2 = kvmppc_get_gpr(vcpu, rs); |
355 | break; | |
bbf45ba5 | 356 | case SPRN_SPRG3: |
a73a9599 AG |
357 | vcpu->arch.shared->sprg3 = kvmppc_get_gpr(vcpu, rs); |
358 | break; | |
bbf45ba5 | 359 | |
bbf45ba5 | 360 | default: |
75f74f0d HB |
361 | emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs); |
362 | if (emulated == EMULATE_FAIL) | |
363 | printk("mtspr: unknown spr %x\n", sprn); | |
bbf45ba5 HB |
364 | break; |
365 | } | |
366 | break; | |
367 | ||
cea5d8c9 | 368 | case OP_31_XOP_DCBI: |
bbf45ba5 HB |
369 | /* Do nothing. The guest is performing dcbi because |
370 | * hardware DMA is not snooped by the dcache, but | |
371 | * emulated DMA either goes through the dcache as | |
372 | * normal writes, or the host kernel has handled dcache | |
373 | * coherence. */ | |
374 | break; | |
375 | ||
cea5d8c9 | 376 | case OP_31_XOP_LWBRX: |
bbf45ba5 HB |
377 | rt = get_rt(inst); |
378 | emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0); | |
379 | break; | |
380 | ||
cea5d8c9 | 381 | case OP_31_XOP_TLBSYNC: |
bbf45ba5 HB |
382 | break; |
383 | ||
cea5d8c9 | 384 | case OP_31_XOP_STWBRX: |
bbf45ba5 HB |
385 | rs = get_rs(inst); |
386 | ra = get_ra(inst); | |
387 | rb = get_rb(inst); | |
388 | ||
389 | emulated = kvmppc_handle_store(run, vcpu, | |
8e5b26b5 | 390 | kvmppc_get_gpr(vcpu, rs), |
bbf45ba5 HB |
391 | 4, 0); |
392 | break; | |
393 | ||
cea5d8c9 | 394 | case OP_31_XOP_LHBRX: |
bbf45ba5 HB |
395 | rt = get_rt(inst); |
396 | emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0); | |
397 | break; | |
398 | ||
cea5d8c9 | 399 | case OP_31_XOP_STHBRX: |
bbf45ba5 HB |
400 | rs = get_rs(inst); |
401 | ra = get_ra(inst); | |
402 | rb = get_rb(inst); | |
403 | ||
404 | emulated = kvmppc_handle_store(run, vcpu, | |
8e5b26b5 | 405 | kvmppc_get_gpr(vcpu, rs), |
bbf45ba5 HB |
406 | 2, 0); |
407 | break; | |
408 | ||
bbf45ba5 | 409 | default: |
75f74f0d | 410 | /* Attempt core-specific emulation below. */ |
bbf45ba5 | 411 | emulated = EMULATE_FAIL; |
bbf45ba5 HB |
412 | } |
413 | break; | |
414 | ||
cea5d8c9 | 415 | case OP_LWZ: |
bbf45ba5 HB |
416 | rt = get_rt(inst); |
417 | emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); | |
418 | break; | |
419 | ||
cea5d8c9 | 420 | case OP_LWZU: |
bbf45ba5 HB |
421 | ra = get_ra(inst); |
422 | rt = get_rt(inst); | |
423 | emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); | |
8e5b26b5 | 424 | kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); |
bbf45ba5 HB |
425 | break; |
426 | ||
cea5d8c9 | 427 | case OP_LBZ: |
bbf45ba5 HB |
428 | rt = get_rt(inst); |
429 | emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); | |
430 | break; | |
431 | ||
cea5d8c9 | 432 | case OP_LBZU: |
bbf45ba5 HB |
433 | ra = get_ra(inst); |
434 | rt = get_rt(inst); | |
435 | emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); | |
8e5b26b5 | 436 | kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); |
bbf45ba5 HB |
437 | break; |
438 | ||
cea5d8c9 | 439 | case OP_STW: |
bbf45ba5 | 440 | rs = get_rs(inst); |
8e5b26b5 AG |
441 | emulated = kvmppc_handle_store(run, vcpu, |
442 | kvmppc_get_gpr(vcpu, rs), | |
bbf45ba5 HB |
443 | 4, 1); |
444 | break; | |
445 | ||
cea5d8c9 | 446 | case OP_STWU: |
bbf45ba5 HB |
447 | ra = get_ra(inst); |
448 | rs = get_rs(inst); | |
8e5b26b5 AG |
449 | emulated = kvmppc_handle_store(run, vcpu, |
450 | kvmppc_get_gpr(vcpu, rs), | |
bbf45ba5 | 451 | 4, 1); |
8e5b26b5 | 452 | kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); |
bbf45ba5 HB |
453 | break; |
454 | ||
cea5d8c9 | 455 | case OP_STB: |
bbf45ba5 | 456 | rs = get_rs(inst); |
8e5b26b5 AG |
457 | emulated = kvmppc_handle_store(run, vcpu, |
458 | kvmppc_get_gpr(vcpu, rs), | |
bbf45ba5 HB |
459 | 1, 1); |
460 | break; | |
461 | ||
cea5d8c9 | 462 | case OP_STBU: |
bbf45ba5 HB |
463 | ra = get_ra(inst); |
464 | rs = get_rs(inst); | |
8e5b26b5 AG |
465 | emulated = kvmppc_handle_store(run, vcpu, |
466 | kvmppc_get_gpr(vcpu, rs), | |
bbf45ba5 | 467 | 1, 1); |
8e5b26b5 | 468 | kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); |
bbf45ba5 HB |
469 | break; |
470 | ||
cea5d8c9 | 471 | case OP_LHZ: |
bbf45ba5 HB |
472 | rt = get_rt(inst); |
473 | emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); | |
474 | break; | |
475 | ||
cea5d8c9 | 476 | case OP_LHZU: |
bbf45ba5 HB |
477 | ra = get_ra(inst); |
478 | rt = get_rt(inst); | |
479 | emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); | |
8e5b26b5 | 480 | kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); |
bbf45ba5 HB |
481 | break; |
482 | ||
3587d534 AG |
483 | case OP_LHA: |
484 | rt = get_rt(inst); | |
485 | emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); | |
486 | break; | |
487 | ||
488 | case OP_LHAU: | |
489 | ra = get_ra(inst); | |
490 | rt = get_rt(inst); | |
491 | emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); | |
492 | kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); | |
493 | break; | |
494 | ||
cea5d8c9 | 495 | case OP_STH: |
bbf45ba5 | 496 | rs = get_rs(inst); |
8e5b26b5 AG |
497 | emulated = kvmppc_handle_store(run, vcpu, |
498 | kvmppc_get_gpr(vcpu, rs), | |
bbf45ba5 HB |
499 | 2, 1); |
500 | break; | |
501 | ||
cea5d8c9 | 502 | case OP_STHU: |
bbf45ba5 HB |
503 | ra = get_ra(inst); |
504 | rs = get_rs(inst); | |
8e5b26b5 AG |
505 | emulated = kvmppc_handle_store(run, vcpu, |
506 | kvmppc_get_gpr(vcpu, rs), | |
bbf45ba5 | 507 | 2, 1); |
8e5b26b5 | 508 | kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); |
bbf45ba5 HB |
509 | break; |
510 | ||
511 | default: | |
bbf45ba5 | 512 | emulated = EMULATE_FAIL; |
75f74f0d HB |
513 | } |
514 | ||
515 | if (emulated == EMULATE_FAIL) { | |
516 | emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance); | |
37f5bca6 AG |
517 | if (emulated == EMULATE_AGAIN) { |
518 | advance = 0; | |
519 | } else if (emulated == EMULATE_FAIL) { | |
75f74f0d HB |
520 | advance = 0; |
521 | printk(KERN_ERR "Couldn't emulate instruction 0x%08x " | |
522 | "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst)); | |
5f2b105a | 523 | kvmppc_core_queue_program(vcpu, 0); |
75f74f0d | 524 | } |
bbf45ba5 HB |
525 | } |
526 | ||
c7f38f46 | 527 | trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); |
3b4bd796 | 528 | |
c7f38f46 | 529 | /* Advance past emulated instruction. */ |
bbf45ba5 | 530 | if (advance) |
c7f38f46 | 531 | kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4); |
bbf45ba5 HB |
532 | |
533 | return emulated; | |
534 | } |