[net-next-2.6.git] / arch / powerpc / kvm / emulate.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright IBM Corp. 2007
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

#include <linux/jiffies.h>
#include <linux/hrtimer.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/kvm_host.h>

#include <asm/reg.h>
#include <asm/time.h>
#include <asm/byteorder.h>
#include <asm/kvm_ppc.h>
#include <asm/disassemble.h>
#include "timing.h"
#include "trace.h"

#define OP_TRAP 3
#define OP_TRAP_64 2

#define OP_31_XOP_LWZX      23
#define OP_31_XOP_LBZX      87
#define OP_31_XOP_STWX      151
#define OP_31_XOP_STBX      215
#define OP_31_XOP_STBUX     247
#define OP_31_XOP_LHZX      279
#define OP_31_XOP_LHZUX     311
#define OP_31_XOP_MFSPR     339
#define OP_31_XOP_STHX      407
#define OP_31_XOP_STHUX     439
#define OP_31_XOP_MTSPR     467
#define OP_31_XOP_DCBI      470
#define OP_31_XOP_LWBRX     534
#define OP_31_XOP_TLBSYNC   566
#define OP_31_XOP_STWBRX    662
#define OP_31_XOP_LHBRX     790
#define OP_31_XOP_STHBRX    918

#define OP_LWZ  32
#define OP_LWZU 33
#define OP_LBZ  34
#define OP_LBZU 35
#define OP_STW  36
#define OP_STWU 37
#define OP_STB  38
#define OP_STBU 39
#define OP_LHZ  40
#define OP_LHZU 41
#define OP_STH  44
#define OP_STHU 45

#ifdef CONFIG_PPC64
static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
{
	return 1;
}
#else
static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.tcr & TCR_DIE;
}
#endif

void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
{
	unsigned long dec_nsec;

	pr_debug("mtDEC: %x\n", vcpu->arch.dec);
#ifdef CONFIG_PPC64
	/* mtdec lowers the interrupt line when positive. */
	kvmppc_core_dequeue_dec(vcpu);

	/* POWER4+ triggers a dec interrupt if the value is < 0 */
	if (vcpu->arch.dec & 0x80000000) {
		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
		kvmppc_core_queue_dec(vcpu);
		return;
	}
#endif
	if (kvmppc_dec_enabled(vcpu)) {
		/* The decrementer ticks at the same rate as the timebase, so
		 * that's how we convert the guest DEC value to the number of
		 * host ticks. */

		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
		dec_nsec = vcpu->arch.dec;
		dec_nsec *= 1000;
		dec_nsec /= tb_ticks_per_usec;
		hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
			      HRTIMER_MODE_REL);
		vcpu->arch.dec_jiffies = get_tb();
	} else {
		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
	}
}

/* XXX to do:
 * lhax
 * lhaux
 * lswx
 * lswi
 * stswx
 * stswi
 * lha
 * lhau
 * lmw
 * stmw
 *
 * XXX is_bigendian should depend on MMU mapping or MSR[LE]
 */
/* XXX Should probably auto-generate instruction decoding for a particular core
 * from opcode tables in the future. */
int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
{
	u32 inst = vcpu->arch.last_inst;
	u32 ea;
	int ra;
	int rb;
	int rs;
	int rt;
	int sprn;
	enum emulation_result emulated = EMULATE_DONE;
	int advance = 1;

	/* this default type might be overwritten by subcategories */
	kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);

	pr_debug(KERN_INFO "Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));

	/* Try again next time */
	if (inst == KVM_INST_FETCH_FAILED)
		return EMULATE_DONE;

	switch (get_op(inst)) {
	case OP_TRAP:
#ifdef CONFIG_PPC64
	case OP_TRAP_64:
#else
		vcpu->arch.esr |= ESR_PTR;
#endif
		kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
		advance = 0;
		break;

	case 31:
		switch (get_xop(inst)) {

		case OP_31_XOP_LWZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
			break;

		case OP_31_XOP_LBZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
			break;

		case OP_31_XOP_STWX:
			rs = get_rs(inst);
			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               4, 1);
			break;

		case OP_31_XOP_STBX:
			rs = get_rs(inst);
			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               1, 1);
			break;

		case OP_31_XOP_STBUX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               1, 1);
			kvmppc_set_gpr(vcpu, rs, ea);
			break;

		case OP_31_XOP_LHZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
			break;

		case OP_31_XOP_LHZUX:
			rt = get_rt(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_MFSPR:
			sprn = get_sprn(inst);
			rt = get_rt(inst);

			switch (sprn) {
			case SPRN_SRR0:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr0); break;
			case SPRN_SRR1:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr1); break;
			case SPRN_PVR:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break;
			case SPRN_PIR:
				kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break;
			case SPRN_MSSSR0:
				kvmppc_set_gpr(vcpu, rt, 0); break;

			/* Note: mftb and TBRL/TBWL are user-accessible, so
			 * the guest can always access the real TB anyways.
			 * In fact, we probably will never see these traps. */
			case SPRN_TBWL:
				kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break;
			case SPRN_TBWU:
				kvmppc_set_gpr(vcpu, rt, get_tb()); break;

			case SPRN_SPRG0:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg0); break;
			case SPRN_SPRG1:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg1); break;
			case SPRN_SPRG2:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg2); break;
			case SPRN_SPRG3:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg3); break;
			/* Note: SPRG4-7 are user-readable, so we don't get
			 * a trap. */

			case SPRN_DEC:
			{
				u64 jd = get_tb() - vcpu->arch.dec_jiffies;
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.dec - jd);
				pr_debug(KERN_INFO "mfDEC: %x - %llx = %lx\n",
					 vcpu->arch.dec, jd,
					 kvmppc_get_gpr(vcpu, rt));
				break;
			}
			default:
				emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt);
				if (emulated == EMULATE_FAIL) {
					printk("mfspr: unknown spr %x\n", sprn);
					kvmppc_set_gpr(vcpu, rt, 0);
				}
				break;
			}
			break;

		case OP_31_XOP_STHX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 1);
			break;

		case OP_31_XOP_STHUX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_MTSPR:
			sprn = get_sprn(inst);
			rs = get_rs(inst);
			switch (sprn) {
			case SPRN_SRR0:
				vcpu->arch.srr0 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SRR1:
				vcpu->arch.srr1 = kvmppc_get_gpr(vcpu, rs); break;

			/* XXX We need to context-switch the timebase for
			 * watchdog and FIT. */
			case SPRN_TBWL: break;
			case SPRN_TBWU: break;

			case SPRN_MSSSR0: break;

			case SPRN_DEC:
				vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs);
				kvmppc_emulate_dec(vcpu);
				break;

			case SPRN_SPRG0:
				vcpu->arch.sprg0 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SPRG1:
				vcpu->arch.sprg1 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SPRG2:
				vcpu->arch.sprg2 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SPRG3:
				vcpu->arch.sprg3 = kvmppc_get_gpr(vcpu, rs); break;

			default:
				emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs);
				if (emulated == EMULATE_FAIL)
					printk("mtspr: unknown spr %x\n", sprn);
				break;
			}
			break;

		case OP_31_XOP_DCBI:
			/* Do nothing. The guest is performing dcbi because
			 * hardware DMA is not snooped by the dcache, but
			 * emulated DMA either goes through the dcache as
			 * normal writes, or the host kernel has handled dcache
			 * coherence. */
			break;

		case OP_31_XOP_LWBRX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
			break;

		case OP_31_XOP_TLBSYNC:
			break;

		case OP_31_XOP_STWBRX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               4, 0);
			break;

		case OP_31_XOP_LHBRX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
			break;

		case OP_31_XOP_STHBRX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 0);
			break;

		default:
			/* Attempt core-specific emulation below. */
			emulated = EMULATE_FAIL;
		}
		break;

	case OP_LWZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
		break;

	case OP_LWZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LBZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
		break;

	case OP_LBZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STW:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               4, 1);
		break;

	case OP_STWU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               4, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STB:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               1, 1);
		break;

	case OP_STBU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               1, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LHZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
		break;

	case OP_LHZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STH:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               2, 1);
		break;

	case OP_STHU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	default:
		emulated = EMULATE_FAIL;
	}

	if (emulated == EMULATE_FAIL) {
		emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance);
		if (emulated == EMULATE_FAIL) {
			advance = 0;
			printk(KERN_ERR "Couldn't emulate instruction 0x%08x "
			       "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
		}
	}

	trace_kvm_ppc_instr(inst, vcpu->arch.pc, emulated);

	if (advance)
		vcpu->arch.pc += 4; /* Advance past emulated instruction. */

	return emulated;
}
Commit	Line	Data
bbf45ba5 HB	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright IBM Corp. 2007
	16	*
	17	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	18	*/
	19
	20	#include <linux/jiffies.h>
544c6761	21	#include <linux/hrtimer.h>
bbf45ba5 HB	22	#include <linux/types.h>
	23	#include <linux/string.h>
	24	#include <linux/kvm_host.h>
	25
75f74f0d	26	#include <asm/reg.h>
bbf45ba5 HB	27	#include <asm/time.h>
	28	#include <asm/byteorder.h>
	29	#include <asm/kvm_ppc.h>
c381a043	30	#include <asm/disassemble.h>
73e75b41	31	#include "timing.h"
46f43c6e	32	#include "trace.h"
bbf45ba5	33
cea5d8c9	34	#define OP_TRAP 3
513579e3	35	#define OP_TRAP_64 2
cea5d8c9 HB	36
	37	#define OP_31_XOP_LWZX 23
	38	#define OP_31_XOP_LBZX 87
	39	#define OP_31_XOP_STWX 151
	40	#define OP_31_XOP_STBX 215
	41	#define OP_31_XOP_STBUX 247
	42	#define OP_31_XOP_LHZX 279
	43	#define OP_31_XOP_LHZUX 311
	44	#define OP_31_XOP_MFSPR 339
	45	#define OP_31_XOP_STHX 407
	46	#define OP_31_XOP_STHUX 439
	47	#define OP_31_XOP_MTSPR 467
	48	#define OP_31_XOP_DCBI 470
	49	#define OP_31_XOP_LWBRX 534
	50	#define OP_31_XOP_TLBSYNC 566
	51	#define OP_31_XOP_STWBRX 662
	52	#define OP_31_XOP_LHBRX 790
	53	#define OP_31_XOP_STHBRX 918
	54
	55	#define OP_LWZ 32
	56	#define OP_LWZU 33
	57	#define OP_LBZ 34
	58	#define OP_LBZU 35
	59	#define OP_STW 36
	60	#define OP_STWU 37
	61	#define OP_STB 38
	62	#define OP_STBU 39
	63	#define OP_LHZ 40
	64	#define OP_LHZU 41
	65	#define OP_STH 44
	66	#define OP_STHU 45
	67
513579e3 AG	68	#ifdef CONFIG_PPC64
	69	static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
	70	{
	71	return 1;
	72	}
	73	#else
	74	static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
	75	{
	76	return vcpu->arch.tcr & TCR_DIE;
	77	}
	78	#endif
	79
75f74f0d	80	void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
bbf45ba5	81	{
544c6761	82	unsigned long dec_nsec;
9a7a9b09	83
544c6761	84	pr_debug("mtDEC: %x\n", vcpu->arch.dec);
513579e3	85	#ifdef CONFIG_PPC64
7706664d AG	86	/* mtdec lowers the interrupt line when positive. */
	87	kvmppc_core_dequeue_dec(vcpu);
	88
513579e3 AG	89	/* POWER4+ triggers a dec interrupt if the value is < 0 */
513579e3 AG	90	if (vcpu->arch.dec & 0x80000000) {
544c6761	91	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
513579e3 AG	92	kvmppc_core_queue_dec(vcpu);
	93	return;
	94	}
	95	#endif
	96	if (kvmppc_dec_enabled(vcpu)) {
bbf45ba5 HB	97	/* The decrementer ticks at the same rate as the timebase, so
	98	* that's how we convert the guest DEC value to the number of
	99	* host ticks. */
bbf45ba5	100
544c6761 AG	101	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
	102	dec_nsec = vcpu->arch.dec;
	103	dec_nsec *= 1000;
	104	dec_nsec /= tb_ticks_per_usec;
	105	hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
	106	HRTIMER_MODE_REL);
513579e3	107	vcpu->arch.dec_jiffies = get_tb();
bbf45ba5	108	} else {
544c6761	109	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
bbf45ba5 HB	110	}
	111	}
	112
bbf45ba5 HB	113	/* XXX to do:
	114	* lhax
	115	* lhaux
	116	* lswx
	117	* lswi
	118	* stswx
	119	* stswi
	120	* lha
	121	* lhau
	122	* lmw
	123	* stmw
	124	*
	125	* XXX is_bigendian should depend on MMU mapping or MSR[LE]
	126	*/
75f74f0d HB	127	/* XXX Should probably auto-generate instruction decoding for a particular core
75f74f0d HB	128	* from opcode tables in the future. */
bbf45ba5 HB	129	int kvmppc_emulate_instruction(struct kvm_run run, struct kvm_vcpu vcpu)
	130	{
	131	u32 inst = vcpu->arch.last_inst;
	132	u32 ea;
	133	int ra;
	134	int rb;
bbf45ba5 HB	135	int rs;
	136	int rt;
	137	int sprn;
bbf45ba5 HB	138	enum emulation_result emulated = EMULATE_DONE;
	139	int advance = 1;
	140
73e75b41 HB	141	/* this default type might be overwritten by subcategories */
	142	kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
	143
513579e3 AG	144	pr_debug(KERN_INFO "Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));
513579e3 AG	145
b4433a7c AG	146	/* Try again next time */
	147	if (inst == KVM_INST_FETCH_FAILED)
	148	return EMULATE_DONE;
	149
bbf45ba5	150	switch (get_op(inst)) {
cea5d8c9	151	case OP_TRAP:
513579e3 AG	152	#ifdef CONFIG_PPC64
	153	case OP_TRAP_64:
	154	#else
fcfdbd26	155	vcpu->arch.esr \|= ESR_PTR;
513579e3	156	#endif
25a8a02d	157	kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
bbf45ba5 HB	158	advance = 0;
	159	break;
	160
bbf45ba5 HB	161	case 31:
	162	switch (get_xop(inst)) {
	163
cea5d8c9	164	case OP_31_XOP_LWZX:
ac3cd34e HB	165	rt = get_rt(inst);
	166	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
	167	break;
	168
cea5d8c9	169	case OP_31_XOP_LBZX:
bbf45ba5 HB	170	rt = get_rt(inst);
	171	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	172	break;
	173
cea5d8c9	174	case OP_31_XOP_STWX:
ac3cd34e HB	175	rs = get_rs(inst);
ac3cd34e HB	176	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	177	kvmppc_get_gpr(vcpu, rs),
ac3cd34e HB	178	4, 1);
	179	break;
	180
cea5d8c9	181	case OP_31_XOP_STBX:
bbf45ba5 HB	182	rs = get_rs(inst);
bbf45ba5 HB	183	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	184	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	185	1, 1);
	186	break;
	187
cea5d8c9	188	case OP_31_XOP_STBUX:
bbf45ba5 HB	189	rs = get_rs(inst);
	190	ra = get_ra(inst);
	191	rb = get_rb(inst);
	192
8e5b26b5	193	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	194	if (ra)
8e5b26b5	195	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	196
bbf45ba5 HB	197	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	198	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	199	1, 1);
8e5b26b5	200	kvmppc_set_gpr(vcpu, rs, ea);
bbf45ba5 HB	201	break;
bbf45ba5 HB	202
cea5d8c9	203	case OP_31_XOP_LHZX:
bbf45ba5 HB	204	rt = get_rt(inst);
	205	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
	206	break;
	207
cea5d8c9	208	case OP_31_XOP_LHZUX:
bbf45ba5 HB	209	rt = get_rt(inst);
	210	ra = get_ra(inst);
	211	rb = get_rb(inst);
	212
8e5b26b5	213	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	214	if (ra)
8e5b26b5	215	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	216
bbf45ba5 HB	217	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
8e5b26b5	218	kvmppc_set_gpr(vcpu, ra, ea);
bbf45ba5 HB	219	break;
bbf45ba5 HB	220
cea5d8c9	221	case OP_31_XOP_MFSPR:
bbf45ba5 HB	222	sprn = get_sprn(inst);
	223	rt = get_rt(inst);
	224
	225	switch (sprn) {
	226	case SPRN_SRR0:
8e5b26b5	227	kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr0); break;
bbf45ba5	228	case SPRN_SRR1:
8e5b26b5	229	kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr1); break;
bbf45ba5	230	case SPRN_PVR:
8e5b26b5	231	kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break;
06579dd9	232	case SPRN_PIR:
8e5b26b5	233	kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break;
513579e3	234	case SPRN_MSSSR0:
8e5b26b5	235	kvmppc_set_gpr(vcpu, rt, 0); break;
bbf45ba5 HB	236
	237	/* Note: mftb and TBRL/TBWL are user-accessible, so
	238	* the guest can always access the real TB anyways.
	239	* In fact, we probably will never see these traps. */
	240	case SPRN_TBWL:
8e5b26b5	241	kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break;
bbf45ba5	242	case SPRN_TBWU:
8e5b26b5	243	kvmppc_set_gpr(vcpu, rt, get_tb()); break;
bbf45ba5 HB	244
bbf45ba5 HB	245	case SPRN_SPRG0:
8e5b26b5	246	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg0); break;
bbf45ba5	247	case SPRN_SPRG1:
8e5b26b5	248	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg1); break;
bbf45ba5	249	case SPRN_SPRG2:
8e5b26b5	250	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg2); break;
bbf45ba5	251	case SPRN_SPRG3:
8e5b26b5	252	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg3); break;
bbf45ba5 HB	253	/* Note: SPRG4-7 are user-readable, so we don't get
	254	* a trap. */
	255
9a7a9b09 AG	256	case SPRN_DEC:
9a7a9b09 AG	257	{
513579e3	258	u64 jd = get_tb() - vcpu->arch.dec_jiffies;
8e5b26b5 AG	259	kvmppc_set_gpr(vcpu, rt, vcpu->arch.dec - jd);
	260	pr_debug(KERN_INFO "mfDEC: %x - %llx = %lx\n",
	261	vcpu->arch.dec, jd,
	262	kvmppc_get_gpr(vcpu, rt));
9a7a9b09 AG	263	break;
9a7a9b09 AG	264	}
bbf45ba5	265	default:
75f74f0d HB	266	emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt);
	267	if (emulated == EMULATE_FAIL) {
	268	printk("mfspr: unknown spr %x\n", sprn);
8e5b26b5	269	kvmppc_set_gpr(vcpu, rt, 0);
75f74f0d	270	}
bbf45ba5 HB	271	break;
	272	}
	273	break;
	274
cea5d8c9	275	case OP_31_XOP_STHX:
bbf45ba5 HB	276	rs = get_rs(inst);
	277	ra = get_ra(inst);
	278	rb = get_rb(inst);
	279
	280	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	281	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	282	2, 1);
	283	break;
	284
cea5d8c9	285	case OP_31_XOP_STHUX:
bbf45ba5 HB	286	rs = get_rs(inst);
	287	ra = get_ra(inst);
	288	rb = get_rb(inst);
	289
8e5b26b5	290	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	291	if (ra)
8e5b26b5	292	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	293
bbf45ba5 HB	294	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	295	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	296	2, 1);
8e5b26b5	297	kvmppc_set_gpr(vcpu, ra, ea);
bbf45ba5 HB	298	break;
bbf45ba5 HB	299
cea5d8c9	300	case OP_31_XOP_MTSPR:
bbf45ba5 HB	301	sprn = get_sprn(inst);
	302	rs = get_rs(inst);
	303	switch (sprn) {
	304	case SPRN_SRR0:
8e5b26b5	305	vcpu->arch.srr0 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	306	case SPRN_SRR1:
8e5b26b5	307	vcpu->arch.srr1 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5 HB	308
	309	/* XXX We need to context-switch the timebase for
	310	* watchdog and FIT. */
	311	case SPRN_TBWL: break;
	312	case SPRN_TBWU: break;
	313
513579e3 AG	314	case SPRN_MSSSR0: break;
513579e3 AG	315
bbf45ba5	316	case SPRN_DEC:
8e5b26b5	317	vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs);
bbf45ba5 HB	318	kvmppc_emulate_dec(vcpu);
	319	break;
	320
bbf45ba5	321	case SPRN_SPRG0:
8e5b26b5	322	vcpu->arch.sprg0 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	323	case SPRN_SPRG1:
8e5b26b5	324	vcpu->arch.sprg1 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	325	case SPRN_SPRG2:
8e5b26b5	326	vcpu->arch.sprg2 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	327	case SPRN_SPRG3:
8e5b26b5	328	vcpu->arch.sprg3 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	329
bbf45ba5	330	default:
75f74f0d HB	331	emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs);
	332	if (emulated == EMULATE_FAIL)
	333	printk("mtspr: unknown spr %x\n", sprn);
bbf45ba5 HB	334	break;
	335	}
	336	break;
	337
cea5d8c9	338	case OP_31_XOP_DCBI:
bbf45ba5 HB	339	/* Do nothing. The guest is performing dcbi because
	340	* hardware DMA is not snooped by the dcache, but
	341	* emulated DMA either goes through the dcache as
	342	* normal writes, or the host kernel has handled dcache
	343	* coherence. */
	344	break;
	345
cea5d8c9	346	case OP_31_XOP_LWBRX:
bbf45ba5 HB	347	rt = get_rt(inst);
	348	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
	349	break;
	350
cea5d8c9	351	case OP_31_XOP_TLBSYNC:
bbf45ba5 HB	352	break;
bbf45ba5 HB	353
cea5d8c9	354	case OP_31_XOP_STWBRX:
bbf45ba5 HB	355	rs = get_rs(inst);
	356	ra = get_ra(inst);
	357	rb = get_rb(inst);
	358
	359	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	360	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	361	4, 0);
	362	break;
	363
cea5d8c9	364	case OP_31_XOP_LHBRX:
bbf45ba5 HB	365	rt = get_rt(inst);
	366	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
	367	break;
	368
cea5d8c9	369	case OP_31_XOP_STHBRX:
bbf45ba5 HB	370	rs = get_rs(inst);
	371	ra = get_ra(inst);
	372	rb = get_rb(inst);
	373
	374	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	375	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	376	2, 0);
	377	break;
	378
bbf45ba5	379	default:
75f74f0d	380	/* Attempt core-specific emulation below. */
bbf45ba5	381	emulated = EMULATE_FAIL;
bbf45ba5 HB	382	}
	383	break;
	384
cea5d8c9	385	case OP_LWZ:
bbf45ba5 HB	386	rt = get_rt(inst);
	387	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
	388	break;
	389
cea5d8c9	390	case OP_LWZU:
bbf45ba5 HB	391	ra = get_ra(inst);
	392	rt = get_rt(inst);
	393	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
8e5b26b5	394	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	395	break;
bbf45ba5 HB	396
cea5d8c9	397	case OP_LBZ:
bbf45ba5 HB	398	rt = get_rt(inst);
	399	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	400	break;
	401
cea5d8c9	402	case OP_LBZU:
bbf45ba5 HB	403	ra = get_ra(inst);
	404	rt = get_rt(inst);
	405	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
8e5b26b5	406	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	407	break;
bbf45ba5 HB	408
cea5d8c9	409	case OP_STW:
bbf45ba5	410	rs = get_rs(inst);
8e5b26b5 AG	411	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	412	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	413	4, 1);
	414	break;
	415
cea5d8c9	416	case OP_STWU:
bbf45ba5 HB	417	ra = get_ra(inst);
bbf45ba5 HB	418	rs = get_rs(inst);
8e5b26b5 AG	419	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	420	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	421	4, 1);
8e5b26b5	422	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	423	break;
bbf45ba5 HB	424
cea5d8c9	425	case OP_STB:
bbf45ba5	426	rs = get_rs(inst);
8e5b26b5 AG	427	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	428	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	429	1, 1);
	430	break;
	431
cea5d8c9	432	case OP_STBU:
bbf45ba5 HB	433	ra = get_ra(inst);
bbf45ba5 HB	434	rs = get_rs(inst);
8e5b26b5 AG	435	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	436	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	437	1, 1);
8e5b26b5	438	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	439	break;
bbf45ba5 HB	440
cea5d8c9	441	case OP_LHZ:
bbf45ba5 HB	442	rt = get_rt(inst);
	443	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
	444	break;
	445
cea5d8c9	446	case OP_LHZU:
bbf45ba5 HB	447	ra = get_ra(inst);
	448	rt = get_rt(inst);
	449	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
8e5b26b5	450	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	451	break;
bbf45ba5 HB	452
cea5d8c9	453	case OP_STH:
bbf45ba5	454	rs = get_rs(inst);
8e5b26b5 AG	455	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	456	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	457	2, 1);
	458	break;
	459
cea5d8c9	460	case OP_STHU:
bbf45ba5 HB	461	ra = get_ra(inst);
bbf45ba5 HB	462	rs = get_rs(inst);
8e5b26b5 AG	463	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	464	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	465	2, 1);
8e5b26b5	466	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	467	break;
	468
	469	default:
bbf45ba5	470	emulated = EMULATE_FAIL;
75f74f0d HB	471	}
	472
	473	if (emulated == EMULATE_FAIL) {
	474	emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance);
	475	if (emulated == EMULATE_FAIL) {
	476	advance = 0;
	477	printk(KERN_ERR "Couldn't emulate instruction 0x%08x "
	478	"(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
	479	}
bbf45ba5 HB	480	}
bbf45ba5 HB	481
46f43c6e	482	trace_kvm_ppc_instr(inst, vcpu->arch.pc, emulated);
3b4bd796	483
bbf45ba5 HB	484	if (advance)
	485	vcpu->arch.pc += 4; /* Advance past emulated instruction. */
	486
	487	return emulated;
	488	}