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KVM: ppc: Refactor powerpc.c to relocate 440-specific code
[net-next-2.6.git] / arch / powerpc / kvm / emulate.c
CommitLineData
bbf45ba5
HB		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#include <linux/jiffies.h>
21#include <linux/timer.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <linux/kvm_host.h>
25
26#include <asm/dcr.h>
27#include <asm/dcr-regs.h>
28#include <asm/time.h>
29#include <asm/byteorder.h>
30#include <asm/kvm_ppc.h>
31
bbf45ba5
HB		 32/* Instruction decoding */
33static inline unsigned int get_op(u32 inst)
34{
35 return inst >> 26;
36}
37
38static inline unsigned int get_xop(u32 inst)
39{
40 return (inst >> 1) & 0x3ff;
41}
42
43static inline unsigned int get_sprn(u32 inst)
44{
45 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
46}
47
48static inline unsigned int get_dcrn(u32 inst)
49{
50 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
51}
52
53static inline unsigned int get_rt(u32 inst)
54{
55 return (inst >> 21) & 0x1f;
56}
57
58static inline unsigned int get_rs(u32 inst)
59{
60 return (inst >> 21) & 0x1f;
61}
62
63static inline unsigned int get_ra(u32 inst)
64{
65 return (inst >> 16) & 0x1f;
66}
67
68static inline unsigned int get_rb(u32 inst)
69{
70 return (inst >> 11) & 0x1f;
71}
72
73static inline unsigned int get_rc(u32 inst)
74{
75 return inst & 0x1;
76}
77
78static inline unsigned int get_ws(u32 inst)
79{
80 return (inst >> 11) & 0x1f;
81}
82
83static inline unsigned int get_d(u32 inst)
84{
85 return inst & 0xffff;
86}
87
bbf45ba5
HB		 88static void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
89{
90 if (vcpu->arch.tcr & TCR_DIE) {
91 /* The decrementer ticks at the same rate as the timebase, so
92 * that's how we convert the guest DEC value to the number of
93 * host ticks. */
94 unsigned long nr_jiffies;
95
96 nr_jiffies = vcpu->arch.dec / tb_ticks_per_jiffy;
97 mod_timer(&vcpu->arch.dec_timer,
98 get_jiffies_64() + nr_jiffies);
99 } else {
100 del_timer(&vcpu->arch.dec_timer);
101 }
102}
103
104static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
105{
106 vcpu->arch.pc = vcpu->arch.srr0;
107 kvmppc_set_msr(vcpu, vcpu->arch.srr1);
108}
109
110/* XXX to do:
111 * lhax
112 * lhaux
113 * lswx
114 * lswi
115 * stswx
116 * stswi
117 * lha
118 * lhau
119 * lmw
120 * stmw
121 *
122 * XXX is_bigendian should depend on MMU mapping or MSR[LE]
123 */
124int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
125{
126 u32 inst = vcpu->arch.last_inst;
127 u32 ea;
128 int ra;
129 int rb;
130 int rc;
131 int rs;
132 int rt;
a0d7b9f2 133 int ws;
bbf45ba5
HB		 134 int sprn;
135 int dcrn;
136 enum emulation_result emulated = EMULATE_DONE;
137 int advance = 1;
138
139 switch (get_op(inst)) {
140 case 3: /* trap */
141 printk("trap!\n");
9dd921cf 142 kvmppc_core_queue_program(vcpu);
bbf45ba5
HB		 143 advance = 0;
144 break;
145
146 case 19:
147 switch (get_xop(inst)) {
148 case 50: /* rfi */
149 kvmppc_emul_rfi(vcpu);
150 advance = 0;
151 break;
152
153 default:
154 emulated = EMULATE_FAIL;
155 break;
156 }
157 break;
158
159 case 31:
160 switch (get_xop(inst)) {
161
ac3cd34e
HB		 162 case 23: /* lwzx */
163 rt = get_rt(inst);
164 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
165 break;
166
bbf45ba5
HB		 167 case 83: /* mfmsr */
168 rt = get_rt(inst);
169 vcpu->arch.gpr[rt] = vcpu->arch.msr;
170 break;
171
172 case 87: /* lbzx */
173 rt = get_rt(inst);
174 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
175 break;
176
177 case 131: /* wrtee */
178 rs = get_rs(inst);
179 vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE)
180 | (vcpu->arch.gpr[rs] & MSR_EE);
181 break;
182
183 case 146: /* mtmsr */
184 rs = get_rs(inst);
185 kvmppc_set_msr(vcpu, vcpu->arch.gpr[rs]);
186 break;
187
ac3cd34e
HB		 188 case 151: /* stwx */
189 rs = get_rs(inst);
190 emulated = kvmppc_handle_store(run, vcpu,
191 vcpu->arch.gpr[rs],
192 4, 1);
193 break;
194
bbf45ba5
HB		 195 case 163: /* wrteei */
196 vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE)
197 | (inst & MSR_EE);
198 break;
199
200 case 215: /* stbx */
201 rs = get_rs(inst);
202 emulated = kvmppc_handle_store(run, vcpu,
203 vcpu->arch.gpr[rs],
204 1, 1);
205 break;
206
207 case 247: /* stbux */
208 rs = get_rs(inst);
209 ra = get_ra(inst);
210 rb = get_rb(inst);
211
212 ea = vcpu->arch.gpr[rb];
213 if (ra)
214 ea += vcpu->arch.gpr[ra];
215
216 emulated = kvmppc_handle_store(run, vcpu,
217 vcpu->arch.gpr[rs],
218 1, 1);
219 vcpu->arch.gpr[rs] = ea;
220 break;
221
222 case 279: /* lhzx */
223 rt = get_rt(inst);
224 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
225 break;
226
227 case 311: /* lhzux */
228 rt = get_rt(inst);
229 ra = get_ra(inst);
230 rb = get_rb(inst);
231
232 ea = vcpu->arch.gpr[rb];
233 if (ra)
234 ea += vcpu->arch.gpr[ra];
235
236 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
237 vcpu->arch.gpr[ra] = ea;
238 break;
239
240 case 323: /* mfdcr */
241 dcrn = get_dcrn(inst);
242 rt = get_rt(inst);
243
244 /* The guest may access CPR0 registers to determine the timebase
245 * frequency, and it must know the real host frequency because it
246 * can directly access the timebase registers.
247 *
248 * It would be possible to emulate those accesses in userspace,
249 * but userspace can really only figure out the end frequency.
250 * We could decompose that into the factors that compute it, but
251 * that's tricky math, and it's easier to just report the real
252 * CPR0 values.
253 */
254 switch (dcrn) {
255 case DCRN_CPR0_CONFIG_ADDR:
256 vcpu->arch.gpr[rt] = vcpu->arch.cpr0_cfgaddr;
257 break;
258 case DCRN_CPR0_CONFIG_DATA:
259 local_irq_disable();
260 mtdcr(DCRN_CPR0_CONFIG_ADDR,
261 vcpu->arch.cpr0_cfgaddr);
262 vcpu->arch.gpr[rt] = mfdcr(DCRN_CPR0_CONFIG_DATA);
263 local_irq_enable();
264 break;
265 default:
266 run->dcr.dcrn = dcrn;
267 run->dcr.data = 0;
268 run->dcr.is_write = 0;
269 vcpu->arch.io_gpr = rt;
270 vcpu->arch.dcr_needed = 1;
271 emulated = EMULATE_DO_DCR;
272 }
273
274 break;
275
276 case 339: /* mfspr */
277 sprn = get_sprn(inst);
278 rt = get_rt(inst);
279
280 switch (sprn) {
281 case SPRN_SRR0:
282 vcpu->arch.gpr[rt] = vcpu->arch.srr0; break;
283 case SPRN_SRR1:
284 vcpu->arch.gpr[rt] = vcpu->arch.srr1; break;
285 case SPRN_MMUCR:
286 vcpu->arch.gpr[rt] = vcpu->arch.mmucr; break;
287 case SPRN_PID:
288 vcpu->arch.gpr[rt] = vcpu->arch.pid; break;
289 case SPRN_IVPR:
290 vcpu->arch.gpr[rt] = vcpu->arch.ivpr; break;
291 case SPRN_CCR0:
292 vcpu->arch.gpr[rt] = vcpu->arch.ccr0; break;
293 case SPRN_CCR1:
294 vcpu->arch.gpr[rt] = vcpu->arch.ccr1; break;
295 case SPRN_PVR:
296 vcpu->arch.gpr[rt] = vcpu->arch.pvr; break;
297 case SPRN_DEAR:
298 vcpu->arch.gpr[rt] = vcpu->arch.dear; break;
299 case SPRN_ESR:
300 vcpu->arch.gpr[rt] = vcpu->arch.esr; break;
301 case SPRN_DBCR0:
302 vcpu->arch.gpr[rt] = vcpu->arch.dbcr0; break;
303 case SPRN_DBCR1:
304 vcpu->arch.gpr[rt] = vcpu->arch.dbcr1; break;
305
306 /* Note: mftb and TBRL/TBWL are user-accessible, so
307 * the guest can always access the real TB anyways.
308 * In fact, we probably will never see these traps. */
309 case SPRN_TBWL:
310 vcpu->arch.gpr[rt] = mftbl(); break;
311 case SPRN_TBWU:
312 vcpu->arch.gpr[rt] = mftbu(); break;
313
314 case SPRN_SPRG0:
315 vcpu->arch.gpr[rt] = vcpu->arch.sprg0; break;
316 case SPRN_SPRG1:
317 vcpu->arch.gpr[rt] = vcpu->arch.sprg1; break;
318 case SPRN_SPRG2:
319 vcpu->arch.gpr[rt] = vcpu->arch.sprg2; break;
320 case SPRN_SPRG3:
321 vcpu->arch.gpr[rt] = vcpu->arch.sprg3; break;
322 /* Note: SPRG4-7 are user-readable, so we don't get
323 * a trap. */
324
325 case SPRN_IVOR0:
326 vcpu->arch.gpr[rt] = vcpu->arch.ivor[0]; break;
327 case SPRN_IVOR1:
328 vcpu->arch.gpr[rt] = vcpu->arch.ivor[1]; break;
329 case SPRN_IVOR2:
330 vcpu->arch.gpr[rt] = vcpu->arch.ivor[2]; break;
331 case SPRN_IVOR3:
332 vcpu->arch.gpr[rt] = vcpu->arch.ivor[3]; break;
333 case SPRN_IVOR4:
334 vcpu->arch.gpr[rt] = vcpu->arch.ivor[4]; break;
335 case SPRN_IVOR5:
336 vcpu->arch.gpr[rt] = vcpu->arch.ivor[5]; break;
337 case SPRN_IVOR6:
338 vcpu->arch.gpr[rt] = vcpu->arch.ivor[6]; break;
339 case SPRN_IVOR7:
340 vcpu->arch.gpr[rt] = vcpu->arch.ivor[7]; break;
341 case SPRN_IVOR8:
342 vcpu->arch.gpr[rt] = vcpu->arch.ivor[8]; break;
343 case SPRN_IVOR9:
344 vcpu->arch.gpr[rt] = vcpu->arch.ivor[9]; break;
345 case SPRN_IVOR10:
346 vcpu->arch.gpr[rt] = vcpu->arch.ivor[10]; break;
347 case SPRN_IVOR11:
348 vcpu->arch.gpr[rt] = vcpu->arch.ivor[11]; break;
349 case SPRN_IVOR12:
350 vcpu->arch.gpr[rt] = vcpu->arch.ivor[12]; break;
351 case SPRN_IVOR13:
352 vcpu->arch.gpr[rt] = vcpu->arch.ivor[13]; break;
353 case SPRN_IVOR14:
354 vcpu->arch.gpr[rt] = vcpu->arch.ivor[14]; break;
355 case SPRN_IVOR15:
356 vcpu->arch.gpr[rt] = vcpu->arch.ivor[15]; break;
357
358 default:
359 printk("mfspr: unknown spr %x\n", sprn);
360 vcpu->arch.gpr[rt] = 0;
361 break;
362 }
363 break;
364
365 case 407: /* sthx */
366 rs = get_rs(inst);
367 ra = get_ra(inst);
368 rb = get_rb(inst);
369
370 emulated = kvmppc_handle_store(run, vcpu,
371 vcpu->arch.gpr[rs],
372 2, 1);
373 break;
374
375 case 439: /* sthux */
376 rs = get_rs(inst);
377 ra = get_ra(inst);
378 rb = get_rb(inst);
379
380 ea = vcpu->arch.gpr[rb];
381 if (ra)
382 ea += vcpu->arch.gpr[ra];
383
384 emulated = kvmppc_handle_store(run, vcpu,
385 vcpu->arch.gpr[rs],
386 2, 1);
387 vcpu->arch.gpr[ra] = ea;
388 break;
389
390 case 451: /* mtdcr */
391 dcrn = get_dcrn(inst);
392 rs = get_rs(inst);
393
394 /* emulate some access in kernel */
395 switch (dcrn) {
396 case DCRN_CPR0_CONFIG_ADDR:
397 vcpu->arch.cpr0_cfgaddr = vcpu->arch.gpr[rs];
398 break;
399 default:
400 run->dcr.dcrn = dcrn;
401 run->dcr.data = vcpu->arch.gpr[rs];
402 run->dcr.is_write = 1;
403 vcpu->arch.dcr_needed = 1;
404 emulated = EMULATE_DO_DCR;
405 }
406
407 break;
408
409 case 467: /* mtspr */
410 sprn = get_sprn(inst);
411 rs = get_rs(inst);
412 switch (sprn) {
413 case SPRN_SRR0:
414 vcpu->arch.srr0 = vcpu->arch.gpr[rs]; break;
415 case SPRN_SRR1:
416 vcpu->arch.srr1 = vcpu->arch.gpr[rs]; break;
417 case SPRN_MMUCR:
418 vcpu->arch.mmucr = vcpu->arch.gpr[rs]; break;
419 case SPRN_PID:
49dd2c49 420 kvmppc_set_pid(vcpu, vcpu->arch.gpr[rs]); break;
bbf45ba5
HB		 421 case SPRN_CCR0:
422 vcpu->arch.ccr0 = vcpu->arch.gpr[rs]; break;
423 case SPRN_CCR1:
424 vcpu->arch.ccr1 = vcpu->arch.gpr[rs]; break;
425 case SPRN_DEAR:
426 vcpu->arch.dear = vcpu->arch.gpr[rs]; break;
427 case SPRN_ESR:
428 vcpu->arch.esr = vcpu->arch.gpr[rs]; break;
429 case SPRN_DBCR0:
430 vcpu->arch.dbcr0 = vcpu->arch.gpr[rs]; break;
431 case SPRN_DBCR1:
432 vcpu->arch.dbcr1 = vcpu->arch.gpr[rs]; break;
433
434 /* XXX We need to context-switch the timebase for
435 * watchdog and FIT. */
436 case SPRN_TBWL: break;
437 case SPRN_TBWU: break;
438
439 case SPRN_DEC:
440 vcpu->arch.dec = vcpu->arch.gpr[rs];
441 kvmppc_emulate_dec(vcpu);
442 break;
443
444 case SPRN_TSR:
445 vcpu->arch.tsr &= ~vcpu->arch.gpr[rs]; break;
446
447 case SPRN_TCR:
448 vcpu->arch.tcr = vcpu->arch.gpr[rs];
449 kvmppc_emulate_dec(vcpu);
450 break;
451
452 case SPRN_SPRG0:
453 vcpu->arch.sprg0 = vcpu->arch.gpr[rs]; break;
454 case SPRN_SPRG1:
455 vcpu->arch.sprg1 = vcpu->arch.gpr[rs]; break;
456 case SPRN_SPRG2:
457 vcpu->arch.sprg2 = vcpu->arch.gpr[rs]; break;
458 case SPRN_SPRG3:
459 vcpu->arch.sprg3 = vcpu->arch.gpr[rs]; break;
460
461 /* Note: SPRG4-7 are user-readable. These values are
462 * loaded into the real SPRGs when resuming the
463 * guest. */
464 case SPRN_SPRG4:
465 vcpu->arch.sprg4 = vcpu->arch.gpr[rs]; break;
466 case SPRN_SPRG5:
467 vcpu->arch.sprg5 = vcpu->arch.gpr[rs]; break;
468 case SPRN_SPRG6:
469 vcpu->arch.sprg6 = vcpu->arch.gpr[rs]; break;
470 case SPRN_SPRG7:
471 vcpu->arch.sprg7 = vcpu->arch.gpr[rs]; break;
472
473 case SPRN_IVPR:
474 vcpu->arch.ivpr = vcpu->arch.gpr[rs]; break;
475 case SPRN_IVOR0:
476 vcpu->arch.ivor[0] = vcpu->arch.gpr[rs]; break;
477 case SPRN_IVOR1:
478 vcpu->arch.ivor[1] = vcpu->arch.gpr[rs]; break;
479 case SPRN_IVOR2:
480 vcpu->arch.ivor[2] = vcpu->arch.gpr[rs]; break;
481 case SPRN_IVOR3:
482 vcpu->arch.ivor[3] = vcpu->arch.gpr[rs]; break;
483 case SPRN_IVOR4:
484 vcpu->arch.ivor[4] = vcpu->arch.gpr[rs]; break;
485 case SPRN_IVOR5:
486 vcpu->arch.ivor[5] = vcpu->arch.gpr[rs]; break;
487 case SPRN_IVOR6:
488 vcpu->arch.ivor[6] = vcpu->arch.gpr[rs]; break;
489 case SPRN_IVOR7:
490 vcpu->arch.ivor[7] = vcpu->arch.gpr[rs]; break;
491 case SPRN_IVOR8:
492 vcpu->arch.ivor[8] = vcpu->arch.gpr[rs]; break;
493 case SPRN_IVOR9:
494 vcpu->arch.ivor[9] = vcpu->arch.gpr[rs]; break;
495 case SPRN_IVOR10:
496 vcpu->arch.ivor[10] = vcpu->arch.gpr[rs]; break;
497 case SPRN_IVOR11:
498 vcpu->arch.ivor[11] = vcpu->arch.gpr[rs]; break;
499 case SPRN_IVOR12:
500 vcpu->arch.ivor[12] = vcpu->arch.gpr[rs]; break;
501 case SPRN_IVOR13:
502 vcpu->arch.ivor[13] = vcpu->arch.gpr[rs]; break;
503 case SPRN_IVOR14:
504 vcpu->arch.ivor[14] = vcpu->arch.gpr[rs]; break;
505 case SPRN_IVOR15:
506 vcpu->arch.ivor[15] = vcpu->arch.gpr[rs]; break;
507
508 default:
509 printk("mtspr: unknown spr %x\n", sprn);
510 emulated = EMULATE_FAIL;
511 break;
512 }
513 break;
514
515 case 470: /* dcbi */
516 /* Do nothing. The guest is performing dcbi because
517 * hardware DMA is not snooped by the dcache, but
518 * emulated DMA either goes through the dcache as
519 * normal writes, or the host kernel has handled dcache
520 * coherence. */
521 break;
522
523 case 534: /* lwbrx */
524 rt = get_rt(inst);
525 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
526 break;
527
528 case 566: /* tlbsync */
529 break;
530
531 case 662: /* stwbrx */
532 rs = get_rs(inst);
533 ra = get_ra(inst);
534 rb = get_rb(inst);
535
536 emulated = kvmppc_handle_store(run, vcpu,
537 vcpu->arch.gpr[rs],
538 4, 0);
539 break;
540
541 case 978: /* tlbwe */
a0d7b9f2
HB		 542 ra = get_ra(inst);
543 rs = get_rs(inst);
544 ws = get_ws(inst);
545 emulated = kvmppc_emul_tlbwe(vcpu, ra, rs, ws);
bbf45ba5
HB		 546 break;
547
a0d7b9f2 548 case 914: /* tlbsx */
bbf45ba5
HB		 549 rt = get_rt(inst);
550 ra = get_ra(inst);
551 rb = get_rb(inst);
552 rc = get_rc(inst);
a0d7b9f2 553 emulated = kvmppc_emul_tlbsx(vcpu, rt, ra, rb, rc);
bbf45ba5
HB		 554 break;
555
556 case 790: /* lhbrx */
557 rt = get_rt(inst);
558 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
559 break;
560
561 case 918: /* sthbrx */
562 rs = get_rs(inst);
563 ra = get_ra(inst);
564 rb = get_rb(inst);
565
566 emulated = kvmppc_handle_store(run, vcpu,
567 vcpu->arch.gpr[rs],
568 2, 0);
569 break;
570
571 case 966: /* iccci */
572 break;
573
574 default:
575 printk("unknown: op %d xop %d\n", get_op(inst),
576 get_xop(inst));
577 emulated = EMULATE_FAIL;
578 break;
579 }
580 break;
581
582 case 32: /* lwz */
583 rt = get_rt(inst);
584 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
585 break;
586
587 case 33: /* lwzu */
588 ra = get_ra(inst);
589 rt = get_rt(inst);
590 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
591 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
592 break;
593
594 case 34: /* lbz */
595 rt = get_rt(inst);
596 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
597 break;
598
599 case 35: /* lbzu */
600 ra = get_ra(inst);
601 rt = get_rt(inst);
602 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
603 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
604 break;
605
606 case 36: /* stw */
607 rs = get_rs(inst);
608 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
609 4, 1);
610 break;
611
612 case 37: /* stwu */
613 ra = get_ra(inst);
614 rs = get_rs(inst);
615 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
616 4, 1);
617 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
618 break;
619
620 case 38: /* stb */
621 rs = get_rs(inst);
622 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
623 1, 1);
624 break;
625
626 case 39: /* stbu */
627 ra = get_ra(inst);
628 rs = get_rs(inst);
629 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
630 1, 1);
631 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
632 break;
633
634 case 40: /* lhz */
635 rt = get_rt(inst);
636 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
637 break;
638
639 case 41: /* lhzu */
640 ra = get_ra(inst);
641 rt = get_rt(inst);
642 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
643 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
644 break;
645
646 case 44: /* sth */
647 rs = get_rs(inst);
648 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
649 2, 1);
650 break;
651
652 case 45: /* sthu */
653 ra = get_ra(inst);
654 rs = get_rs(inst);
655 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
656 2, 1);
657 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
658 break;
659
660 default:
661 printk("unknown op %d\n", get_op(inst));
662 emulated = EMULATE_FAIL;
663 break;
664 }
665
3b4bd796
CE		 666 KVMTRACE_3D(PPC_INSTR, vcpu, inst, vcpu->arch.pc, emulated, entryexit);
667
bbf45ba5
HB		 668 if (advance)
669 vcpu->arch.pc += 4; /* Advance past emulated instruction. */
670
671 return emulated;
672}
Clone of davem's net-next-2.6 tree