]>
Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/unistd.h> | |
8dad3f92 | 23 | #include <linux/ptrace.h> |
14cf11af PM |
24 | #include <linux/slab.h> |
25 | #include <linux/user.h> | |
14cf11af | 26 | #include <linux/interrupt.h> |
14cf11af PM |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> | |
8dad3f92 | 29 | #include <linux/prctl.h> |
14cf11af PM |
30 | #include <linux/delay.h> |
31 | #include <linux/kprobes.h> | |
cc532915 | 32 | #include <linux/kexec.h> |
5474c120 | 33 | #include <linux/backlight.h> |
73c9ceab | 34 | #include <linux/bug.h> |
1eeb66a1 | 35 | #include <linux/kdebug.h> |
80947e7c | 36 | #include <linux/debugfs.h> |
14cf11af | 37 | |
80947e7c | 38 | #include <asm/emulated_ops.h> |
14cf11af PM |
39 | #include <asm/pgtable.h> |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/system.h> | |
42 | #include <asm/io.h> | |
86417780 PM |
43 | #include <asm/machdep.h> |
44 | #include <asm/rtas.h> | |
f7f6f4fe | 45 | #include <asm/pmc.h> |
dc1c1ca3 | 46 | #ifdef CONFIG_PPC32 |
14cf11af | 47 | #include <asm/reg.h> |
86417780 | 48 | #endif |
14cf11af PM |
49 | #ifdef CONFIG_PMAC_BACKLIGHT |
50 | #include <asm/backlight.h> | |
51 | #endif | |
dc1c1ca3 | 52 | #ifdef CONFIG_PPC64 |
86417780 | 53 | #include <asm/firmware.h> |
dc1c1ca3 | 54 | #include <asm/processor.h> |
dc1c1ca3 | 55 | #endif |
c0ce7d08 | 56 | #include <asm/kexec.h> |
16c57b36 | 57 | #include <asm/ppc-opcode.h> |
620165f9 KG |
58 | #ifdef CONFIG_FSL_BOOKE |
59 | #include <asm/dbell.h> | |
60 | #endif | |
dc1c1ca3 | 61 | |
7dbb922c | 62 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
5be3492f AB |
63 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
64 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
65 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
66 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
67 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
68 | int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; | |
69 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; | |
14cf11af PM |
70 | |
71 | EXPORT_SYMBOL(__debugger); | |
72 | EXPORT_SYMBOL(__debugger_ipi); | |
73 | EXPORT_SYMBOL(__debugger_bpt); | |
74 | EXPORT_SYMBOL(__debugger_sstep); | |
75 | EXPORT_SYMBOL(__debugger_iabr_match); | |
76 | EXPORT_SYMBOL(__debugger_dabr_match); | |
77 | EXPORT_SYMBOL(__debugger_fault_handler); | |
78 | #endif | |
79 | ||
14cf11af PM |
80 | /* |
81 | * Trap & Exception support | |
82 | */ | |
83 | ||
6031d9d9 | 84 | #ifdef CONFIG_PMAC_BACKLIGHT |
85 | static void pmac_backlight_unblank(void) | |
86 | { | |
87 | mutex_lock(&pmac_backlight_mutex); | |
88 | if (pmac_backlight) { | |
89 | struct backlight_properties *props; | |
90 | ||
91 | props = &pmac_backlight->props; | |
92 | props->brightness = props->max_brightness; | |
93 | props->power = FB_BLANK_UNBLANK; | |
94 | backlight_update_status(pmac_backlight); | |
95 | } | |
96 | mutex_unlock(&pmac_backlight_mutex); | |
97 | } | |
98 | #else | |
99 | static inline void pmac_backlight_unblank(void) { } | |
100 | #endif | |
101 | ||
14cf11af PM |
102 | int die(const char *str, struct pt_regs *regs, long err) |
103 | { | |
34c2a14f | 104 | static struct { |
105 | spinlock_t lock; | |
106 | u32 lock_owner; | |
107 | int lock_owner_depth; | |
108 | } die = { | |
109 | .lock = __SPIN_LOCK_UNLOCKED(die.lock), | |
110 | .lock_owner = -1, | |
111 | .lock_owner_depth = 0 | |
112 | }; | |
c0ce7d08 | 113 | static int die_counter; |
34c2a14f | 114 | unsigned long flags; |
14cf11af PM |
115 | |
116 | if (debugger(regs)) | |
117 | return 1; | |
118 | ||
293e4688 | 119 | oops_enter(); |
120 | ||
34c2a14f | 121 | if (die.lock_owner != raw_smp_processor_id()) { |
122 | console_verbose(); | |
123 | spin_lock_irqsave(&die.lock, flags); | |
124 | die.lock_owner = smp_processor_id(); | |
125 | die.lock_owner_depth = 0; | |
126 | bust_spinlocks(1); | |
127 | if (machine_is(powermac)) | |
128 | pmac_backlight_unblank(); | |
129 | } else { | |
130 | local_save_flags(flags); | |
131 | } | |
5474c120 | 132 | |
34c2a14f | 133 | if (++die.lock_owner_depth < 3) { |
134 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
14cf11af | 135 | #ifdef CONFIG_PREEMPT |
34c2a14f | 136 | printk("PREEMPT "); |
14cf11af PM |
137 | #endif |
138 | #ifdef CONFIG_SMP | |
34c2a14f | 139 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
14cf11af PM |
140 | #endif |
141 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
34c2a14f | 142 | printk("DEBUG_PAGEALLOC "); |
14cf11af PM |
143 | #endif |
144 | #ifdef CONFIG_NUMA | |
34c2a14f | 145 | printk("NUMA "); |
14cf11af | 146 | #endif |
ae7f4463 | 147 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
34c2a14f | 148 | |
66fcb105 AB |
149 | sysfs_printk_last_file(); |
150 | if (notify_die(DIE_OOPS, str, regs, err, 255, | |
151 | SIGSEGV) == NOTIFY_STOP) | |
152 | return 1; | |
153 | ||
34c2a14f | 154 | print_modules(); |
155 | show_regs(regs); | |
156 | } else { | |
157 | printk("Recursive die() failure, output suppressed\n"); | |
158 | } | |
e8222502 | 159 | |
14cf11af | 160 | bust_spinlocks(0); |
34c2a14f | 161 | die.lock_owner = -1; |
bcdcd8e7 | 162 | add_taint(TAINT_DIE); |
34c2a14f | 163 | spin_unlock_irqrestore(&die.lock, flags); |
cc532915 | 164 | |
c0ce7d08 DW |
165 | if (kexec_should_crash(current) || |
166 | kexec_sr_activated(smp_processor_id())) | |
cc532915 | 167 | crash_kexec(regs); |
c0ce7d08 | 168 | crash_kexec_secondary(regs); |
14cf11af PM |
169 | |
170 | if (in_interrupt()) | |
171 | panic("Fatal exception in interrupt"); | |
172 | ||
cea6a4ba | 173 | if (panic_on_oops) |
012c437d | 174 | panic("Fatal exception"); |
cea6a4ba | 175 | |
293e4688 | 176 | oops_exit(); |
14cf11af PM |
177 | do_exit(err); |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
25baa35b ON |
182 | void user_single_step_siginfo(struct task_struct *tsk, |
183 | struct pt_regs *regs, siginfo_t *info) | |
184 | { | |
185 | memset(info, 0, sizeof(*info)); | |
186 | info->si_signo = SIGTRAP; | |
187 | info->si_code = TRAP_TRACE; | |
188 | info->si_addr = (void __user *)regs->nip; | |
189 | } | |
190 | ||
14cf11af PM |
191 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
192 | { | |
193 | siginfo_t info; | |
d0c3d534 OJ |
194 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
195 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
196 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
197 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
198 | |
199 | if (!user_mode(regs)) { | |
200 | if (die("Exception in kernel mode", regs, signr)) | |
201 | return; | |
d0c3d534 OJ |
202 | } else if (show_unhandled_signals && |
203 | unhandled_signal(current, signr) && | |
204 | printk_ratelimit()) { | |
205 | printk(regs->msr & MSR_SF ? fmt64 : fmt32, | |
206 | current->comm, current->pid, signr, | |
207 | addr, regs->nip, regs->link, code); | |
208 | } | |
14cf11af PM |
209 | |
210 | memset(&info, 0, sizeof(info)); | |
211 | info.si_signo = signr; | |
212 | info.si_code = code; | |
213 | info.si_addr = (void __user *) addr; | |
214 | force_sig_info(signr, &info, current); | |
14cf11af PM |
215 | } |
216 | ||
217 | #ifdef CONFIG_PPC64 | |
218 | void system_reset_exception(struct pt_regs *regs) | |
219 | { | |
220 | /* See if any machine dependent calls */ | |
c902be71 AB |
221 | if (ppc_md.system_reset_exception) { |
222 | if (ppc_md.system_reset_exception(regs)) | |
223 | return; | |
224 | } | |
14cf11af | 225 | |
c0ce7d08 DW |
226 | #ifdef CONFIG_KEXEC |
227 | cpu_set(smp_processor_id(), cpus_in_sr); | |
228 | #endif | |
229 | ||
8dad3f92 | 230 | die("System Reset", regs, SIGABRT); |
14cf11af | 231 | |
eac8392f DW |
232 | /* |
233 | * Some CPUs when released from the debugger will execute this path. | |
234 | * These CPUs entered the debugger via a soft-reset. If the CPU was | |
235 | * hung before entering the debugger it will return to the hung | |
236 | * state when exiting this function. This causes a problem in | |
237 | * kdump since the hung CPU(s) will not respond to the IPI sent | |
238 | * from kdump. To prevent the problem we call crash_kexec_secondary() | |
239 | * here. If a kdump had not been initiated or we exit the debugger | |
240 | * with the "exit and recover" command (x) crash_kexec_secondary() | |
241 | * will return after 5ms and the CPU returns to its previous state. | |
242 | */ | |
243 | crash_kexec_secondary(regs); | |
244 | ||
14cf11af PM |
245 | /* Must die if the interrupt is not recoverable */ |
246 | if (!(regs->msr & MSR_RI)) | |
247 | panic("Unrecoverable System Reset"); | |
248 | ||
249 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
250 | } | |
251 | #endif | |
252 | ||
253 | /* | |
254 | * I/O accesses can cause machine checks on powermacs. | |
255 | * Check if the NIP corresponds to the address of a sync | |
256 | * instruction for which there is an entry in the exception | |
257 | * table. | |
258 | * Note that the 601 only takes a machine check on TEA | |
259 | * (transfer error ack) signal assertion, and does not | |
260 | * set any of the top 16 bits of SRR1. | |
261 | * -- paulus. | |
262 | */ | |
263 | static inline int check_io_access(struct pt_regs *regs) | |
264 | { | |
68a64357 | 265 | #ifdef CONFIG_PPC32 |
14cf11af PM |
266 | unsigned long msr = regs->msr; |
267 | const struct exception_table_entry *entry; | |
268 | unsigned int *nip = (unsigned int *)regs->nip; | |
269 | ||
270 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
271 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
272 | /* | |
273 | * Check that it's a sync instruction, or somewhere | |
274 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
275 | * As the address is in the exception table | |
276 | * we should be able to read the instr there. | |
277 | * For the debug message, we look at the preceding | |
278 | * load or store. | |
279 | */ | |
280 | if (*nip == 0x60000000) /* nop */ | |
281 | nip -= 2; | |
282 | else if (*nip == 0x4c00012c) /* isync */ | |
283 | --nip; | |
284 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
285 | /* sync or twi */ | |
286 | unsigned int rb; | |
287 | ||
288 | --nip; | |
289 | rb = (*nip >> 11) & 0x1f; | |
290 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
291 | (*nip & 0x100)? "OUT to": "IN from", | |
292 | regs->gpr[rb] - _IO_BASE, nip); | |
293 | regs->msr |= MSR_RI; | |
294 | regs->nip = entry->fixup; | |
295 | return 1; | |
296 | } | |
297 | } | |
68a64357 | 298 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
299 | return 0; |
300 | } | |
301 | ||
302 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
303 | /* On 4xx, the reason for the machine check or program exception | |
304 | is in the ESR. */ | |
305 | #define get_reason(regs) ((regs)->dsisr) | |
306 | #ifndef CONFIG_FSL_BOOKE | |
307 | #define get_mc_reason(regs) ((regs)->dsisr) | |
308 | #else | |
86d7a9a9 | 309 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) |
14cf11af PM |
310 | #endif |
311 | #define REASON_FP ESR_FP | |
312 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
313 | #define REASON_PRIVILEGED ESR_PPR | |
314 | #define REASON_TRAP ESR_PTR | |
315 | ||
316 | /* single-step stuff */ | |
317 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
318 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
319 | ||
320 | #else | |
321 | /* On non-4xx, the reason for the machine check or program | |
322 | exception is in the MSR. */ | |
323 | #define get_reason(regs) ((regs)->msr) | |
324 | #define get_mc_reason(regs) ((regs)->msr) | |
325 | #define REASON_FP 0x100000 | |
326 | #define REASON_ILLEGAL 0x80000 | |
327 | #define REASON_PRIVILEGED 0x40000 | |
328 | #define REASON_TRAP 0x20000 | |
329 | ||
330 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
331 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
332 | #endif | |
333 | ||
47c0bd1a BH |
334 | #if defined(CONFIG_4xx) |
335 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 336 | { |
1a6a4ffe | 337 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 338 | |
14cf11af PM |
339 | if (reason & ESR_IMCP) { |
340 | printk("Instruction"); | |
341 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
342 | } else | |
343 | printk("Data"); | |
344 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
345 | |
346 | return 0; | |
347 | } | |
348 | ||
349 | int machine_check_440A(struct pt_regs *regs) | |
350 | { | |
351 | unsigned long reason = get_mc_reason(regs); | |
352 | ||
14cf11af PM |
353 | printk("Machine check in kernel mode.\n"); |
354 | if (reason & ESR_IMCP){ | |
355 | printk("Instruction Synchronous Machine Check exception\n"); | |
356 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
357 | } | |
358 | else { | |
359 | u32 mcsr = mfspr(SPRN_MCSR); | |
360 | if (mcsr & MCSR_IB) | |
361 | printk("Instruction Read PLB Error\n"); | |
362 | if (mcsr & MCSR_DRB) | |
363 | printk("Data Read PLB Error\n"); | |
364 | if (mcsr & MCSR_DWB) | |
365 | printk("Data Write PLB Error\n"); | |
366 | if (mcsr & MCSR_TLBP) | |
367 | printk("TLB Parity Error\n"); | |
368 | if (mcsr & MCSR_ICP){ | |
369 | flush_instruction_cache(); | |
370 | printk("I-Cache Parity Error\n"); | |
371 | } | |
372 | if (mcsr & MCSR_DCSP) | |
373 | printk("D-Cache Search Parity Error\n"); | |
374 | if (mcsr & MCSR_DCFP) | |
375 | printk("D-Cache Flush Parity Error\n"); | |
376 | if (mcsr & MCSR_IMPE) | |
377 | printk("Machine Check exception is imprecise\n"); | |
378 | ||
379 | /* Clear MCSR */ | |
380 | mtspr(SPRN_MCSR, mcsr); | |
381 | } | |
47c0bd1a BH |
382 | return 0; |
383 | } | |
384 | #elif defined(CONFIG_E500) | |
385 | int machine_check_e500(struct pt_regs *regs) | |
386 | { | |
387 | unsigned long reason = get_mc_reason(regs); | |
388 | ||
14cf11af PM |
389 | printk("Machine check in kernel mode.\n"); |
390 | printk("Caused by (from MCSR=%lx): ", reason); | |
391 | ||
392 | if (reason & MCSR_MCP) | |
393 | printk("Machine Check Signal\n"); | |
394 | if (reason & MCSR_ICPERR) | |
395 | printk("Instruction Cache Parity Error\n"); | |
396 | if (reason & MCSR_DCP_PERR) | |
397 | printk("Data Cache Push Parity Error\n"); | |
398 | if (reason & MCSR_DCPERR) | |
399 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
400 | if (reason & MCSR_BUS_IAERR) |
401 | printk("Bus - Instruction Address Error\n"); | |
402 | if (reason & MCSR_BUS_RAERR) | |
403 | printk("Bus - Read Address Error\n"); | |
404 | if (reason & MCSR_BUS_WAERR) | |
405 | printk("Bus - Write Address Error\n"); | |
406 | if (reason & MCSR_BUS_IBERR) | |
407 | printk("Bus - Instruction Data Error\n"); | |
408 | if (reason & MCSR_BUS_RBERR) | |
409 | printk("Bus - Read Data Bus Error\n"); | |
410 | if (reason & MCSR_BUS_WBERR) | |
411 | printk("Bus - Read Data Bus Error\n"); | |
412 | if (reason & MCSR_BUS_IPERR) | |
413 | printk("Bus - Instruction Parity Error\n"); | |
414 | if (reason & MCSR_BUS_RPERR) | |
415 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
416 | |
417 | return 0; | |
418 | } | |
419 | #elif defined(CONFIG_E200) | |
420 | int machine_check_e200(struct pt_regs *regs) | |
421 | { | |
422 | unsigned long reason = get_mc_reason(regs); | |
423 | ||
14cf11af PM |
424 | printk("Machine check in kernel mode.\n"); |
425 | printk("Caused by (from MCSR=%lx): ", reason); | |
426 | ||
427 | if (reason & MCSR_MCP) | |
428 | printk("Machine Check Signal\n"); | |
429 | if (reason & MCSR_CP_PERR) | |
430 | printk("Cache Push Parity Error\n"); | |
431 | if (reason & MCSR_CPERR) | |
432 | printk("Cache Parity Error\n"); | |
433 | if (reason & MCSR_EXCP_ERR) | |
434 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
435 | if (reason & MCSR_BUS_IRERR) | |
436 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
437 | if (reason & MCSR_BUS_DRERR) | |
438 | printk("Bus - Read Bus Error on data load\n"); | |
439 | if (reason & MCSR_BUS_WRERR) | |
440 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
441 | |
442 | return 0; | |
443 | } | |
444 | #else | |
445 | int machine_check_generic(struct pt_regs *regs) | |
446 | { | |
447 | unsigned long reason = get_mc_reason(regs); | |
448 | ||
14cf11af PM |
449 | printk("Machine check in kernel mode.\n"); |
450 | printk("Caused by (from SRR1=%lx): ", reason); | |
451 | switch (reason & 0x601F0000) { | |
452 | case 0x80000: | |
453 | printk("Machine check signal\n"); | |
454 | break; | |
455 | case 0: /* for 601 */ | |
456 | case 0x40000: | |
457 | case 0x140000: /* 7450 MSS error and TEA */ | |
458 | printk("Transfer error ack signal\n"); | |
459 | break; | |
460 | case 0x20000: | |
461 | printk("Data parity error signal\n"); | |
462 | break; | |
463 | case 0x10000: | |
464 | printk("Address parity error signal\n"); | |
465 | break; | |
466 | case 0x20000000: | |
467 | printk("L1 Data Cache error\n"); | |
468 | break; | |
469 | case 0x40000000: | |
470 | printk("L1 Instruction Cache error\n"); | |
471 | break; | |
472 | case 0x00100000: | |
473 | printk("L2 data cache parity error\n"); | |
474 | break; | |
475 | default: | |
476 | printk("Unknown values in msr\n"); | |
477 | } | |
75918a4b OJ |
478 | return 0; |
479 | } | |
47c0bd1a | 480 | #endif /* everything else */ |
75918a4b OJ |
481 | |
482 | void machine_check_exception(struct pt_regs *regs) | |
483 | { | |
484 | int recover = 0; | |
485 | ||
47c0bd1a BH |
486 | /* See if any machine dependent calls. In theory, we would want |
487 | * to call the CPU first, and call the ppc_md. one if the CPU | |
488 | * one returns a positive number. However there is existing code | |
489 | * that assumes the board gets a first chance, so let's keep it | |
490 | * that way for now and fix things later. --BenH. | |
491 | */ | |
75918a4b OJ |
492 | if (ppc_md.machine_check_exception) |
493 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
494 | else if (cur_cpu_spec->machine_check) |
495 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 496 | |
47c0bd1a | 497 | if (recover > 0) |
75918a4b OJ |
498 | return; |
499 | ||
500 | if (user_mode(regs)) { | |
501 | regs->msr |= MSR_RI; | |
502 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
503 | return; | |
504 | } | |
505 | ||
506 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
47c0bd1a BH |
507 | /* the qspan pci read routines can cause machine checks -- Cort |
508 | * | |
509 | * yuck !!! that totally needs to go away ! There are better ways | |
510 | * to deal with that than having a wart in the mcheck handler. | |
511 | * -- BenH | |
512 | */ | |
75918a4b OJ |
513 | bad_page_fault(regs, regs->dar, SIGBUS); |
514 | return; | |
515 | #endif | |
516 | ||
517 | if (debugger_fault_handler(regs)) { | |
518 | regs->msr |= MSR_RI; | |
519 | return; | |
520 | } | |
521 | ||
522 | if (check_io_access(regs)) | |
523 | return; | |
524 | ||
14cf11af PM |
525 | if (debugger_fault_handler(regs)) |
526 | return; | |
8dad3f92 | 527 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
528 | |
529 | /* Must die if the interrupt is not recoverable */ | |
530 | if (!(regs->msr & MSR_RI)) | |
531 | panic("Unrecoverable Machine check"); | |
532 | } | |
533 | ||
534 | void SMIException(struct pt_regs *regs) | |
535 | { | |
536 | die("System Management Interrupt", regs, SIGABRT); | |
537 | } | |
538 | ||
dc1c1ca3 | 539 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
540 | { |
541 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
542 | regs->nip, regs->msr, regs->trap); | |
543 | ||
544 | _exception(SIGTRAP, regs, 0, 0); | |
545 | } | |
546 | ||
dc1c1ca3 | 547 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
548 | { |
549 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
550 | 5, SIGTRAP) == NOTIFY_STOP) | |
551 | return; | |
552 | if (debugger_iabr_match(regs)) | |
553 | return; | |
554 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
555 | } | |
556 | ||
557 | void RunModeException(struct pt_regs *regs) | |
558 | { | |
559 | _exception(SIGTRAP, regs, 0, 0); | |
560 | } | |
561 | ||
8dad3f92 | 562 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
563 | { |
564 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
565 | ||
566 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
567 | 5, SIGTRAP) == NOTIFY_STOP) | |
568 | return; | |
569 | if (debugger_sstep(regs)) | |
570 | return; | |
571 | ||
572 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
573 | } | |
574 | ||
575 | /* | |
576 | * After we have successfully emulated an instruction, we have to | |
577 | * check if the instruction was being single-stepped, and if so, | |
578 | * pretend we got a single-step exception. This was pointed out | |
579 | * by Kumar Gala. -- paulus | |
580 | */ | |
8dad3f92 | 581 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
582 | { |
583 | if (single_stepping(regs)) { | |
584 | clear_single_step(regs); | |
585 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
586 | } | |
587 | } | |
588 | ||
5fad293b | 589 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 590 | { |
5fad293b | 591 | int ret = 0; |
dc1c1ca3 SR |
592 | |
593 | /* Invalid operation */ | |
594 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 595 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
596 | |
597 | /* Overflow */ | |
598 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 599 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
600 | |
601 | /* Underflow */ | |
602 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 603 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
604 | |
605 | /* Divide by zero */ | |
606 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 607 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
608 | |
609 | /* Inexact result */ | |
610 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
611 | ret = FPE_FLTRES; |
612 | ||
613 | return ret; | |
614 | } | |
615 | ||
616 | static void parse_fpe(struct pt_regs *regs) | |
617 | { | |
618 | int code = 0; | |
619 | ||
620 | flush_fp_to_thread(current); | |
621 | ||
622 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
623 | |
624 | _exception(SIGFPE, regs, code, regs->nip); | |
625 | } | |
626 | ||
627 | /* | |
628 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
629 | * provide the PVR to user applications using the mfspr rd, PVR. |
630 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
631 | * memory access caused an access fault. Return zero on success. | |
632 | * | |
633 | * There are a couple of ways to do this, either "decode" the instruction | |
634 | * or directly match lots of bits. In this case, matching lots of | |
635 | * bits is faster and easier. | |
86417780 | 636 | * |
14cf11af | 637 | */ |
14cf11af PM |
638 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
639 | { | |
640 | u8 rT = (instword >> 21) & 0x1f; | |
641 | u8 rA = (instword >> 16) & 0x1f; | |
642 | u8 NB_RB = (instword >> 11) & 0x1f; | |
643 | u32 num_bytes; | |
644 | unsigned long EA; | |
645 | int pos = 0; | |
646 | ||
647 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 648 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
649 | if ((rT == rA) || (rT == NB_RB)) |
650 | return -EINVAL; | |
651 | ||
652 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
653 | ||
16c57b36 KG |
654 | switch (instword & PPC_INST_STRING_MASK) { |
655 | case PPC_INST_LSWX: | |
656 | case PPC_INST_STSWX: | |
14cf11af PM |
657 | EA += NB_RB; |
658 | num_bytes = regs->xer & 0x7f; | |
659 | break; | |
16c57b36 KG |
660 | case PPC_INST_LSWI: |
661 | case PPC_INST_STSWI: | |
14cf11af PM |
662 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
663 | break; | |
664 | default: | |
665 | return -EINVAL; | |
666 | } | |
667 | ||
668 | while (num_bytes != 0) | |
669 | { | |
670 | u8 val; | |
671 | u32 shift = 8 * (3 - (pos & 0x3)); | |
672 | ||
16c57b36 KG |
673 | switch ((instword & PPC_INST_STRING_MASK)) { |
674 | case PPC_INST_LSWX: | |
675 | case PPC_INST_LSWI: | |
14cf11af PM |
676 | if (get_user(val, (u8 __user *)EA)) |
677 | return -EFAULT; | |
678 | /* first time updating this reg, | |
679 | * zero it out */ | |
680 | if (pos == 0) | |
681 | regs->gpr[rT] = 0; | |
682 | regs->gpr[rT] |= val << shift; | |
683 | break; | |
16c57b36 KG |
684 | case PPC_INST_STSWI: |
685 | case PPC_INST_STSWX: | |
14cf11af PM |
686 | val = regs->gpr[rT] >> shift; |
687 | if (put_user(val, (u8 __user *)EA)) | |
688 | return -EFAULT; | |
689 | break; | |
690 | } | |
691 | /* move EA to next address */ | |
692 | EA += 1; | |
693 | num_bytes--; | |
694 | ||
695 | /* manage our position within the register */ | |
696 | if (++pos == 4) { | |
697 | pos = 0; | |
698 | if (++rT == 32) | |
699 | rT = 0; | |
700 | } | |
701 | } | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
c3412dcb WS |
706 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
707 | { | |
708 | u32 ra,rs; | |
709 | unsigned long tmp; | |
710 | ||
711 | ra = (instword >> 16) & 0x1f; | |
712 | rs = (instword >> 21) & 0x1f; | |
713 | ||
714 | tmp = regs->gpr[rs]; | |
715 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
716 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
717 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
718 | regs->gpr[ra] = tmp; | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
c1469f13 KG |
723 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
724 | { | |
725 | u8 rT = (instword >> 21) & 0x1f; | |
726 | u8 rA = (instword >> 16) & 0x1f; | |
727 | u8 rB = (instword >> 11) & 0x1f; | |
728 | u8 BC = (instword >> 6) & 0x1f; | |
729 | u8 bit; | |
730 | unsigned long tmp; | |
731 | ||
732 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
733 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
734 | ||
735 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
14cf11af PM |
740 | static int emulate_instruction(struct pt_regs *regs) |
741 | { | |
742 | u32 instword; | |
743 | u32 rd; | |
744 | ||
fab5db97 | 745 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
746 | return -EINVAL; |
747 | CHECK_FULL_REGS(regs); | |
748 | ||
749 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
750 | return -EFAULT; | |
751 | ||
752 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 753 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 754 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
755 | rd = (instword >> 21) & 0x1f; |
756 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
757 | return 0; | |
758 | } | |
759 | ||
760 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 761 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 762 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 763 | return 0; |
80947e7c | 764 | } |
14cf11af PM |
765 | |
766 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 767 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 768 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
769 | unsigned long msk = 0xf0000000UL >> shift; |
770 | ||
eecff81d | 771 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
772 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
773 | regs->xer &= ~0xf0000000UL; | |
774 | return 0; | |
775 | } | |
776 | ||
777 | /* Emulate load/store string insn. */ | |
80947e7c | 778 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
eecff81d | 779 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 780 | return emulate_string_inst(regs, instword); |
80947e7c | 781 | } |
14cf11af | 782 | |
c3412dcb | 783 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 784 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 785 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
786 | return emulate_popcntb_inst(regs, instword); |
787 | } | |
788 | ||
c1469f13 | 789 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 790 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 791 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
792 | return emulate_isel(regs, instword); |
793 | } | |
794 | ||
14cf11af PM |
795 | return -EINVAL; |
796 | } | |
797 | ||
73c9ceab | 798 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 799 | { |
73c9ceab | 800 | return is_kernel_addr(addr); |
14cf11af PM |
801 | } |
802 | ||
8dad3f92 | 803 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
804 | { |
805 | unsigned int reason = get_reason(regs); | |
806 | extern int do_mathemu(struct pt_regs *regs); | |
807 | ||
aa42c69c | 808 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 809 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 810 | |
dc1c1ca3 SR |
811 | if (reason & REASON_FP) { |
812 | /* IEEE FP exception */ | |
813 | parse_fpe(regs); | |
8dad3f92 PM |
814 | return; |
815 | } | |
816 | if (reason & REASON_TRAP) { | |
14cf11af | 817 | /* trap exception */ |
dc1c1ca3 SR |
818 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
819 | == NOTIFY_STOP) | |
820 | return; | |
14cf11af PM |
821 | if (debugger_bpt(regs)) |
822 | return; | |
73c9ceab JF |
823 | |
824 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 825 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
826 | regs->nip += 4; |
827 | return; | |
828 | } | |
8dad3f92 PM |
829 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
830 | return; | |
831 | } | |
832 | ||
cd8a5673 PM |
833 | local_irq_enable(); |
834 | ||
04903a30 KG |
835 | #ifdef CONFIG_MATH_EMULATION |
836 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
837 | * but there seems to be a hardware bug on the 405GP (RevD) | |
838 | * that means ESR is sometimes set incorrectly - either to | |
839 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
840 | * hardware people - not sure if it can happen on any illegal | |
841 | * instruction or only on FP instructions, whether there is a | |
842 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
5fad293b KG |
843 | switch (do_mathemu(regs)) { |
844 | case 0: | |
04903a30 KG |
845 | emulate_single_step(regs); |
846 | return; | |
5fad293b KG |
847 | case 1: { |
848 | int code = 0; | |
849 | code = __parse_fpscr(current->thread.fpscr.val); | |
850 | _exception(SIGFPE, regs, code, regs->nip); | |
851 | return; | |
852 | } | |
853 | case -EFAULT: | |
854 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
855 | return; | |
04903a30 | 856 | } |
5fad293b | 857 | /* fall through on any other errors */ |
04903a30 KG |
858 | #endif /* CONFIG_MATH_EMULATION */ |
859 | ||
8dad3f92 PM |
860 | /* Try to emulate it if we should. */ |
861 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
862 | switch (emulate_instruction(regs)) { |
863 | case 0: | |
864 | regs->nip += 4; | |
865 | emulate_single_step(regs); | |
8dad3f92 | 866 | return; |
14cf11af PM |
867 | case -EFAULT: |
868 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 869 | return; |
14cf11af PM |
870 | } |
871 | } | |
8dad3f92 PM |
872 | |
873 | if (reason & REASON_PRIVILEGED) | |
874 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
875 | else | |
876 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
877 | } |
878 | ||
dc1c1ca3 | 879 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 880 | { |
4393c4f6 | 881 | int sig, code, fixed = 0; |
14cf11af | 882 | |
e9370ae1 PM |
883 | /* we don't implement logging of alignment exceptions */ |
884 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
885 | fixed = fix_alignment(regs); | |
14cf11af PM |
886 | |
887 | if (fixed == 1) { | |
888 | regs->nip += 4; /* skip over emulated instruction */ | |
889 | emulate_single_step(regs); | |
890 | return; | |
891 | } | |
892 | ||
dc1c1ca3 | 893 | /* Operand address was bad */ |
14cf11af | 894 | if (fixed == -EFAULT) { |
4393c4f6 BH |
895 | sig = SIGSEGV; |
896 | code = SEGV_ACCERR; | |
897 | } else { | |
898 | sig = SIGBUS; | |
899 | code = BUS_ADRALN; | |
14cf11af | 900 | } |
4393c4f6 BH |
901 | if (user_mode(regs)) |
902 | _exception(sig, regs, code, regs->dar); | |
903 | else | |
904 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
905 | } |
906 | ||
907 | void StackOverflow(struct pt_regs *regs) | |
908 | { | |
909 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
910 | current, regs->gpr[1]); | |
911 | debugger(regs); | |
912 | show_regs(regs); | |
913 | panic("kernel stack overflow"); | |
914 | } | |
915 | ||
916 | void nonrecoverable_exception(struct pt_regs *regs) | |
917 | { | |
918 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
919 | regs->nip, regs->msr); | |
920 | debugger(regs); | |
921 | die("nonrecoverable exception", regs, SIGKILL); | |
922 | } | |
923 | ||
924 | void trace_syscall(struct pt_regs *regs) | |
925 | { | |
926 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 927 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
928 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
929 | } | |
dc1c1ca3 | 930 | |
dc1c1ca3 SR |
931 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
932 | { | |
933 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
934 | "%lx at %lx\n", regs->trap, regs->nip); | |
935 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
936 | } | |
dc1c1ca3 SR |
937 | |
938 | void altivec_unavailable_exception(struct pt_regs *regs) | |
939 | { | |
dc1c1ca3 SR |
940 | if (user_mode(regs)) { |
941 | /* A user program has executed an altivec instruction, | |
942 | but this kernel doesn't support altivec. */ | |
943 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
944 | return; | |
945 | } | |
6c4841c2 | 946 | |
dc1c1ca3 SR |
947 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
948 | "%lx at %lx\n", regs->trap, regs->nip); | |
949 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
950 | } |
951 | ||
ce48b210 MN |
952 | void vsx_unavailable_exception(struct pt_regs *regs) |
953 | { | |
954 | if (user_mode(regs)) { | |
955 | /* A user program has executed an vsx instruction, | |
956 | but this kernel doesn't support vsx. */ | |
957 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
958 | return; | |
959 | } | |
960 | ||
961 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
962 | "%lx at %lx\n", regs->trap, regs->nip); | |
963 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
964 | } | |
965 | ||
dc1c1ca3 SR |
966 | void performance_monitor_exception(struct pt_regs *regs) |
967 | { | |
968 | perf_irq(regs); | |
969 | } | |
dc1c1ca3 | 970 | |
8dad3f92 | 971 | #ifdef CONFIG_8xx |
14cf11af PM |
972 | void SoftwareEmulation(struct pt_regs *regs) |
973 | { | |
974 | extern int do_mathemu(struct pt_regs *); | |
975 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 976 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 977 | int errcode; |
5dd57a13 | 978 | #endif |
14cf11af PM |
979 | |
980 | CHECK_FULL_REGS(regs); | |
981 | ||
982 | if (!user_mode(regs)) { | |
983 | debugger(regs); | |
984 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
985 | } | |
986 | ||
987 | #ifdef CONFIG_MATH_EMULATION | |
988 | errcode = do_mathemu(regs); | |
80947e7c | 989 | if (errcode >= 0) |
eecff81d | 990 | PPC_WARN_EMULATED(math, regs); |
5fad293b KG |
991 | |
992 | switch (errcode) { | |
993 | case 0: | |
994 | emulate_single_step(regs); | |
995 | return; | |
996 | case 1: { | |
997 | int code = 0; | |
998 | code = __parse_fpscr(current->thread.fpscr.val); | |
999 | _exception(SIGFPE, regs, code, regs->nip); | |
1000 | return; | |
1001 | } | |
1002 | case -EFAULT: | |
1003 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1004 | return; | |
1005 | default: | |
1006 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1007 | return; | |
1008 | } | |
1009 | ||
5dd57a13 | 1010 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1011 | errcode = Soft_emulate_8xx(regs); |
80947e7c | 1012 | if (errcode >= 0) |
eecff81d | 1013 | PPC_WARN_EMULATED(8xx, regs); |
80947e7c | 1014 | |
5fad293b KG |
1015 | switch (errcode) { |
1016 | case 0: | |
14cf11af | 1017 | emulate_single_step(regs); |
5fad293b KG |
1018 | return; |
1019 | case 1: | |
1020 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1021 | return; | |
1022 | case -EFAULT: | |
1023 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1024 | return; | |
1025 | } | |
5dd57a13 SW |
1026 | #else |
1027 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1028 | #endif |
14cf11af | 1029 | } |
8dad3f92 | 1030 | #endif /* CONFIG_8xx */ |
14cf11af PM |
1031 | |
1032 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
1033 | ||
f8279621 | 1034 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1035 | { |
ec097c84 RM |
1036 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1037 | * on server, it stops on the target of the branch. In order to simulate | |
1038 | * the server behaviour, we thus restart right away with a single step | |
1039 | * instead of stopping here when hitting a BT | |
1040 | */ | |
1041 | if (debug_status & DBSR_BT) { | |
1042 | regs->msr &= ~MSR_DE; | |
1043 | ||
1044 | /* Disable BT */ | |
1045 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1046 | /* Clear the BT event */ | |
1047 | mtspr(SPRN_DBSR, DBSR_BT); | |
1048 | ||
1049 | /* Do the single step trick only when coming from userspace */ | |
1050 | if (user_mode(regs)) { | |
1051 | current->thread.dbcr0 &= ~DBCR0_BT; | |
1052 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1053 | regs->msr |= MSR_DE; | |
1054 | return; | |
1055 | } | |
1056 | ||
1057 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | |
1058 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1059 | return; | |
1060 | } | |
1061 | if (debugger_sstep(regs)) | |
1062 | return; | |
1063 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1064 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1065 | |
1066 | /* Disable instruction completion */ | |
1067 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1068 | /* Clear the instruction completion event */ | |
1069 | mtspr(SPRN_DBSR, DBSR_IC); | |
1070 | ||
1071 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1072 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1073 | return; | |
1074 | } | |
1075 | ||
1076 | if (debugger_sstep(regs)) | |
1077 | return; | |
1078 | ||
ec097c84 RM |
1079 | if (user_mode(regs)) |
1080 | current->thread.dbcr0 &= ~(DBCR0_IC); | |
f8279621 KG |
1081 | |
1082 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
d6a61bfc LM |
1083 | } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { |
1084 | regs->msr &= ~MSR_DE; | |
1085 | ||
1086 | if (user_mode(regs)) { | |
1087 | current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | | |
1088 | DBCR0_IDM); | |
1089 | } else { | |
1090 | /* Disable DAC interupts */ | |
1091 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R | | |
1092 | DBSR_DAC1W | DBCR0_IDM)); | |
1093 | ||
1094 | /* Clear the DAC event */ | |
1095 | mtspr(SPRN_DBSR, (DBSR_DAC1R | DBSR_DAC1W)); | |
1096 | } | |
1097 | /* Setup and send the trap to the handler */ | |
1098 | do_dabr(regs, mfspr(SPRN_DAC1), debug_status); | |
14cf11af PM |
1099 | } |
1100 | } | |
1101 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
1102 | ||
1103 | #if !defined(CONFIG_TAU_INT) | |
1104 | void TAUException(struct pt_regs *regs) | |
1105 | { | |
1106 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1107 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1108 | } | |
1109 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1110 | |
1111 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1112 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1113 | { |
1114 | int err; | |
1115 | ||
14cf11af PM |
1116 | if (!user_mode(regs)) { |
1117 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1118 | " at %lx\n", regs->nip); | |
8dad3f92 | 1119 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1120 | } |
1121 | ||
dc1c1ca3 | 1122 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1123 | |
eecff81d | 1124 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1125 | err = emulate_altivec(regs); |
1126 | if (err == 0) { | |
1127 | regs->nip += 4; /* skip emulated instruction */ | |
1128 | emulate_single_step(regs); | |
1129 | return; | |
1130 | } | |
1131 | ||
1132 | if (err == -EFAULT) { | |
1133 | /* got an error reading the instruction */ | |
1134 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1135 | } else { | |
1136 | /* didn't recognize the instruction */ | |
1137 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
1138 | if (printk_ratelimit()) | |
1139 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1140 | "in %s at %lx\n", current->comm, regs->nip); | |
1141 | current->thread.vscr.u[3] |= 0x10000; | |
1142 | } | |
1143 | } | |
1144 | #endif /* CONFIG_ALTIVEC */ | |
1145 | ||
ce48b210 MN |
1146 | #ifdef CONFIG_VSX |
1147 | void vsx_assist_exception(struct pt_regs *regs) | |
1148 | { | |
1149 | if (!user_mode(regs)) { | |
1150 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1151 | " at %lx\n", regs->nip); | |
1152 | die("Kernel VSX assist exception", regs, SIGILL); | |
1153 | } | |
1154 | ||
1155 | flush_vsx_to_thread(current); | |
1156 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1157 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1158 | } | |
1159 | #endif /* CONFIG_VSX */ | |
1160 | ||
14cf11af | 1161 | #ifdef CONFIG_FSL_BOOKE |
620165f9 KG |
1162 | |
1163 | void doorbell_exception(struct pt_regs *regs) | |
1164 | { | |
1165 | #ifdef CONFIG_SMP | |
1166 | int cpu = smp_processor_id(); | |
1167 | int msg; | |
1168 | ||
1169 | if (num_online_cpus() < 2) | |
1170 | return; | |
1171 | ||
1172 | for (msg = 0; msg < 4; msg++) | |
1173 | if (test_and_clear_bit(msg, &dbell_smp_message[cpu])) | |
1174 | smp_message_recv(msg); | |
1175 | #else | |
1176 | printk(KERN_WARNING "Received doorbell on non-smp system\n"); | |
1177 | #endif | |
1178 | } | |
1179 | ||
14cf11af PM |
1180 | void CacheLockingException(struct pt_regs *regs, unsigned long address, |
1181 | unsigned long error_code) | |
1182 | { | |
1183 | /* We treat cache locking instructions from the user | |
1184 | * as priv ops, in the future we could try to do | |
1185 | * something smarter | |
1186 | */ | |
1187 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1188 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1189 | return; | |
1190 | } | |
1191 | #endif /* CONFIG_FSL_BOOKE */ | |
1192 | ||
1193 | #ifdef CONFIG_SPE | |
1194 | void SPEFloatingPointException(struct pt_regs *regs) | |
1195 | { | |
6a800f36 | 1196 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1197 | unsigned long spefscr; |
1198 | int fpexc_mode; | |
1199 | int code = 0; | |
6a800f36 LY |
1200 | int err; |
1201 | ||
1202 | preempt_disable(); | |
1203 | if (regs->msr & MSR_SPE) | |
1204 | giveup_spe(current); | |
1205 | preempt_enable(); | |
14cf11af PM |
1206 | |
1207 | spefscr = current->thread.spefscr; | |
1208 | fpexc_mode = current->thread.fpexc_mode; | |
1209 | ||
14cf11af PM |
1210 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1211 | code = FPE_FLTOVF; | |
14cf11af PM |
1212 | } |
1213 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1214 | code = FPE_FLTUND; | |
14cf11af PM |
1215 | } |
1216 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1217 | code = FPE_FLTDIV; | |
1218 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1219 | code = FPE_FLTINV; | |
14cf11af PM |
1220 | } |
1221 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1222 | code = FPE_FLTRES; | |
1223 | ||
6a800f36 LY |
1224 | err = do_spe_mathemu(regs); |
1225 | if (err == 0) { | |
1226 | regs->nip += 4; /* skip emulated instruction */ | |
1227 | emulate_single_step(regs); | |
1228 | return; | |
1229 | } | |
1230 | ||
1231 | if (err == -EFAULT) { | |
1232 | /* got an error reading the instruction */ | |
1233 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1234 | } else if (err == -EINVAL) { | |
1235 | /* didn't recognize the instruction */ | |
1236 | printk(KERN_ERR "unrecognized spe instruction " | |
1237 | "in %s at %lx\n", current->comm, regs->nip); | |
1238 | } else { | |
1239 | _exception(SIGFPE, regs, code, regs->nip); | |
1240 | } | |
14cf11af | 1241 | |
14cf11af PM |
1242 | return; |
1243 | } | |
6a800f36 LY |
1244 | |
1245 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1246 | { | |
1247 | extern int speround_handler(struct pt_regs *regs); | |
1248 | int err; | |
1249 | ||
1250 | preempt_disable(); | |
1251 | if (regs->msr & MSR_SPE) | |
1252 | giveup_spe(current); | |
1253 | preempt_enable(); | |
1254 | ||
1255 | regs->nip -= 4; | |
1256 | err = speround_handler(regs); | |
1257 | if (err == 0) { | |
1258 | regs->nip += 4; /* skip emulated instruction */ | |
1259 | emulate_single_step(regs); | |
1260 | return; | |
1261 | } | |
1262 | ||
1263 | if (err == -EFAULT) { | |
1264 | /* got an error reading the instruction */ | |
1265 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1266 | } else if (err == -EINVAL) { | |
1267 | /* didn't recognize the instruction */ | |
1268 | printk(KERN_ERR "unrecognized spe instruction " | |
1269 | "in %s at %lx\n", current->comm, regs->nip); | |
1270 | } else { | |
1271 | _exception(SIGFPE, regs, 0, regs->nip); | |
1272 | return; | |
1273 | } | |
1274 | } | |
14cf11af PM |
1275 | #endif |
1276 | ||
dc1c1ca3 SR |
1277 | /* |
1278 | * We enter here if we get an unrecoverable exception, that is, one | |
1279 | * that happened at a point where the RI (recoverable interrupt) bit | |
1280 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1281 | * we therefore lost state by taking this exception. | |
1282 | */ | |
1283 | void unrecoverable_exception(struct pt_regs *regs) | |
1284 | { | |
1285 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1286 | regs->trap, regs->nip); | |
1287 | die("Unrecoverable exception", regs, SIGABRT); | |
1288 | } | |
dc1c1ca3 | 1289 | |
14cf11af PM |
1290 | #ifdef CONFIG_BOOKE_WDT |
1291 | /* | |
1292 | * Default handler for a Watchdog exception, | |
1293 | * spins until a reboot occurs | |
1294 | */ | |
1295 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1296 | { | |
1297 | /* Generic WatchdogHandler, implement your own */ | |
1298 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1299 | return; | |
1300 | } | |
1301 | ||
1302 | void WatchdogException(struct pt_regs *regs) | |
1303 | { | |
1304 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1305 | WatchdogHandler(regs); | |
1306 | } | |
1307 | #endif | |
dc1c1ca3 | 1308 | |
dc1c1ca3 SR |
1309 | /* |
1310 | * We enter here if we discover during exception entry that we are | |
1311 | * running in supervisor mode with a userspace value in the stack pointer. | |
1312 | */ | |
1313 | void kernel_bad_stack(struct pt_regs *regs) | |
1314 | { | |
1315 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1316 | regs->gpr[1], regs->nip); | |
1317 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1318 | } | |
14cf11af PM |
1319 | |
1320 | void __init trap_init(void) | |
1321 | { | |
1322 | } | |
80947e7c GU |
1323 | |
1324 | ||
1325 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1326 | ||
1327 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1328 | ||
1329 | struct ppc_emulated ppc_emulated = { | |
1330 | #ifdef CONFIG_ALTIVEC | |
1331 | WARN_EMULATED_SETUP(altivec), | |
1332 | #endif | |
1333 | WARN_EMULATED_SETUP(dcba), | |
1334 | WARN_EMULATED_SETUP(dcbz), | |
1335 | WARN_EMULATED_SETUP(fp_pair), | |
1336 | WARN_EMULATED_SETUP(isel), | |
1337 | WARN_EMULATED_SETUP(mcrxr), | |
1338 | WARN_EMULATED_SETUP(mfpvr), | |
1339 | WARN_EMULATED_SETUP(multiple), | |
1340 | WARN_EMULATED_SETUP(popcntb), | |
1341 | WARN_EMULATED_SETUP(spe), | |
1342 | WARN_EMULATED_SETUP(string), | |
1343 | WARN_EMULATED_SETUP(unaligned), | |
1344 | #ifdef CONFIG_MATH_EMULATION | |
1345 | WARN_EMULATED_SETUP(math), | |
1346 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1347 | WARN_EMULATED_SETUP(8xx), | |
1348 | #endif | |
1349 | #ifdef CONFIG_VSX | |
1350 | WARN_EMULATED_SETUP(vsx), | |
1351 | #endif | |
1352 | }; | |
1353 | ||
1354 | u32 ppc_warn_emulated; | |
1355 | ||
1356 | void ppc_warn_emulated_print(const char *type) | |
1357 | { | |
1358 | if (printk_ratelimit()) | |
1359 | pr_warning("%s used emulated %s instruction\n", current->comm, | |
1360 | type); | |
1361 | } | |
1362 | ||
1363 | static int __init ppc_warn_emulated_init(void) | |
1364 | { | |
1365 | struct dentry *dir, *d; | |
1366 | unsigned int i; | |
1367 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1368 | ||
1369 | if (!powerpc_debugfs_root) | |
1370 | return -ENODEV; | |
1371 | ||
1372 | dir = debugfs_create_dir("emulated_instructions", | |
1373 | powerpc_debugfs_root); | |
1374 | if (!dir) | |
1375 | return -ENOMEM; | |
1376 | ||
1377 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1378 | &ppc_warn_emulated); | |
1379 | if (!d) | |
1380 | goto fail; | |
1381 | ||
1382 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1383 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1384 | (u32 *)&entries[i].val.counter); | |
1385 | if (!d) | |
1386 | goto fail; | |
1387 | } | |
1388 | ||
1389 | return 0; | |
1390 | ||
1391 | fail: | |
1392 | debugfs_remove_recursive(dir); | |
1393 | return -ENOMEM; | |
1394 | } | |
1395 | ||
1396 | device_initcall(ppc_warn_emulated_init); | |
1397 | ||
1398 | #endif /* CONFIG_PPC_EMULATED_STATS */ |