[net-next-2.6.git] / arch / powerpc / kernel / setup_32.c

/*
 * Common prep/pmac/chrp boot and setup code.
 */

#include <linux/module.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include <linux/delay.h>
#include <linux/initrd.h>
#include <linux/tty.h>
#include <linux/bootmem.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/console.h>
#include <linux/lmb.h>

#include <asm/io.h>
#include <asm/prom.h>
#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/setup.h>
#include <asm/smp.h>
#include <asm/elf.h>
#include <asm/cputable.h>
#include <asm/bootx.h>
#include <asm/btext.h>
#include <asm/machdep.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/pmac_feature.h>
#include <asm/sections.h>
#include <asm/nvram.h>
#include <asm/xmon.h>
#include <asm/time.h>
#include <asm/serial.h>
#include <asm/udbg.h>
#include <asm/mmu_context.h>

#include "setup.h"

#define DBG(fmt...)

extern void bootx_init(unsigned long r4, unsigned long phys);

int boot_cpuid;
EXPORT_SYMBOL_GPL(boot_cpuid);
int boot_cpuid_phys;

int smp_hw_index[NR_CPUS];

unsigned long ISA_DMA_THRESHOLD;
unsigned int DMA_MODE_READ;
unsigned int DMA_MODE_WRITE;

#ifdef CONFIG_VGA_CONSOLE
unsigned long vgacon_remap_base;
EXPORT_SYMBOL(vgacon_remap_base);
#endif

/*
 * These are used in binfmt_elf.c to put aux entries on the stack
 * for each elf executable being started.
 */
int dcache_bsize;
int icache_bsize;
int ucache_bsize;

/*
 * We're called here very early in the boot.  We determine the machine
 * type and call the appropriate low-level setup functions.
 *  -- Cort <cort@fsmlabs.com>
 *
 * Note that the kernel may be running at an address which is different
 * from the address that it was linked at, so we must use RELOC/PTRRELOC
 * to access static data (including strings).  -- paulus
 */
notrace unsigned long __init early_init(unsigned long dt_ptr)
{
	unsigned long offset = reloc_offset();
	struct cpu_spec *spec;

	/* First zero the BSS -- use memset_io, some platforms don't have
	 * caches on yet */
	memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
			__bss_stop - __bss_start);

	/*
	 * Identify the CPU type and fix up code sections
	 * that depend on which cpu we have.
	 */
	spec = identify_cpu(offset, mfspr(SPRN_PVR));

	do_feature_fixups(spec->cpu_features,
			  PTRRELOC(&__start___ftr_fixup),
			  PTRRELOC(&__stop___ftr_fixup));

	do_feature_fixups(spec->mmu_features,
			  PTRRELOC(&__start___mmu_ftr_fixup),
			  PTRRELOC(&__stop___mmu_ftr_fixup));

	do_lwsync_fixups(spec->cpu_features,
			 PTRRELOC(&__start___lwsync_fixup),
			 PTRRELOC(&__stop___lwsync_fixup));

	return KERNELBASE + offset;
}


/*
 * Find out what kind of machine we're on and save any data we need
 * from the early boot process (devtree is copied on pmac by prom_init()).
 * This is called very early on the boot process, after a minimal
 * MMU environment has been set up but before MMU_init is called.
 */
notrace void __init machine_init(unsigned long dt_ptr)
{
	lockdep_init();

	/* Enable early debugging if any specified (see udbg.h) */
	udbg_early_init();

	/* Do some early initialization based on the flat device tree */
	early_init_devtree(__va(dt_ptr));

	probe_machine();

	setup_kdump_trampoline();

#ifdef CONFIG_6xx
	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
	    cpu_has_feature(CPU_FTR_CAN_NAP))
		ppc_md.power_save = ppc6xx_idle;
#endif

#ifdef CONFIG_E500
	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
	    cpu_has_feature(CPU_FTR_CAN_NAP))
		ppc_md.power_save = e500_idle;
#endif
	if (ppc_md.progress)
		ppc_md.progress("id mach(): done", 0x200);
}

#ifdef CONFIG_BOOKE_WDT
/* Checks wdt=x and wdt_period=xx command-line option */
notrace int __init early_parse_wdt(char *p)
{
	if (p && strncmp(p, "0", 1) != 0)
	       booke_wdt_enabled = 1;

	return 0;
}
early_param("wdt", early_parse_wdt);

int __init early_parse_wdt_period (char *p)
{
	if (p)
		booke_wdt_period = simple_strtoul(p, NULL, 0);

	return 0;
}
early_param("wdt_period", early_parse_wdt_period);
#endif	/* CONFIG_BOOKE_WDT */

/* Checks "l2cr=xxxx" command-line option */
int __init ppc_setup_l2cr(char *str)
{
	if (cpu_has_feature(CPU_FTR_L2CR)) {
		unsigned long val = simple_strtoul(str, NULL, 0);
		printk(KERN_INFO "l2cr set to %lx\n", val);
		_set_L2CR(0);		/* force invalidate by disable cache */
		_set_L2CR(val);		/* and enable it */
	}
	return 1;
}
__setup("l2cr=", ppc_setup_l2cr);

/* Checks "l3cr=xxxx" command-line option */
int __init ppc_setup_l3cr(char *str)
{
	if (cpu_has_feature(CPU_FTR_L3CR)) {
		unsigned long val = simple_strtoul(str, NULL, 0);
		printk(KERN_INFO "l3cr set to %lx\n", val);
		_set_L3CR(val);		/* and enable it */
	}
	return 1;
}
__setup("l3cr=", ppc_setup_l3cr);

#ifdef CONFIG_GENERIC_NVRAM

/* Generic nvram hooks used by drivers/char/gen_nvram.c */
unsigned char nvram_read_byte(int addr)
{
	if (ppc_md.nvram_read_val)
		return ppc_md.nvram_read_val(addr);
	return 0xff;
}
EXPORT_SYMBOL(nvram_read_byte);

void nvram_write_byte(unsigned char val, int addr)
{
	if (ppc_md.nvram_write_val)
		ppc_md.nvram_write_val(addr, val);
}
EXPORT_SYMBOL(nvram_write_byte);

ssize_t nvram_get_size(void)
{
	if (ppc_md.nvram_size)
		return ppc_md.nvram_size();
	return -1;
}
EXPORT_SYMBOL(nvram_get_size);

void nvram_sync(void)
{
	if (ppc_md.nvram_sync)
		ppc_md.nvram_sync();
}
EXPORT_SYMBOL(nvram_sync);

#endif /* CONFIG_NVRAM */

int __init ppc_init(void)
{
	/* clear the progress line */
	if (ppc_md.progress)
		ppc_md.progress("             ", 0xffff);

	/* call platform init */
	if (ppc_md.init != NULL) {
		ppc_md.init();
	}
	return 0;
}

arch_initcall(ppc_init);

static void __init irqstack_early_init(void)
{
	unsigned int i;

	/* interrupt stacks must be in lowmem, we get that for free on ppc32
	 * as the lmb is limited to lowmem by LMB_REAL_LIMIT */
	for_each_possible_cpu(i) {
		softirq_ctx[i] = (struct thread_info *)
			__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
		hardirq_ctx[i] = (struct thread_info *)
			__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
	}
}

#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
static void __init exc_lvl_early_init(void)
{
	unsigned int i;

	/* interrupt stacks must be in lowmem, we get that for free on ppc32
	 * as the lmb is limited to lowmem by LMB_REAL_LIMIT */
	for_each_possible_cpu(i) {
		critirq_ctx[i] = (struct thread_info *)
			__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
#ifdef CONFIG_BOOKE
		dbgirq_ctx[i] = (struct thread_info *)
			__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
		mcheckirq_ctx[i] = (struct thread_info *)
			__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
#endif
	}
}
#else
#define exc_lvl_early_init()
#endif

/* Warning, IO base is not yet inited */
void __init setup_arch(char **cmdline_p)
{
	*cmdline_p = cmd_line;

	/* so udelay does something sensible, assume <= 1000 bogomips */
	loops_per_jiffy = 500000000 / HZ;

	unflatten_device_tree();
	check_for_initrd();

	if (ppc_md.init_early)
		ppc_md.init_early();

	find_legacy_serial_ports();

	smp_setup_cpu_maps();

	/* Register early console */
	register_early_udbg_console();

	xmon_setup();

	/*
	 * Set cache line size based on type of cpu as a default.
	 * Systems with OF can look in the properties on the cpu node(s)
	 * for a possibly more accurate value.
	 */
	dcache_bsize = cur_cpu_spec->dcache_bsize;
	icache_bsize = cur_cpu_spec->icache_bsize;
	ucache_bsize = 0;
	if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
		ucache_bsize = icache_bsize = dcache_bsize;

	/* reboot on panic */
	panic_timeout = 180;

	if (ppc_md.panic)
		setup_panic();

	init_mm.start_code = (unsigned long)_stext;
	init_mm.end_code = (unsigned long) _etext;
	init_mm.end_data = (unsigned long) _edata;
	init_mm.brk = klimit;

	exc_lvl_early_init();

	irqstack_early_init();

	/* set up the bootmem stuff with available memory */
	do_init_bootmem();
	if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	if (ppc_md.setup_arch)
		ppc_md.setup_arch();
	if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);

	paging_init();

	/* Initialize the MMU context management stuff */
	mmu_context_init();

}
Commit	Line	Data
9b6b563c PM	1	/*
	2	* Common prep/pmac/chrp boot and setup code.
	3	*/
	4
9b6b563c PM	5	#include <linux/module.h>
	6	#include <linux/string.h>
	7	#include <linux/sched.h>
	8	#include <linux/init.h>
	9	#include <linux/kernel.h>
	10	#include <linux/reboot.h>
	11	#include <linux/delay.h>
	12	#include <linux/initrd.h>
9b6b563c PM	13	#include <linux/tty.h>
	14	#include <linux/bootmem.h>
	15	#include <linux/seq_file.h>
	16	#include <linux/root_dev.h>
	17	#include <linux/cpu.h>
	18	#include <linux/console.h>
85218827	19	#include <linux/lmb.h>
9b6b563c	20
9b6b563c PM	21	#include <asm/io.h>
	22	#include <asm/prom.h>
	23	#include <asm/processor.h>
	24	#include <asm/pgtable.h>
9b6b563c	25	#include <asm/setup.h>
9b6b563c PM	26	#include <asm/smp.h>
	27	#include <asm/elf.h>
	28	#include <asm/cputable.h>
	29	#include <asm/bootx.h>
	30	#include <asm/btext.h>
	31	#include <asm/machdep.h>
	32	#include <asm/uaccess.h>
	33	#include <asm/system.h>
	34	#include <asm/pmac_feature.h>
	35	#include <asm/sections.h>
	36	#include <asm/nvram.h>
	37	#include <asm/xmon.h>
6d7f58b0	38	#include <asm/time.h>
463ce0e1	39	#include <asm/serial.h>
51d3082f	40	#include <asm/udbg.h>
77520351	41	#include <asm/mmu_context.h>
9b6b563c	42
66ba135c SR	43	#include "setup.h"
66ba135c SR	44
03501dab PM	45	#define DBG(fmt...)
03501dab PM	46
9b6b563c PM	47	extern void bootx_init(unsigned long r4, unsigned long phys);
9b6b563c PM	48
80579e1f PM	49	int boot_cpuid;
	50	EXPORT_SYMBOL_GPL(boot_cpuid);
	51	int boot_cpuid_phys;
	52
13a9801e NL	53	int smp_hw_index[NR_CPUS];
13a9801e NL	54
9b6b563c PM	55	unsigned long ISA_DMA_THRESHOLD;
	56	unsigned int DMA_MODE_READ;
	57	unsigned int DMA_MODE_WRITE;
	58
9b6b563c PM	59	#ifdef CONFIG_VGA_CONSOLE
9b6b563c PM	60	unsigned long vgacon_remap_base;
d003e7a1	61	EXPORT_SYMBOL(vgacon_remap_base);
9b6b563c PM	62	#endif
9b6b563c PM	63
9b6b563c PM	64	/*
	65	* These are used in binfmt_elf.c to put aux entries on the stack
	66	* for each elf executable being started.
	67	*/
	68	int dcache_bsize;
	69	int icache_bsize;
	70	int ucache_bsize;
	71
9b6b563c PM	72	/*
	73	* We're called here very early in the boot. We determine the machine
	74	* type and call the appropriate low-level setup functions.
	75	* -- Cort <cort@fsmlabs.com>
	76	*
	77	* Note that the kernel may be running at an address which is different
	78	* from the address that it was linked at, so we must use RELOC/PTRRELOC
	79	* to access static data (including strings). -- paulus
	80	*/
4e491d14	81	notrace unsigned long __init early_init(unsigned long dt_ptr)
9b6b563c PM	82	{
9b6b563c PM	83	unsigned long offset = reloc_offset();
42c4aaad	84	struct cpu_spec *spec;
9b6b563c	85
dd184343 PM	86	/* First zero the BSS -- use memset_io, some platforms don't have
dd184343 PM	87	* caches on yet */
556b09c8 MG	88	memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
556b09c8 MG	89	__bss_stop - __bss_start);
dd184343	90
9b6b563c PM	91	/*
	92	* Identify the CPU type and fix up code sections
	93	* that depend on which cpu we have.
	94	*/
974a76f5	95	spec = identify_cpu(offset, mfspr(SPRN_PVR));
42c4aaad	96
0909c8c2	97	do_feature_fixups(spec->cpu_features,
42c4aaad BH	98	PTRRELOC(&__start___ftr_fixup),
42c4aaad BH	99	PTRRELOC(&__stop___ftr_fixup));
9b6b563c	100
7c03d653 BH	101	do_feature_fixups(spec->mmu_features,
	102	PTRRELOC(&__start___mmu_ftr_fixup),
	103	PTRRELOC(&__stop___mmu_ftr_fixup));
	104
2d1b2027 KG	105	do_lwsync_fixups(spec->cpu_features,
	106	PTRRELOC(&__start___lwsync_fixup),
	107	PTRRELOC(&__stop___lwsync_fixup));
	108
9b6b563c PM	109	return KERNELBASE + offset;
	110	}
	111
9b6b563c	112
9b6b563c PM	113	/*
	114	* Find out what kind of machine we're on and save any data we need
	115	* from the early boot process (devtree is copied on pmac by prom_init()).
	116	* This is called very early on the boot process, after a minimal
	117	* MMU environment has been set up but before MMU_init is called.
	118	*/
cd301c7b	119	notrace void __init machine_init(unsigned long dt_ptr)
9b6b563c	120	{
5d38902c BH	121	lockdep_init();
5d38902c BH	122
719c91cc DG	123	/* Enable early debugging if any specified (see udbg.h) */
719c91cc DG	124	udbg_early_init();
51d3082f BH	125
51d3082f BH	126	/* Do some early initialization based on the flat device tree */
9b6b563c PM	127	early_init_devtree(__va(dt_ptr));
9b6b563c PM	128
e8222502	129	probe_machine();
35499c01	130
f8f50b1b DF	131	setup_kdump_trampoline();
f8f50b1b DF	132
9b6b563c	133	#ifdef CONFIG_6xx
a0652fc9 PM	134	if (cpu_has_feature(CPU_FTR_CAN_DOZE) \|\|
	135	cpu_has_feature(CPU_FTR_CAN_NAP))
	136	ppc_md.power_save = ppc6xx_idle;
9b6b563c	137	#endif
9b6b563c	138
fc4033b2 KG	139	#ifdef CONFIG_E500
	140	if (cpu_has_feature(CPU_FTR_CAN_DOZE) \|\|
	141	cpu_has_feature(CPU_FTR_CAN_NAP))
	142	ppc_md.power_save = e500_idle;
	143	#endif
9b6b563c PM	144	if (ppc_md.progress)
	145	ppc_md.progress("id mach(): done", 0x200);
	146	}
	147
	148	#ifdef CONFIG_BOOKE_WDT
	149	/* Checks wdt=x and wdt_period=xx command-line option */
4e491d14	150	notrace int __init early_parse_wdt(char *p)
9b6b563c PM	151	{
	152	if (p && strncmp(p, "0", 1) != 0)
	153	booke_wdt_enabled = 1;
	154
	155	return 0;
	156	}
	157	early_param("wdt", early_parse_wdt);
	158
	159	int __init early_parse_wdt_period (char *p)
	160	{
	161	if (p)
	162	booke_wdt_period = simple_strtoul(p, NULL, 0);
	163
	164	return 0;
	165	}
	166	early_param("wdt_period", early_parse_wdt_period);
	167	#endif /* CONFIG_BOOKE_WDT */
	168
	169	/* Checks "l2cr=xxxx" command-line option */
	170	int __init ppc_setup_l2cr(char *str)
	171	{
	172	if (cpu_has_feature(CPU_FTR_L2CR)) {
	173	unsigned long val = simple_strtoul(str, NULL, 0);
	174	printk(KERN_INFO "l2cr set to %lx\n", val);
	175	_set_L2CR(0); /* force invalidate by disable cache */
	176	_set_L2CR(val); /* and enable it */
	177	}
	178	return 1;
	179	}
	180	__setup("l2cr=", ppc_setup_l2cr);
	181
a78bfbfc RB	182	/* Checks "l3cr=xxxx" command-line option */
	183	int __init ppc_setup_l3cr(char *str)
	184	{
	185	if (cpu_has_feature(CPU_FTR_L3CR)) {
	186	unsigned long val = simple_strtoul(str, NULL, 0);
	187	printk(KERN_INFO "l3cr set to %lx\n", val);
	188	_set_L3CR(val); /* and enable it */
	189	}
	190	return 1;
	191	}
	192	__setup("l3cr=", ppc_setup_l3cr);
	193
9b6b563c PM	194	#ifdef CONFIG_GENERIC_NVRAM
	195
	196	/* Generic nvram hooks used by drivers/char/gen_nvram.c */
	197	unsigned char nvram_read_byte(int addr)
	198	{
	199	if (ppc_md.nvram_read_val)
	200	return ppc_md.nvram_read_val(addr);
	201	return 0xff;
	202	}
	203	EXPORT_SYMBOL(nvram_read_byte);
	204
	205	void nvram_write_byte(unsigned char val, int addr)
	206	{
	207	if (ppc_md.nvram_write_val)
	208	ppc_md.nvram_write_val(addr, val);
	209	}
	210	EXPORT_SYMBOL(nvram_write_byte);
	211
d331d830 MW	212	ssize_t nvram_get_size(void)
	213	{
	214	if (ppc_md.nvram_size)
	215	return ppc_md.nvram_size();
	216	return -1;
	217	}
	218	EXPORT_SYMBOL(nvram_get_size);
	219
9b6b563c PM	220	void nvram_sync(void)
	221	{
	222	if (ppc_md.nvram_sync)
	223	ppc_md.nvram_sync();
	224	}
	225	EXPORT_SYMBOL(nvram_sync);
	226
	227	#endif /* CONFIG_NVRAM */
	228
9b6b563c PM	229	int __init ppc_init(void)
9b6b563c PM	230	{
9b6b563c	231	/* clear the progress line */
5e41763a GP	232	if (ppc_md.progress)
5e41763a GP	233	ppc_md.progress(" ", 0xffff);
9b6b563c	234
9b6b563c PM	235	/* call platform init */
	236	if (ppc_md.init != NULL) {
	237	ppc_md.init();
	238	}
	239	return 0;
	240	}
	241
	242	arch_initcall(ppc_init);
	243
85218827 KG	244	static void __init irqstack_early_init(void)
	245	{
	246	unsigned int i;
	247
	248	/* interrupt stacks must be in lowmem, we get that for free on ppc32
	249	* as the lmb is limited to lowmem by LMB_REAL_LIMIT */
	250	for_each_possible_cpu(i) {
	251	softirq_ctx[i] = (struct thread_info *)
	252	__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
	253	hardirq_ctx[i] = (struct thread_info *)
	254	__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
	255	}
	256	}
85218827	257
bcf0b088 KG	258	#if defined(CONFIG_BOOKE) \|\| defined(CONFIG_40x)
	259	static void __init exc_lvl_early_init(void)
	260	{
	261	unsigned int i;
	262
	263	/* interrupt stacks must be in lowmem, we get that for free on ppc32
	264	* as the lmb is limited to lowmem by LMB_REAL_LIMIT */
	265	for_each_possible_cpu(i) {
	266	critirq_ctx[i] = (struct thread_info *)
	267	__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
	268	#ifdef CONFIG_BOOKE
	269	dbgirq_ctx[i] = (struct thread_info *)
	270	__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
	271	mcheckirq_ctx[i] = (struct thread_info *)
	272	__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
	273	#endif
	274	}
	275	}
	276	#else
	277	#define exc_lvl_early_init()
	278	#endif
	279
9b6b563c PM	280	/* Warning, IO base is not yet inited */
	281	void __init setup_arch(char **cmdline_p)
	282	{
846f77b0 ME	283	*cmdline_p = cmd_line;
846f77b0 ME	284
9b6b563c PM	285	/* so udelay does something sensible, assume <= 1000 bogomips */
	286	loops_per_jiffy = 500000000 / HZ;
	287
9b6b563c	288	unflatten_device_tree();
a82765b6	289	check_for_initrd();
463ce0e1 BH	290
	291	if (ppc_md.init_early)
	292	ppc_md.init_early();
	293
463ce0e1	294	find_legacy_serial_ports();
9b6b563c	295
5ad57078 PM	296	smp_setup_cpu_maps();
5ad57078 PM	297
51d3082f BH	298	/* Register early console */
51d3082f BH	299	register_early_udbg_console();
9b6b563c	300
47679283 ME	301	xmon_setup();
47679283 ME	302
9b6b563c PM	303	/*
	304	* Set cache line size based on type of cpu as a default.
	305	* Systems with OF can look in the properties on the cpu node(s)
	306	* for a possibly more accurate value.
	307	*/
4508dc21 DG	308	dcache_bsize = cur_cpu_spec->dcache_bsize;
	309	icache_bsize = cur_cpu_spec->icache_bsize;
	310	ucache_bsize = 0;
	311	if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
	312	ucache_bsize = icache_bsize = dcache_bsize;
9b6b563c PM	313
	314	/* reboot on panic */
	315	panic_timeout = 180;
	316
7e990266 KG	317	if (ppc_md.panic)
	318	setup_panic();
	319
4846c5de	320	init_mm.start_code = (unsigned long)_stext;
9b6b563c PM	321	init_mm.end_code = (unsigned long) _etext;
9b6b563c PM	322	init_mm.end_data = (unsigned long) _edata;
49b09853	323	init_mm.brk = klimit;
9b6b563c	324
bcf0b088 KG	325	exc_lvl_early_init();
bcf0b088 KG	326
85218827 KG	327	irqstack_early_init();
85218827 KG	328
9b6b563c PM	329	/* set up the bootmem stuff with available memory */
	330	do_init_bootmem();
	331	if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
	332
9b6b563c PM	333	#ifdef CONFIG_DUMMY_CONSOLE
	334	conswitchp = &dummy_con;
	335	#endif
	336
38db7e74 GL	337	if (ppc_md.setup_arch)
38db7e74 GL	338	ppc_md.setup_arch();
9b6b563c PM	339	if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
	340
	341	paging_init();
77520351 BH	342
	343	/* Initialize the MMU context management stuff */
	344	mmu_context_init();
	345
9b6b563c	346	}