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1da177e4 LT |
1 | #ifndef __ASM_SPINLOCK_H |
2 | #define __ASM_SPINLOCK_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
1da177e4 LT |
4 | |
5 | /* | |
6 | * Simple spin lock operations. | |
7 | * | |
8 | * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM | |
9 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
10 | * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM | |
11 | * Rework to support virtual processors | |
12 | * | |
13 | * Type of int is used as a full 64b word is not necessary. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
fb1c8f93 IM |
19 | * |
20 | * (the type definitions are in asm/spinlock_types.h) | |
1da177e4 | 21 | */ |
945feb17 | 22 | #include <linux/irqflags.h> |
0212ddd8 | 23 | #ifdef CONFIG_PPC64 |
1da177e4 LT |
24 | #include <asm/paca.h> |
25 | #include <asm/hvcall.h> | |
1da44037 | 26 | #include <asm/iseries/hv_call.h> |
0212ddd8 PM |
27 | #endif |
28 | #include <asm/asm-compat.h> | |
29 | #include <asm/synch.h> | |
4e14a4d1 | 30 | #include <asm/ppc-opcode.h> |
1da177e4 | 31 | |
0199c4e6 | 32 | #define arch_spin_is_locked(x) ((x)->slock != 0) |
1da177e4 | 33 | |
0212ddd8 PM |
34 | #ifdef CONFIG_PPC64 |
35 | /* use 0x800000yy when locked, where yy == CPU number */ | |
36 | #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token)) | |
37 | #else | |
38 | #define LOCK_TOKEN 1 | |
39 | #endif | |
40 | ||
f007cacf PM |
41 | #if defined(CONFIG_PPC64) && defined(CONFIG_SMP) |
42 | #define CLEAR_IO_SYNC (get_paca()->io_sync = 0) | |
43 | #define SYNC_IO do { \ | |
44 | if (unlikely(get_paca()->io_sync)) { \ | |
45 | mb(); \ | |
46 | get_paca()->io_sync = 0; \ | |
47 | } \ | |
48 | } while (0) | |
49 | #else | |
50 | #define CLEAR_IO_SYNC | |
51 | #define SYNC_IO | |
52 | #endif | |
53 | ||
fb1c8f93 IM |
54 | /* |
55 | * This returns the old value in the lock, so we succeeded | |
56 | * in getting the lock if the return value is 0. | |
57 | */ | |
0199c4e6 | 58 | static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock) |
fb1c8f93 | 59 | { |
0212ddd8 | 60 | unsigned long tmp, token; |
1da177e4 | 61 | |
0212ddd8 | 62 | token = LOCK_TOKEN; |
fb1c8f93 | 63 | __asm__ __volatile__( |
4e14a4d1 | 64 | "1: " PPC_LWARX(%0,0,%2,1) "\n\ |
fb1c8f93 IM |
65 | cmpwi 0,%0,0\n\ |
66 | bne- 2f\n\ | |
67 | stwcx. %1,0,%2\n\ | |
f10e2e5b AB |
68 | bne- 1b\n" |
69 | PPC_ACQUIRE_BARRIER | |
70 | "2:" | |
71 | : "=&r" (tmp) | |
0212ddd8 | 72 | : "r" (token), "r" (&lock->slock) |
fb1c8f93 | 73 | : "cr0", "memory"); |
1da177e4 | 74 | |
fb1c8f93 IM |
75 | return tmp; |
76 | } | |
1da177e4 | 77 | |
0199c4e6 | 78 | static inline int arch_spin_trylock(arch_spinlock_t *lock) |
1da177e4 | 79 | { |
f007cacf | 80 | CLEAR_IO_SYNC; |
0199c4e6 | 81 | return __arch_spin_trylock(lock) == 0; |
1da177e4 LT |
82 | } |
83 | ||
84 | /* | |
85 | * On a system with shared processors (that is, where a physical | |
86 | * processor is multiplexed between several virtual processors), | |
87 | * there is no point spinning on a lock if the holder of the lock | |
88 | * isn't currently scheduled on a physical processor. Instead | |
89 | * we detect this situation and ask the hypervisor to give the | |
90 | * rest of our timeslice to the lock holder. | |
91 | * | |
92 | * So that we can tell which virtual processor is holding a lock, | |
93 | * we put 0x80000000 | smp_processor_id() in the lock when it is | |
94 | * held. Conveniently, we have a word in the paca that holds this | |
95 | * value. | |
96 | */ | |
97 | ||
98 | #if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES) | |
99 | /* We only yield to the hypervisor if we are in shared processor mode */ | |
3356bb9f | 100 | #define SHARED_PROCESSOR (get_lppaca()->shared_proc) |
445c8951 | 101 | extern void __spin_yield(arch_spinlock_t *lock); |
fb3a6bbc | 102 | extern void __rw_yield(arch_rwlock_t *lock); |
1da177e4 LT |
103 | #else /* SPLPAR || ISERIES */ |
104 | #define __spin_yield(x) barrier() | |
105 | #define __rw_yield(x) barrier() | |
106 | #define SHARED_PROCESSOR 0 | |
107 | #endif | |
1da177e4 | 108 | |
0199c4e6 | 109 | static inline void arch_spin_lock(arch_spinlock_t *lock) |
1da177e4 | 110 | { |
f007cacf | 111 | CLEAR_IO_SYNC; |
1da177e4 | 112 | while (1) { |
0199c4e6 | 113 | if (likely(__arch_spin_trylock(lock) == 0)) |
1da177e4 LT |
114 | break; |
115 | do { | |
116 | HMT_low(); | |
117 | if (SHARED_PROCESSOR) | |
118 | __spin_yield(lock); | |
fb1c8f93 | 119 | } while (unlikely(lock->slock != 0)); |
1da177e4 LT |
120 | HMT_medium(); |
121 | } | |
122 | } | |
123 | ||
89b5810f | 124 | static inline |
0199c4e6 | 125 | void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags) |
1da177e4 LT |
126 | { |
127 | unsigned long flags_dis; | |
128 | ||
f007cacf | 129 | CLEAR_IO_SYNC; |
1da177e4 | 130 | while (1) { |
0199c4e6 | 131 | if (likely(__arch_spin_trylock(lock) == 0)) |
1da177e4 LT |
132 | break; |
133 | local_save_flags(flags_dis); | |
134 | local_irq_restore(flags); | |
135 | do { | |
136 | HMT_low(); | |
137 | if (SHARED_PROCESSOR) | |
138 | __spin_yield(lock); | |
fb1c8f93 | 139 | } while (unlikely(lock->slock != 0)); |
1da177e4 LT |
140 | HMT_medium(); |
141 | local_irq_restore(flags_dis); | |
142 | } | |
143 | } | |
144 | ||
0199c4e6 | 145 | static inline void arch_spin_unlock(arch_spinlock_t *lock) |
fb1c8f93 | 146 | { |
f007cacf | 147 | SYNC_IO; |
0199c4e6 | 148 | __asm__ __volatile__("# arch_spin_unlock\n\t" |
f10e2e5b | 149 | PPC_RELEASE_BARRIER: : :"memory"); |
fb1c8f93 IM |
150 | lock->slock = 0; |
151 | } | |
152 | ||
0212ddd8 | 153 | #ifdef CONFIG_PPC64 |
0199c4e6 | 154 | extern void arch_spin_unlock_wait(arch_spinlock_t *lock); |
0212ddd8 | 155 | #else |
0199c4e6 TG |
156 | #define arch_spin_unlock_wait(lock) \ |
157 | do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0) | |
0212ddd8 | 158 | #endif |
fb1c8f93 | 159 | |
1da177e4 LT |
160 | /* |
161 | * Read-write spinlocks, allowing multiple readers | |
162 | * but only one writer. | |
163 | * | |
164 | * NOTE! it is quite common to have readers in interrupts | |
165 | * but no interrupt writers. For those circumstances we | |
166 | * can "mix" irq-safe locks - any writer needs to get a | |
167 | * irq-safe write-lock, but readers can get non-irqsafe | |
168 | * read-locks. | |
169 | */ | |
1da177e4 | 170 | |
e5931943 TG |
171 | #define arch_read_can_lock(rw) ((rw)->lock >= 0) |
172 | #define arch_write_can_lock(rw) (!(rw)->lock) | |
1da177e4 | 173 | |
0212ddd8 PM |
174 | #ifdef CONFIG_PPC64 |
175 | #define __DO_SIGN_EXTEND "extsw %0,%0\n" | |
176 | #define WRLOCK_TOKEN LOCK_TOKEN /* it's negative */ | |
177 | #else | |
178 | #define __DO_SIGN_EXTEND | |
179 | #define WRLOCK_TOKEN (-1) | |
180 | #endif | |
181 | ||
1da177e4 LT |
182 | /* |
183 | * This returns the old value in the lock + 1, | |
184 | * so we got a read lock if the return value is > 0. | |
185 | */ | |
e5931943 | 186 | static inline long __arch_read_trylock(arch_rwlock_t *rw) |
1da177e4 LT |
187 | { |
188 | long tmp; | |
189 | ||
190 | __asm__ __volatile__( | |
4e14a4d1 | 191 | "1: " PPC_LWARX(%0,0,%1,1) "\n" |
0212ddd8 PM |
192 | __DO_SIGN_EXTEND |
193 | " addic. %0,%0,1\n\ | |
194 | ble- 2f\n" | |
195 | PPC405_ERR77(0,%1) | |
196 | " stwcx. %0,0,%1\n\ | |
f10e2e5b AB |
197 | bne- 1b\n" |
198 | PPC_ACQUIRE_BARRIER | |
199 | "2:" : "=&r" (tmp) | |
1da177e4 LT |
200 | : "r" (&rw->lock) |
201 | : "cr0", "xer", "memory"); | |
202 | ||
203 | return tmp; | |
204 | } | |
205 | ||
1da177e4 LT |
206 | /* |
207 | * This returns the old value in the lock, | |
208 | * so we got the write lock if the return value is 0. | |
209 | */ | |
e5931943 | 210 | static inline long __arch_write_trylock(arch_rwlock_t *rw) |
1da177e4 | 211 | { |
0212ddd8 | 212 | long tmp, token; |
1da177e4 | 213 | |
0212ddd8 | 214 | token = WRLOCK_TOKEN; |
1da177e4 | 215 | __asm__ __volatile__( |
4e14a4d1 | 216 | "1: " PPC_LWARX(%0,0,%2,1) "\n\ |
1da177e4 | 217 | cmpwi 0,%0,0\n\ |
0212ddd8 PM |
218 | bne- 2f\n" |
219 | PPC405_ERR77(0,%1) | |
220 | " stwcx. %1,0,%2\n\ | |
f10e2e5b AB |
221 | bne- 1b\n" |
222 | PPC_ACQUIRE_BARRIER | |
223 | "2:" : "=&r" (tmp) | |
0212ddd8 | 224 | : "r" (token), "r" (&rw->lock) |
1da177e4 LT |
225 | : "cr0", "memory"); |
226 | ||
227 | return tmp; | |
228 | } | |
229 | ||
e5931943 | 230 | static inline void arch_read_lock(arch_rwlock_t *rw) |
1da177e4 | 231 | { |
fb1c8f93 | 232 | while (1) { |
e5931943 | 233 | if (likely(__arch_read_trylock(rw) > 0)) |
fb1c8f93 IM |
234 | break; |
235 | do { | |
236 | HMT_low(); | |
237 | if (SHARED_PROCESSOR) | |
238 | __rw_yield(rw); | |
239 | } while (unlikely(rw->lock < 0)); | |
240 | HMT_medium(); | |
241 | } | |
1da177e4 LT |
242 | } |
243 | ||
e5931943 | 244 | static inline void arch_write_lock(arch_rwlock_t *rw) |
1da177e4 LT |
245 | { |
246 | while (1) { | |
e5931943 | 247 | if (likely(__arch_write_trylock(rw) == 0)) |
1da177e4 LT |
248 | break; |
249 | do { | |
250 | HMT_low(); | |
251 | if (SHARED_PROCESSOR) | |
252 | __rw_yield(rw); | |
d637413f | 253 | } while (unlikely(rw->lock != 0)); |
1da177e4 LT |
254 | HMT_medium(); |
255 | } | |
256 | } | |
257 | ||
e5931943 | 258 | static inline int arch_read_trylock(arch_rwlock_t *rw) |
fb1c8f93 | 259 | { |
e5931943 | 260 | return __arch_read_trylock(rw) > 0; |
fb1c8f93 IM |
261 | } |
262 | ||
e5931943 | 263 | static inline int arch_write_trylock(arch_rwlock_t *rw) |
fb1c8f93 | 264 | { |
e5931943 | 265 | return __arch_write_trylock(rw) == 0; |
fb1c8f93 IM |
266 | } |
267 | ||
e5931943 | 268 | static inline void arch_read_unlock(arch_rwlock_t *rw) |
fb1c8f93 IM |
269 | { |
270 | long tmp; | |
271 | ||
272 | __asm__ __volatile__( | |
144b9c13 | 273 | "# read_unlock\n\t" |
f10e2e5b | 274 | PPC_RELEASE_BARRIER |
144b9c13 | 275 | "1: lwarx %0,0,%1\n\ |
0212ddd8 PM |
276 | addic %0,%0,-1\n" |
277 | PPC405_ERR77(0,%1) | |
278 | " stwcx. %0,0,%1\n\ | |
fb1c8f93 IM |
279 | bne- 1b" |
280 | : "=&r"(tmp) | |
281 | : "r"(&rw->lock) | |
efc3624c | 282 | : "cr0", "xer", "memory"); |
fb1c8f93 IM |
283 | } |
284 | ||
e5931943 | 285 | static inline void arch_write_unlock(arch_rwlock_t *rw) |
fb1c8f93 | 286 | { |
144b9c13 | 287 | __asm__ __volatile__("# write_unlock\n\t" |
f10e2e5b | 288 | PPC_RELEASE_BARRIER: : :"memory"); |
fb1c8f93 IM |
289 | rw->lock = 0; |
290 | } | |
291 | ||
e5931943 TG |
292 | #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) |
293 | #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) | |
f5f7eac4 | 294 | |
0199c4e6 TG |
295 | #define arch_spin_relax(lock) __spin_yield(lock) |
296 | #define arch_read_relax(lock) __rw_yield(lock) | |
297 | #define arch_write_relax(lock) __rw_yield(lock) | |
ef6edc97 | 298 | |
88ced031 | 299 | #endif /* __KERNEL__ */ |
1da177e4 | 300 | #endif /* __ASM_SPINLOCK_H */ |