[net-next-2.6.git] / arch / parisc / kernel / pci.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1997, 1998 Ralf Baechle
 * Copyright (C) 1999 SuSE GmbH
 * Copyright (C) 1999-2001 Hewlett-Packard Company
 * Copyright (C) 1999-2001 Grant Grundler
 */
#include <linux/eisa.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/types.h>

#include <asm/io.h>
#include <asm/system.h>
#include <asm/superio.h>

#define DEBUG_RESOURCES 0
#define DEBUG_CONFIG 0

#if DEBUG_CONFIG
# define DBGC(x...)	printk(KERN_DEBUG x)
#else
# define DBGC(x...)
#endif


#if DEBUG_RESOURCES
#define DBG_RES(x...)	printk(KERN_DEBUG x)
#else
#define DBG_RES(x...)
#endif

/* To be used as: mdelay(pci_post_reset_delay);
 *
 * post_reset is the time the kernel should stall to prevent anyone from
 * accessing the PCI bus once #RESET is de-asserted. 
 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
 * this makes the boot time much longer than necessary.
 * 20ms seems to work for all the HP PCI implementations to date.
 *
 * #define pci_post_reset_delay 50
 */

struct pci_port_ops *pci_port __read_mostly;
struct pci_bios_ops *pci_bios __read_mostly;

static int pci_hba_count __read_mostly;

/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data.  */
#define PCI_HBA_MAX 32
static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;


/********************************************************************
**
** I/O port space support
**
*********************************************************************/

/* EISA port numbers and PCI port numbers share the same interface.  Some
 * machines have both EISA and PCI adapters installed.  Rather than turn
 * pci_port into an array, we reserve bus 0 for EISA and call the EISA
 * routines if the access is to a port on bus 0.  We don't want to fix
 * EISA and ISA drivers which assume port space is <= 0xffff.
 */

#ifdef CONFIG_EISA
#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
#else
#define EISA_IN(size)
#define EISA_OUT(size)
#endif

#define PCI_PORT_IN(type, size) \
u##size in##type (int addr) \
{ \
	int b = PCI_PORT_HBA(addr); \
	EISA_IN(size); \
	if (!parisc_pci_hba[b]) return (u##size) -1; \
	return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
} \
EXPORT_SYMBOL(in##type);

PCI_PORT_IN(b,  8)
PCI_PORT_IN(w, 16)
PCI_PORT_IN(l, 32)


#define PCI_PORT_OUT(type, size) \
void out##type (u##size d, int addr) \
{ \
	int b = PCI_PORT_HBA(addr); \
	EISA_OUT(size); \
	if (!parisc_pci_hba[b]) return; \
	pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
} \
EXPORT_SYMBOL(out##type);

PCI_PORT_OUT(b,  8)
PCI_PORT_OUT(w, 16)
PCI_PORT_OUT(l, 32)


/*
 * BIOS32 replacement.
 */
static int __init pcibios_init(void)
{
	if (!pci_bios)
		return -1;

	if (pci_bios->init) {
		pci_bios->init();
	} else {
		printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
	}

	/* Set the CLS for PCI as early as possible. */
	pci_cache_line_size = pci_dfl_cache_line_size;

	return 0;
}


/* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
void pcibios_fixup_bus(struct pci_bus *bus)
{
	if (pci_bios->fixup_bus) {
		pci_bios->fixup_bus(bus);
	} else {
		printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
	}
}


char *pcibios_setup(char *str)
{
	return str;
}

/*
 * Called by pci_set_master() - a driver interface.
 *
 * Legacy PDC guarantees to set:
 *	Map Memory BAR's into PA IO space.
 *	Map Expansion ROM BAR into one common PA IO space per bus.
 *	Map IO BAR's into PCI IO space.
 *	Command (see below)
 *	Cache Line Size
 *	Latency Timer
 *	Interrupt Line
 *	PPB: secondary latency timer, io/mmio base/limit,
 *		bus numbers, bridge control
 *
 */
void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;

	/* If someone already mucked with this, don't touch it. */
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat >= 16) return;

	/*
	** HP generally has fewer devices on the bus than other architectures.
	** upper byte is PCI_LATENCY_TIMER.
	*/
	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
			      (0x80 << 8) | pci_cache_line_size);
}


void __init pcibios_init_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;
	unsigned short bridge_ctl;

	/* We deal only with pci controllers and pci-pci bridges. */
	if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
		return;

	/* PCI-PCI bridge - set the cache line and default latency
	   (32) for primary and secondary buses. */
	pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);

	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
	bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
}

/* called by drivers/pci/setup-bus.c:pci_setup_bridge().  */
void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
		struct pci_bus_region *region, struct resource *res)
{
#ifdef CONFIG_64BIT
	struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
#endif

	if (res->flags & IORESOURCE_IO) {
		/*
		** I/O space may see busnumbers here. Something
		** in the form of 0xbbxxxx where bb is the bus num
		** and xxxx is the I/O port space address.
		** Remaining address translation are done in the
		** PCI Host adapter specific code - ie dino_out8.
		*/
		region->start = PCI_PORT_ADDR(res->start);
		region->end   = PCI_PORT_ADDR(res->end);
	} else if (res->flags & IORESOURCE_MEM) {
		/* Convert MMIO addr to PCI addr (undo global virtualization) */
		region->start = PCI_BUS_ADDR(hba, res->start);
		region->end   = PCI_BUS_ADDR(hba, res->end);
	}

	DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
		dev->bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
		region->start, region->end);
}

void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			      struct pci_bus_region *region)
{
#ifdef CONFIG_64BIT
	struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
#endif

	if (res->flags & IORESOURCE_MEM) {
		res->start = PCI_HOST_ADDR(hba, region->start);
		res->end = PCI_HOST_ADDR(hba, region->end);
	}

	if (res->flags & IORESOURCE_IO) {
		res->start = region->start;
		res->end = region->end;
	}
}

#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
EXPORT_SYMBOL(pcibios_bus_to_resource);
#endif

/*
 * pcibios align resources() is called every time generic PCI code
 * wants to generate a new address. The process of looking for
 * an available address, each candidate is first "aligned" and
 * then checked if the resource is available until a match is found.
 *
 * Since we are just checking candidates, don't use any fields other
 * than res->start.
 */
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
				resource_size_t size, resource_size_t alignment)
{
	resource_size_t mask, align, start = res->start;

	DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
		pci_name(((struct pci_dev *) data)),
		res->parent, res->start, res->end,
		(int) res->flags, size, alignment);

	/* If it's not IO, then it's gotta be MEM */
	align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/* Align to largest of MIN or input size */
	mask = max(alignment, align) - 1;
	start += mask;
	start &= ~mask;

	return start;
}


/*
 * A driver is enabling the device.  We make sure that all the appropriate
 * bits are set to allow the device to operate as the driver is expecting.
 * We enable the port IO and memory IO bits if the device has any BARs of
 * that type, and we enable the PERR and SERR bits unconditionally.
 * Drivers that do not need parity (eg graphics and possibly networking)
 * can clear these bits if they want.
 */
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;
	u16 cmd, old_cmd;

	err = pci_enable_resources(dev, mask);
	if (err < 0)
		return err;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);

#if 0
	/* If bridge/bus controller has FBB enabled, child must too. */
	if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
		cmd |= PCI_COMMAND_FAST_BACK;
#endif

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
			old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}


/* PA-RISC specific */
void pcibios_register_hba(struct pci_hba_data *hba)
{
	if (pci_hba_count >= PCI_HBA_MAX) {
		printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
		return;
	}

	parisc_pci_hba[pci_hba_count] = hba;
	hba->hba_num = pci_hba_count++;
}

subsys_initcall(pcibios_init);
Commit	Line	Data
071327ec	1	/*
1da177e4 LT	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1997, 1998 Ralf Baechle
	7	* Copyright (C) 1999 SuSE GmbH
	8	* Copyright (C) 1999-2001 Hewlett-Packard Company
	9	* Copyright (C) 1999-2001 Grant Grundler
	10	*/
1da177e4 LT	11	#include <linux/eisa.h>
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/pci.h>
1da177e4 LT	16	#include <linux/types.h>
	17
	18	#include <asm/io.h>
	19	#include <asm/system.h>
1da177e4 LT	20	#include <asm/superio.h>
	21
	22	#define DEBUG_RESOURCES 0
	23	#define DEBUG_CONFIG 0
	24
	25	#if DEBUG_CONFIG
	26	# define DBGC(x...) printk(KERN_DEBUG x)
	27	#else
	28	# define DBGC(x...)
	29	#endif
	30
	31
	32	#if DEBUG_RESOURCES
	33	#define DBG_RES(x...) printk(KERN_DEBUG x)
	34	#else
	35	#define DBG_RES(x...)
	36	#endif
	37
	38	/* To be used as: mdelay(pci_post_reset_delay);
	39	*
	40	* post_reset is the time the kernel should stall to prevent anyone from
	41	* accessing the PCI bus once #RESET is de-asserted.
	42	* PCI spec somewhere says 1 second but with multi-PCI bus systems,
	43	* this makes the boot time much longer than necessary.
	44	* 20ms seems to work for all the HP PCI implementations to date.
	45	*
cb6fc18e	46	* #define pci_post_reset_delay 50
1da177e4	47	*/
1da177e4	48
cb6fc18e HD	49	struct pci_port_ops *pci_port __read_mostly;
cb6fc18e HD	50	struct pci_bios_ops *pci_bios __read_mostly;
1da177e4	51
cb6fc18e	52	static int pci_hba_count __read_mostly;
1da177e4 LT	53
	54	/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
	55	#define PCI_HBA_MAX 32
2c9aadab	56	static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
1da177e4 LT	57
	58
	59	/********************************************************************
	60	**
	61	** I/O port space support
	62	**
	63	*********************************************************************/
	64
	65	/* EISA port numbers and PCI port numbers share the same interface. Some
	66	* machines have both EISA and PCI adapters installed. Rather than turn
	67	* pci_port into an array, we reserve bus 0 for EISA and call the EISA
	68	* routines if the access is to a port on bus 0. We don't want to fix
	69	* EISA and ISA drivers which assume port space is <= 0xffff.
	70	*/
	71
	72	#ifdef CONFIG_EISA
	73	#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
	74	#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
	75	#else
	76	#define EISA_IN(size)
	77	#define EISA_OUT(size)
	78	#endif
	79
	80	#define PCI_PORT_IN(type, size) \
	81	u##size in##type (int addr) \
	82	{ \
	83	int b = PCI_PORT_HBA(addr); \
	84	EISA_IN(size); \
	85	if (!parisc_pci_hba[b]) return (u##size) -1; \
	86	return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
	87	} \
	88	EXPORT_SYMBOL(in##type);
	89
	90	PCI_PORT_IN(b, 8)
	91	PCI_PORT_IN(w, 16)
	92	PCI_PORT_IN(l, 32)
	93
	94
	95	#define PCI_PORT_OUT(type, size) \
	96	void out##type (u##size d, int addr) \
	97	{ \
	98	int b = PCI_PORT_HBA(addr); \
	99	EISA_OUT(size); \
	100	if (!parisc_pci_hba[b]) return; \
	101	pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
	102	} \
	103	EXPORT_SYMBOL(out##type);
	104
	105	PCI_PORT_OUT(b, 8)
	106	PCI_PORT_OUT(w, 16)
	107	PCI_PORT_OUT(l, 32)
	108
	109
	110
	111	/*
	112	* BIOS32 replacement.
	113	*/
	114	static int __init pcibios_init(void)
	115	{
	116	if (!pci_bios)
	117	return -1;
	118
	119	if (pci_bios->init) {
	120	pci_bios->init();
121	} else {
122	printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
123	}
5fd4514b CD	124
	125	/* Set the CLS for PCI as early as possible. */
	126	pci_cache_line_size = pci_dfl_cache_line_size;
	127
1da177e4 LT	128	return 0;
	129	}
	130
	131
	132	/* Called from pci_do_scan_bus() after walking a bus but before walking PPBs. */
	133	void pcibios_fixup_bus(struct pci_bus *bus)
	134	{
	135	if (pci_bios->fixup_bus) {
	136	pci_bios->fixup_bus(bus);
	137	} else {
	138	printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
	139	}
	140	}
	141
	142
	143	char pcibios_setup(char str)
	144	{
	145	return str;
	146	}
	147
	148	/*
	149	* Called by pci_set_master() - a driver interface.
	150	*
	151	* Legacy PDC guarantees to set:
	152	* Map Memory BAR's into PA IO space.
	153	* Map Expansion ROM BAR into one common PA IO space per bus.
	154	* Map IO BAR's into PCI IO space.
	155	* Command (see below)
	156	* Cache Line Size
	157	* Latency Timer
	158	* Interrupt Line
	159	* PPB: secondary latency timer, io/mmio base/limit,
	160	* bus numbers, bridge control
	161	*
	162	*/
	163	void pcibios_set_master(struct pci_dev *dev)
	164	{
	165	u8 lat;
	166
	167	/* If someone already mucked with this, don't touch it. */
	168	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	169	if (lat >= 16) return;
	170
	171	/*
	172	** HP generally has fewer devices on the bus than other architectures.
	173	** upper byte is PCI_LATENCY_TIMER.
	174	*/
	175	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
5fd4514b	176	(0x80 << 8) \| pci_cache_line_size);
1da177e4 LT	177	}
	178
	179
	180	void __init pcibios_init_bus(struct pci_bus *bus)
	181	{
	182	struct pci_dev *dev = bus->self;
	183	unsigned short bridge_ctl;
	184
	185	/* We deal only with pci controllers and pci-pci bridges. */
	186	if (!dev \|\| (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
	187	return;
	188
	189	/* PCI-PCI bridge - set the cache line and default latency
	190	(32) for primary and secondary buses. */
	191	pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
	192
	193	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
	194	bridge_ctl \|= PCI_BRIDGE_CTL_PARITY \| PCI_BRIDGE_CTL_SERR;
	195	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
	196	}
	197
1da177e4 LT	198	/* called by drivers/pci/setup-bus.c:pci_setup_bridge(). */
	199	void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
	200	struct pci_bus_region region, struct resource res)
	201	{
7425ada2 KM	202	#ifdef CONFIG_64BIT
	203	struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
	204	#endif
1da177e4 LT	205
	206	if (res->flags & IORESOURCE_IO) {
	207	/*
	208	** I/O space may see busnumbers here. Something
	209	** in the form of 0xbbxxxx where bb is the bus num
	210	** and xxxx is the I/O port space address.
	211	** Remaining address translation are done in the
	212	** PCI Host adapter specific code - ie dino_out8.
	213	*/
	214	region->start = PCI_PORT_ADDR(res->start);
	215	region->end = PCI_PORT_ADDR(res->end);
	216	} else if (res->flags & IORESOURCE_MEM) {
	217	/* Convert MMIO addr to PCI addr (undo global virtualization) */
	218	region->start = PCI_BUS_ADDR(hba, res->start);
	219	region->end = PCI_BUS_ADDR(hba, res->end);
	220	}
	221
	222	DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
7425ada2	223	dev->bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
1da177e4	224	region->start, region->end);
1da177e4 LT	225	}
1da177e4 LT	226
0f94c8e1 DB	227	void pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
	228	struct pci_bus_region *region)
	229	{
96629c0b	230	#ifdef CONFIG_64BIT
7425ada2	231	struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
96629c0b	232	#endif
0f94c8e1 DB	233
	234	if (res->flags & IORESOURCE_MEM) {
	235	res->start = PCI_HOST_ADDR(hba, region->start);
	236	res->end = PCI_HOST_ADDR(hba, region->end);
	237	}
	238
	239	if (res->flags & IORESOURCE_IO) {
	240	res->start = region->start;
	241	res->end = region->end;
	242	}
	243	}
	244
1da177e4 LT	245	#ifdef CONFIG_HOTPLUG
1da177e4 LT	246	EXPORT_SYMBOL(pcibios_resource_to_bus);
0f94c8e1	247	EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 LT	248	#endif
	249
	250	/*
	251	* pcibios align resources() is called every time generic PCI code
	252	* wants to generate a new address. The process of looking for
	253	* an available address, each candidate is first "aligned" and
	254	* then checked if the resource is available until a match is found.
	255	*
	256	* Since we are just checking candidates, don't use any fields other
	257	* than res->start.
	258	*/
3b7a17fc	259	resource_size_t pcibios_align_resource(void data, const struct resource res,
e31dd6e4	260	resource_size_t size, resource_size_t alignment)
1da177e4	261	{
b26b2d49	262	resource_size_t mask, align, start = res->start;
1da177e4 LT	263
	264	DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
	265	pci_name(((struct pci_dev *) data)),
	266	res->parent, res->start, res->end,
	267	(int) res->flags, size, alignment);
	268
	269	/* If it's not IO, then it's gotta be MEM */
	270	align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	271
	272	/* Align to largest of MIN or input size */
	273	mask = max(alignment, align) - 1;
b26b2d49 DB	274	start += mask;
b26b2d49 DB	275	start &= ~mask;
1da177e4	276
b26b2d49	277	return start;
1da177e4 LT	278	}
	279
	280
	281	/*
	282	* A driver is enabling the device. We make sure that all the appropriate
	283	* bits are set to allow the device to operate as the driver is expecting.
	284	* We enable the port IO and memory IO bits if the device has any BARs of
	285	* that type, and we enable the PERR and SERR bits unconditionally.
	286	* Drivers that do not need parity (eg graphics and possibly networking)
	287	* can clear these bits if they want.
	288	*/
	289	int pcibios_enable_device(struct pci_dev *dev, int mask)
	290	{
c9e9e0bf BH	291	int err;
c9e9e0bf BH	292	u16 cmd, old_cmd;
1da177e4	293
c9e9e0bf BH	294	err = pci_enable_resources(dev, mask);
	295	if (err < 0)
	296	return err;
1da177e4	297
c9e9e0bf BH	298	pci_read_config_word(dev, PCI_COMMAND, &cmd);
c9e9e0bf BH	299	old_cmd = cmd;
1da177e4 LT	300
	301	cmd \|= (PCI_COMMAND_SERR \| PCI_COMMAND_PARITY);
	302
	303	#if 0
	304	/* If bridge/bus controller has FBB enabled, child must too. */
	305	if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
	306	cmd \|= PCI_COMMAND_FAST_BACK;
	307	#endif
c9e9e0bf BH	308
	309	if (cmd != old_cmd) {
	310	dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
	311	old_cmd, cmd);
	312	pci_write_config_word(dev, PCI_COMMAND, cmd);
	313	}
1da177e4 LT	314	return 0;
	315	}
	316
	317
	318	/* PA-RISC specific */
	319	void pcibios_register_hba(struct pci_hba_data *hba)
	320	{
	321	if (pci_hba_count >= PCI_HBA_MAX) {
	322	printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
	323	return;
	324	}
	325
	326	parisc_pci_hba[pci_hba_count] = hba;
	327	hba->hba_num = pci_hba_count++;
	328	}
	329
	330	subsys_initcall(pcibios_init);