[net-next-2.6.git] / arch / parisc / kernel / irq.c

/* 
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
 * Copyright (C) 1999-2000 Grant Grundler
 * Copyright (c) 2005 Matthew Wilcox
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/io.h>

#include <asm/smp.h>

#undef PARISC_IRQ_CR16_COUNTS

extern irqreturn_t timer_interrupt(int, void *);
extern irqreturn_t ipi_interrupt(int, void *);

#define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))

/* Bits in EIEM correlate with cpu_irq_action[].
** Numbered *Big Endian*! (ie bit 0 is MSB)
*/
static volatile unsigned long cpu_eiem = 0;

/*
** local ACK bitmap ... habitually set to 1, but reset to zero
** between ->ack() and ->end() of the interrupt to prevent
** re-interruption of a processing interrupt.
*/
static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;

static void cpu_mask_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem &= ~eirr_bit;
	/* Do nothing on the other CPUs.  If they get this interrupt,
	 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	 * handle it, and the set_eiem() at the bottom will ensure it
	 * then gets disabled */
}

static void cpu_unmask_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem |= eirr_bit;

	/* This is just a simple NOP IPI.  But what it does is cause
	 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
	 * of the interrupt handler */
	smp_send_all_nop();
}

void no_ack_irq(unsigned int irq) { }
void no_end_irq(unsigned int irq) { }

void cpu_ack_irq(unsigned int irq)
{
	unsigned long mask = EIEM_MASK(irq);
	int cpu = smp_processor_id();

	/* Clear in EIEM so we can no longer process */
	per_cpu(local_ack_eiem, cpu) &= ~mask;

	/* disable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));

	/* and now ack it */
	mtctl(mask, 23);
}

void cpu_eoi_irq(unsigned int irq)
{
	unsigned long mask = EIEM_MASK(irq);
	int cpu = smp_processor_id();

	/* set it in the eiems---it's no longer in process */
	per_cpu(local_ack_eiem, cpu) |= mask;

	/* enable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
}

#ifdef CONFIG_SMP
int cpu_check_affinity(unsigned int irq, const struct cpumask *dest)
{
	int cpu_dest;

	/* timer and ipi have to always be received on all CPUs */
	if (CHECK_IRQ_PER_CPU(irq)) {
		/* Bad linux design decision.  The mask has already
		 * been set; we must reset it */
		cpumask_setall(irq_desc[irq].affinity);
		return -EINVAL;
	}

	/* whatever mask they set, we just allow one CPU */
	cpu_dest = first_cpu(*dest);

	return cpu_dest;
}

static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
{
	int cpu_dest;

	cpu_dest = cpu_check_affinity(irq, dest);
	if (cpu_dest < 0)
		return -1;

	cpumask_copy(irq_desc[irq].affinity, dest);

	return 0;
}
#endif

static struct irq_chip cpu_interrupt_type = {
	.name		= "CPU",
	.mask		= cpu_mask_irq,
	.unmask		= cpu_unmask_irq,
	.ack		= cpu_ack_irq,
	.eoi		= cpu_eoi_irq,
#ifdef CONFIG_SMP
	.set_affinity	= cpu_set_affinity_irq,
#endif
	/* XXX: Needs to be written.  We managed without it so far, but
	 * we really ought to write it.
	 */
	.retrigger	= NULL,
};

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	unsigned long flags;

	if (i == 0) {
		seq_puts(p, "    ");
		for_each_online_cpu(j)
			seq_printf(p, "       CPU%d", j);

#ifdef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, " [min/avg/max] (CPU cycle counts)");
#endif
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		struct irqaction *action;

		raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
		action = irq_desc[i].action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ", i);
#ifdef CONFIG_SMP
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#else
		seq_printf(p, "%10u ", kstat_irqs(i));
#endif

		seq_printf(p, " %14s", irq_desc[i].chip->name);
#ifndef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, "  %s", action->name);

		while ((action = action->next))
			seq_printf(p, ", %s", action->name);
#else
		for ( ;action; action = action->next) {
			unsigned int k, avg, min, max;

			min = max = action->cr16_hist[0];

			for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
				int hist = action->cr16_hist[k];

				if (hist) {
					avg += hist;
				} else
					break;

				if (hist > max) max = hist;
				if (hist < min) min = hist;
			}

			avg /= k;
			seq_printf(p, " %s[%d/%d/%d]", action->name,
					min,avg,max);
		}
#endif

		seq_putc(p, '\n');
 skip:
		raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	}

	return 0;
}


/*
** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
**
** To use txn_XXX() interfaces, get a Virtual IRQ first.
** Then use that to get the Transaction address and data.
*/

int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
{
	if (irq_desc[irq].action)
		return -EBUSY;
	if (irq_desc[irq].chip != &cpu_interrupt_type)
		return -EBUSY;

	/* for iosapic interrupts */
	if (type) {
		set_irq_chip_and_handler(irq, type, handle_level_irq);
		set_irq_chip_data(irq, data);
		cpu_unmask_irq(irq);
	}
	return 0;
}

int txn_claim_irq(int irq)
{
	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
}

/*
 * The bits_wide parameter accommodates the limitations of the HW/SW which
 * use these bits:
 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 * V-class (EPIC):          6 bits
 * N/L/A-class (iosapic):   8 bits
 * PCI 2.2 MSI:            16 bits
 * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 *
 * On the service provider side:
 * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 * o PA 2.0 wide mode                   6-bits (per processor)
 * o IA64                               8-bits (0-256 total)
 *
 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 * by the processor...and the N/L-class I/O subsystem supports more bits than
 * PA2.0 has. The first case is the problem.
 */
int txn_alloc_irq(unsigned int bits_wide)
{
	int irq;

	/* never return irq 0 cause that's the interval timer */
	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
		if (cpu_claim_irq(irq, NULL, NULL) < 0)
			continue;
		if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
			continue;
		return irq;
	}

	/* unlikely, but be prepared */
	return -1;
}


unsigned long txn_affinity_addr(unsigned int irq, int cpu)
{
#ifdef CONFIG_SMP
	cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu));
#endif

	return per_cpu(cpu_data, cpu).txn_addr;
}


unsigned long txn_alloc_addr(unsigned int virt_irq)
{
	static int next_cpu = -1;

	next_cpu++; /* assign to "next" CPU we want this bugger on */

	/* validate entry */
	while ((next_cpu < nr_cpu_ids) &&
		(!per_cpu(cpu_data, next_cpu).txn_addr ||
		 !cpu_online(next_cpu)))
		next_cpu++;

	if (next_cpu >= nr_cpu_ids) 
		next_cpu = 0;	/* nothing else, assign monarch */

	return txn_affinity_addr(virt_irq, next_cpu);
}


unsigned int txn_alloc_data(unsigned int virt_irq)
{
	return virt_irq - CPU_IRQ_BASE;
}

static inline int eirr_to_irq(unsigned long eirr)
{
	int bit = fls_long(eirr);
	return (BITS_PER_LONG - bit) + TIMER_IRQ;
}

/* ONLY called from entry.S:intr_extint() */
void do_cpu_irq_mask(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	unsigned long eirr_val;
	int irq, cpu = smp_processor_id();
#ifdef CONFIG_SMP
	cpumask_t dest;
#endif

	old_regs = set_irq_regs(regs);
	local_irq_disable();
	irq_enter();

	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
	if (!eirr_val)
		goto set_out;
	irq = eirr_to_irq(eirr_val);

#ifdef CONFIG_SMP
	cpumask_copy(&dest, irq_desc[irq].affinity);
	if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) &&
	    !cpu_isset(smp_processor_id(), dest)) {
		int cpu = first_cpu(dest);

		printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
		       irq, smp_processor_id(), cpu);
		gsc_writel(irq + CPU_IRQ_BASE,
			   per_cpu(cpu_data, cpu).hpa);
		goto set_out;
	}
#endif
	generic_handle_irq(irq);

 out:
	irq_exit();
	set_irq_regs(old_regs);
	return;

 set_out:
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
	goto out;
}

static struct irqaction timer_action = {
	.handler = timer_interrupt,
	.name = "timer",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
};

#ifdef CONFIG_SMP
static struct irqaction ipi_action = {
	.handler = ipi_interrupt,
	.name = "IPI",
	.flags = IRQF_DISABLED | IRQF_PERCPU,
};
#endif

static void claim_cpu_irqs(void)
{
	int i;
	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
		set_irq_chip_and_handler(i, &cpu_interrupt_type,
			handle_level_irq);
	}

	set_irq_handler(TIMER_IRQ, handle_percpu_irq);
	setup_irq(TIMER_IRQ, &timer_action);
#ifdef CONFIG_SMP
	set_irq_handler(IPI_IRQ, handle_percpu_irq);
	setup_irq(IPI_IRQ, &ipi_action);
#endif
}

void __init init_IRQ(void)
{
	local_irq_disable();	/* PARANOID - should already be disabled */
	mtctl(~0UL, 23);	/* EIRR : clear all pending external intr */
	claim_cpu_irqs();
#ifdef CONFIG_SMP
	if (!cpu_eiem)
		cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
#else
	cpu_eiem = EIEM_MASK(TIMER_IRQ);
#endif
        set_eiem(cpu_eiem);	/* EIEM : enable all external intr */

}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	3	*
	4	* Copyright (C) 1992 Linus Torvalds
	5	* Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
	6	* Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
	7	* Copyright (C) 1999-2000 Grant Grundler
	8	* Copyright (c) 2005 Matthew Wilcox
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2, or (at your option)
	13	* any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24	#include <linux/bitops.h>
1da177e4 LT	25	#include <linux/errno.h>
	26	#include <linux/init.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/kernel_stat.h>
	29	#include <linux/seq_file.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/types.h>
c2ab64d0	32	#include <asm/io.h>
1da177e4	33
1d4c452a KM	34	#include <asm/smp.h>
1d4c452a KM	35
1da177e4 LT	36	#undef PARISC_IRQ_CR16_COUNTS
1da177e4 LT	37
be577a52 MW	38	extern irqreturn_t timer_interrupt(int, void *);
be577a52 MW	39	extern irqreturn_t ipi_interrupt(int, void *);
1da177e4 LT	40
	41	#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
	42
	43	/* Bits in EIEM correlate with cpu_irq_action[].
	44	** Numbered Big Endian! (ie bit 0 is MSB)
	45	*/
	46	static volatile unsigned long cpu_eiem = 0;
	47
7085689e	48	/*
462b529f	49	** local ACK bitmap ... habitually set to 1, but reset to zero
7085689e JB	50	** between ->ack() and ->end() of the interrupt to prevent
	51	** re-interruption of a processing interrupt.
	52	*/
7085689e JB	53	static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
7085689e JB	54
4d4f681d	55	static void cpu_mask_irq(unsigned int irq)
1da177e4 LT	56	{
	57	unsigned long eirr_bit = EIEM_MASK(irq);
	58
	59	cpu_eiem &= ~eirr_bit;
d911aed8 JB	60	/* Do nothing on the other CPUs. If they get this interrupt,
	61	* The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	62	* handle it, and the set_eiem() at the bottom will ensure it
	63	* then gets disabled */
1da177e4 LT	64	}
1da177e4 LT	65
4d4f681d	66	static void cpu_unmask_irq(unsigned int irq)
1da177e4 LT	67	{
	68	unsigned long eirr_bit = EIEM_MASK(irq);
	69
1da177e4	70	cpu_eiem \|= eirr_bit;
d911aed8	71
d911aed8 JB	72	/* This is just a simple NOP IPI. But what it does is cause
	73	* all the other CPUs to do a set_eiem(cpu_eiem) at the end
	74	* of the interrupt handler */
	75	smp_send_all_nop();
1da177e4 LT	76	}
1da177e4 LT	77
1da177e4 LT	78	void no_ack_irq(unsigned int irq) { }
	79	void no_end_irq(unsigned int irq) { }
	80
7085689e JB	81	void cpu_ack_irq(unsigned int irq)
	82	{
	83	unsigned long mask = EIEM_MASK(irq);
	84	int cpu = smp_processor_id();
	85
	86	/* Clear in EIEM so we can no longer process */
462b529f	87	per_cpu(local_ack_eiem, cpu) &= ~mask;
7085689e JB	88
7085689e JB	89	/* disable the interrupt */
462b529f GG	90	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
462b529f GG	91
7085689e JB	92	/* and now ack it */
	93	mtctl(mask, 23);
	94	}
	95
4d4f681d	96	void cpu_eoi_irq(unsigned int irq)
7085689e JB	97	{
	98	unsigned long mask = EIEM_MASK(irq);
	99	int cpu = smp_processor_id();
	100
	101	/* set it in the eiems---it's no longer in process */
462b529f	102	per_cpu(local_ack_eiem, cpu) \|= mask;
7085689e JB	103
7085689e JB	104	/* enable the interrupt */
462b529f	105	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	106	}
7085689e JB	107
c2ab64d0	108	#ifdef CONFIG_SMP
8b6649c5	109	int cpu_check_affinity(unsigned int irq, const struct cpumask *dest)
c2ab64d0 JB	110	{
	111	int cpu_dest;
	112
	113	/* timer and ipi have to always be received on all CPUs */
7085689e	114	if (CHECK_IRQ_PER_CPU(irq)) {
c2ab64d0 JB	115	/* Bad linux design decision. The mask has already
c2ab64d0 JB	116	* been set; we must reset it */
47b4150b	117	cpumask_setall(irq_desc[irq].affinity);
c2ab64d0 JB	118	return -EINVAL;
	119	}
	120
	121	/* whatever mask they set, we just allow one CPU */
	122	cpu_dest = first_cpu(*dest);
c2ab64d0	123
8b6649c5	124	return cpu_dest;
c2ab64d0 JB	125	}
c2ab64d0 JB	126
d5dedd45	127	static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
c2ab64d0	128	{
8b6649c5 KM	129	int cpu_dest;
	130
	131	cpu_dest = cpu_check_affinity(irq, dest);
	132	if (cpu_dest < 0)
d5dedd45	133	return -1;
c2ab64d0	134
47b4150b	135	cpumask_copy(irq_desc[irq].affinity, dest);
d5dedd45 YL	136
d5dedd45 YL	137	return 0;
c2ab64d0 JB	138	}
	139	#endif
	140
dfe07565	141	static struct irq_chip cpu_interrupt_type = {
d0608b54	142	.name = "CPU",
4d4f681d KM	143	.mask = cpu_mask_irq,
4d4f681d KM	144	.unmask = cpu_unmask_irq,
7085689e	145	.ack = cpu_ack_irq,
4d4f681d	146	.eoi = cpu_eoi_irq,
c2ab64d0 JB	147	#ifdef CONFIG_SMP
	148	.set_affinity = cpu_set_affinity_irq,
	149	#endif
c0ad90a3 IM	150	/* XXX: Needs to be written. We managed without it so far, but
	151	* we really ought to write it.
	152	*/
	153	.retrigger = NULL,
1da177e4 LT	154	};
	155
	156	int show_interrupts(struct seq_file p, void v)
	157	{
	158	int i = (loff_t ) v, j;
	159	unsigned long flags;
	160
	161	if (i == 0) {
	162	seq_puts(p, " ");
	163	for_each_online_cpu(j)
	164	seq_printf(p, " CPU%d", j);
	165
	166	#ifdef PARISC_IRQ_CR16_COUNTS
	167	seq_printf(p, " [min/avg/max] (CPU cycle counts)");
	168	#endif
	169	seq_putc(p, '\n');
	170	}
	171
	172	if (i < NR_IRQS) {
	173	struct irqaction *action;
	174
239007b8	175	raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
1da177e4 LT	176	action = irq_desc[i].action;
	177	if (!action)
	178	goto skip;
	179	seq_printf(p, "%3d: ", i);
	180	#ifdef CONFIG_SMP
	181	for_each_online_cpu(j)
dee4102a	182	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
1da177e4 LT	183	#else
	184	seq_printf(p, "%10u ", kstat_irqs(i));
	185	#endif
	186
d0608b54	187	seq_printf(p, " %14s", irq_desc[i].chip->name);
1da177e4 LT	188	#ifndef PARISC_IRQ_CR16_COUNTS
	189	seq_printf(p, " %s", action->name);
	190
	191	while ((action = action->next))
	192	seq_printf(p, ", %s", action->name);
	193	#else
	194	for ( ;action; action = action->next) {
	195	unsigned int k, avg, min, max;
	196
	197	min = max = action->cr16_hist[0];
	198
	199	for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
	200	int hist = action->cr16_hist[k];
	201
	202	if (hist) {
	203	avg += hist;
	204	} else
	205	break;
	206
	207	if (hist > max) max = hist;
	208	if (hist < min) min = hist;
	209	}
	210
	211	avg /= k;
	212	seq_printf(p, " %s[%d/%d/%d]", action->name,
	213	min,avg,max);
	214	}
	215	#endif
	216
	217	seq_putc(p, '\n');
	218	skip:
239007b8	219	raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
1da177e4 LT	220	}
	221
	222	return 0;
	223	}
	224
	225
	226
	227	/*
	228	** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
	229	** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
	230	**
	231	** To use txn_XXX() interfaces, get a Virtual IRQ first.
	232	** Then use that to get the Transaction address and data.
	233	*/
	234
5cfe87d3	235	int cpu_claim_irq(unsigned int irq, struct irq_chip type, void data)
1da177e4 LT	236	{
	237	if (irq_desc[irq].action)
	238	return -EBUSY;
d1bef4ed	239	if (irq_desc[irq].chip != &cpu_interrupt_type)
1da177e4 LT	240	return -EBUSY;
1da177e4 LT	241
ba20085c	242	/* for iosapic interrupts */
1da177e4	243	if (type) {
f3d46059	244	set_irq_chip_and_handler(irq, type, handle_level_irq);
ba20085c	245	set_irq_chip_data(irq, data);
4d4f681d	246	cpu_unmask_irq(irq);
1da177e4 LT	247	}
	248	return 0;
	249	}
	250
	251	int txn_claim_irq(int irq)
	252	{
	253	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
	254	}
	255
	256	/*
	257	* The bits_wide parameter accommodates the limitations of the HW/SW which
	258	* use these bits:
	259	* Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
	260	* V-class (EPIC): 6 bits
	261	* N/L/A-class (iosapic): 8 bits
	262	* PCI 2.2 MSI: 16 bits
	263	* Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
	264	*
	265	* On the service provider side:
	266	* o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
	267	* o PA 2.0 wide mode 6-bits (per processor)
	268	* o IA64 8-bits (0-256 total)
	269	*
	270	* So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
	271	* by the processor...and the N/L-class I/O subsystem supports more bits than
	272	* PA2.0 has. The first case is the problem.
	273	*/
	274	int txn_alloc_irq(unsigned int bits_wide)
	275	{
	276	int irq;
	277
	278	/* never return irq 0 cause that's the interval timer */
	279	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
	280	if (cpu_claim_irq(irq, NULL, NULL) < 0)
	281	continue;
	282	if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
	283	continue;
	284	return irq;
	285	}
	286
	287	/* unlikely, but be prepared */
	288	return -1;
	289	}
	290
03afe22f	291
c2ab64d0 JB	292	unsigned long txn_affinity_addr(unsigned int irq, int cpu)
c2ab64d0 JB	293	{
03afe22f	294	#ifdef CONFIG_SMP
47b4150b	295	cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu));
03afe22f	296	#endif
c2ab64d0	297
ef017beb	298	return per_cpu(cpu_data, cpu).txn_addr;
c2ab64d0 JB	299	}
c2ab64d0 JB	300
03afe22f	301
1da177e4 LT	302	unsigned long txn_alloc_addr(unsigned int virt_irq)
	303	{
	304	static int next_cpu = -1;
	305
	306	next_cpu++; /* assign to "next" CPU we want this bugger on */
	307
	308	/* validate entry */
bd071e1a	309	while ((next_cpu < nr_cpu_ids) &&
ef017beb HD	310	(!per_cpu(cpu_data, next_cpu).txn_addr \|\|
ef017beb HD	311	!cpu_online(next_cpu)))
1da177e4 LT	312	next_cpu++;
1da177e4 LT	313
bd071e1a	314	if (next_cpu >= nr_cpu_ids)
1da177e4 LT	315	next_cpu = 0; /* nothing else, assign monarch */
1da177e4 LT	316
c2ab64d0	317	return txn_affinity_addr(virt_irq, next_cpu);
1da177e4 LT	318	}
	319
	320
	321	unsigned int txn_alloc_data(unsigned int virt_irq)
	322	{
	323	return virt_irq - CPU_IRQ_BASE;
	324	}
	325
7085689e JB	326	static inline int eirr_to_irq(unsigned long eirr)
7085689e JB	327	{
0c2de3c6	328	int bit = fls_long(eirr);
7085689e JB	329	return (BITS_PER_LONG - bit) + TIMER_IRQ;
	330	}
	331
1da177e4 LT	332	/* ONLY called from entry.S:intr_extint() */
	333	void do_cpu_irq_mask(struct pt_regs *regs)
	334	{
e11e30a0	335	struct pt_regs *old_regs;
1da177e4	336	unsigned long eirr_val;
7085689e	337	int irq, cpu = smp_processor_id();
03afe22f	338	#ifdef CONFIG_SMP
7085689e	339	cpumask_t dest;
03afe22f	340	#endif
1da177e4	341
e11e30a0	342	old_regs = set_irq_regs(regs);
7085689e JB	343	local_irq_disable();
7085689e JB	344	irq_enter();
1da177e4	345
462b529f	346	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
7085689e JB	347	if (!eirr_val)
	348	goto set_out;
	349	irq = eirr_to_irq(eirr_val);
c2ab64d0	350
7085689e	351	#ifdef CONFIG_SMP
47b4150b	352	cpumask_copy(&dest, irq_desc[irq].affinity);
7085689e JB	353	if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) &&
	354	!cpu_isset(smp_processor_id(), dest)) {
	355	int cpu = first_cpu(dest);
	356
	357	printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
	358	irq, smp_processor_id(), cpu);
	359	gsc_writel(irq + CPU_IRQ_BASE,
ef017beb	360	per_cpu(cpu_data, cpu).hpa);
7085689e	361	goto set_out;
1da177e4	362	}
7085689e	363	#endif
ba20085c	364	generic_handle_irq(irq);
3f902886	365
7085689e	366	out:
1da177e4	367	irq_exit();
e11e30a0	368	set_irq_regs(old_regs);
7085689e	369	return;
1da177e4	370
7085689e	371	set_out:
462b529f	372	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	373	goto out;
7085689e JB	374	}
1da177e4 LT	375
	376	static struct irqaction timer_action = {
	377	.handler = timer_interrupt,
	378	.name = "timer",
57501c70	379	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_PERCPU \| IRQF_IRQPOLL,
1da177e4 LT	380	};
	381
	382	#ifdef CONFIG_SMP
	383	static struct irqaction ipi_action = {
	384	.handler = ipi_interrupt,
	385	.name = "IPI",
7085689e	386	.flags = IRQF_DISABLED \| IRQF_PERCPU,
1da177e4 LT	387	};
	388	#endif
	389
	390	static void claim_cpu_irqs(void)
	391	{
	392	int i;
	393	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
4d4f681d KM	394	set_irq_chip_and_handler(i, &cpu_interrupt_type,
4d4f681d KM	395	handle_level_irq);
1da177e4 LT	396	}
1da177e4 LT	397
ba20085c KM	398	set_irq_handler(TIMER_IRQ, handle_percpu_irq);
ba20085c KM	399	setup_irq(TIMER_IRQ, &timer_action);
1da177e4	400	#ifdef CONFIG_SMP
ba20085c KM	401	set_irq_handler(IPI_IRQ, handle_percpu_irq);
ba20085c KM	402	setup_irq(IPI_IRQ, &ipi_action);
1da177e4 LT	403	#endif
	404	}
	405
	406	void __init init_IRQ(void)
	407	{
	408	local_irq_disable(); /* PARANOID - should already be disabled */
	409	mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
	410	claim_cpu_irqs();
	411	#ifdef CONFIG_SMP
	412	if (!cpu_eiem)
	413	cpu_eiem = EIEM_MASK(IPI_IRQ) \| EIEM_MASK(TIMER_IRQ);
	414	#else
	415	cpu_eiem = EIEM_MASK(TIMER_IRQ);
	416	#endif
	417	set_eiem(cpu_eiem); /* EIEM : enable all external intr */
	418
	419	}
ba20085c	420