[net-next-2.6.git] / arch / parisc / kernel / irq.c

/* 
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
 * Copyright (C) 1999-2000 Grant Grundler
 * Copyright (c) 2005 Matthew Wilcox
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/io.h>

#include <asm/smp.h>

#undef PARISC_IRQ_CR16_COUNTS

extern irqreturn_t timer_interrupt(int, void *);
extern irqreturn_t ipi_interrupt(int, void *);

#define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))

/* Bits in EIEM correlate with cpu_irq_action[].
** Numbered *Big Endian*! (ie bit 0 is MSB)
*/
static volatile unsigned long cpu_eiem = 0;

/*
** local ACK bitmap ... habitually set to 1, but reset to zero
** between ->ack() and ->end() of the interrupt to prevent
** re-interruption of a processing interrupt.
*/
static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;

static void cpu_disable_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem &= ~eirr_bit;
	/* Do nothing on the other CPUs.  If they get this interrupt,
	 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	 * handle it, and the set_eiem() at the bottom will ensure it
	 * then gets disabled */
}

static void cpu_enable_irq(unsigned int irq)
{
	unsigned long eirr_bit = EIEM_MASK(irq);

	cpu_eiem |= eirr_bit;

	/* This is just a simple NOP IPI.  But what it does is cause
	 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
	 * of the interrupt handler */
	smp_send_all_nop();
}

static unsigned int cpu_startup_irq(unsigned int irq)
{
	cpu_enable_irq(irq);
	return 0;
}

void no_ack_irq(unsigned int irq) { }
void no_end_irq(unsigned int irq) { }

void cpu_ack_irq(unsigned int irq)
{
	unsigned long mask = EIEM_MASK(irq);
	int cpu = smp_processor_id();

	/* Clear in EIEM so we can no longer process */
	per_cpu(local_ack_eiem, cpu) &= ~mask;

	/* disable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));

	/* and now ack it */
	mtctl(mask, 23);
}

void cpu_end_irq(unsigned int irq)
{
	unsigned long mask = EIEM_MASK(irq);
	int cpu = smp_processor_id();

	/* set it in the eiems---it's no longer in process */
	per_cpu(local_ack_eiem, cpu) |= mask;

	/* enable the interrupt */
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
}

#ifdef CONFIG_SMP
int cpu_check_affinity(unsigned int irq, const struct cpumask *dest)
{
	int cpu_dest;

	/* timer and ipi have to always be received on all CPUs */
	if (CHECK_IRQ_PER_CPU(irq)) {
		/* Bad linux design decision.  The mask has already
		 * been set; we must reset it */
		cpumask_setall(irq_desc[irq].affinity);
		return -EINVAL;
	}

	/* whatever mask they set, we just allow one CPU */
	cpu_dest = first_cpu(*dest);

	return cpu_dest;
}

static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
{
	int cpu_dest;

	cpu_dest = cpu_check_affinity(irq, dest);
	if (cpu_dest < 0)
		return -1;

	cpumask_copy(irq_desc[irq].affinity, dest);

	return 0;
}
#endif

static struct irq_chip cpu_interrupt_type = {
	.name		= "CPU",
	.startup	= cpu_startup_irq,
	.shutdown	= cpu_disable_irq,
	.enable		= cpu_enable_irq,
	.disable	= cpu_disable_irq,
	.ack		= cpu_ack_irq,
	.end		= cpu_end_irq,
#ifdef CONFIG_SMP
	.set_affinity	= cpu_set_affinity_irq,
#endif
	/* XXX: Needs to be written.  We managed without it so far, but
	 * we really ought to write it.
	 */
	.retrigger	= NULL,
};

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	unsigned long flags;

	if (i == 0) {
		seq_puts(p, "    ");
		for_each_online_cpu(j)
			seq_printf(p, "       CPU%d", j);

#ifdef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, " [min/avg/max] (CPU cycle counts)");
#endif
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		struct irqaction *action;

		raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
		action = irq_desc[i].action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ", i);
#ifdef CONFIG_SMP
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#else
		seq_printf(p, "%10u ", kstat_irqs(i));
#endif

		seq_printf(p, " %14s", irq_desc[i].chip->name);
#ifndef PARISC_IRQ_CR16_COUNTS
		seq_printf(p, "  %s", action->name);

		while ((action = action->next))
			seq_printf(p, ", %s", action->name);
#else
		for ( ;action; action = action->next) {
			unsigned int k, avg, min, max;

			min = max = action->cr16_hist[0];

			for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
				int hist = action->cr16_hist[k];

				if (hist) {
					avg += hist;
				} else
					break;

				if (hist > max) max = hist;
				if (hist < min) min = hist;
			}

			avg /= k;
			seq_printf(p, " %s[%d/%d/%d]", action->name,
					min,avg,max);
		}
#endif

		seq_putc(p, '\n');
 skip:
		raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	}

	return 0;
}


/*
** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
**
** To use txn_XXX() interfaces, get a Virtual IRQ first.
** Then use that to get the Transaction address and data.
*/

int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
{
	if (irq_desc[irq].action)
		return -EBUSY;
	if (irq_desc[irq].chip != &cpu_interrupt_type)
		return -EBUSY;

	if (type) {
		irq_desc[irq].chip = type;
		irq_desc[irq].chip_data = data;
		cpu_interrupt_type.enable(irq);
	}
	return 0;
}

int txn_claim_irq(int irq)
{
	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
}

/*
 * The bits_wide parameter accommodates the limitations of the HW/SW which
 * use these bits:
 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 * V-class (EPIC):          6 bits
 * N/L/A-class (iosapic):   8 bits
 * PCI 2.2 MSI:            16 bits
 * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 *
 * On the service provider side:
 * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 * o PA 2.0 wide mode                   6-bits (per processor)
 * o IA64                               8-bits (0-256 total)
 *
 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 * by the processor...and the N/L-class I/O subsystem supports more bits than
 * PA2.0 has. The first case is the problem.
 */
int txn_alloc_irq(unsigned int bits_wide)
{
	int irq;

	/* never return irq 0 cause that's the interval timer */
	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
		if (cpu_claim_irq(irq, NULL, NULL) < 0)
			continue;
		if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
			continue;
		return irq;
	}

	/* unlikely, but be prepared */
	return -1;
}


unsigned long txn_affinity_addr(unsigned int irq, int cpu)
{
#ifdef CONFIG_SMP
	cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu));
#endif

	return per_cpu(cpu_data, cpu).txn_addr;
}


unsigned long txn_alloc_addr(unsigned int virt_irq)
{
	static int next_cpu = -1;

	next_cpu++; /* assign to "next" CPU we want this bugger on */

	/* validate entry */
	while ((next_cpu < nr_cpu_ids) &&
		(!per_cpu(cpu_data, next_cpu).txn_addr ||
		 !cpu_online(next_cpu)))
		next_cpu++;

	if (next_cpu >= nr_cpu_ids) 
		next_cpu = 0;	/* nothing else, assign monarch */

	return txn_affinity_addr(virt_irq, next_cpu);
}


unsigned int txn_alloc_data(unsigned int virt_irq)
{
	return virt_irq - CPU_IRQ_BASE;
}

static inline int eirr_to_irq(unsigned long eirr)
{
	int bit = fls_long(eirr);
	return (BITS_PER_LONG - bit) + TIMER_IRQ;
}

/* ONLY called from entry.S:intr_extint() */
void do_cpu_irq_mask(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	unsigned long eirr_val;
	int irq, cpu = smp_processor_id();
#ifdef CONFIG_SMP
	cpumask_t dest;
#endif

	old_regs = set_irq_regs(regs);
	local_irq_disable();
	irq_enter();

	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
	if (!eirr_val)
		goto set_out;
	irq = eirr_to_irq(eirr_val);

#ifdef CONFIG_SMP
	cpumask_copy(&dest, irq_desc[irq].affinity);
	if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) &&
	    !cpu_isset(smp_processor_id(), dest)) {
		int cpu = first_cpu(dest);

		printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
		       irq, smp_processor_id(), cpu);
		gsc_writel(irq + CPU_IRQ_BASE,
			   per_cpu(cpu_data, cpu).hpa);
		goto set_out;
	}
#endif
	__do_IRQ(irq);

 out:
	irq_exit();
	set_irq_regs(old_regs);
	return;

 set_out:
	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
	goto out;
}

static struct irqaction timer_action = {
	.handler = timer_interrupt,
	.name = "timer",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
};

#ifdef CONFIG_SMP
static struct irqaction ipi_action = {
	.handler = ipi_interrupt,
	.name = "IPI",
	.flags = IRQF_DISABLED | IRQF_PERCPU,
};
#endif

static void claim_cpu_irqs(void)
{
	int i;
	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
		irq_desc[i].chip = &cpu_interrupt_type;
	}

	irq_desc[TIMER_IRQ].action = &timer_action;
	irq_desc[TIMER_IRQ].status = IRQ_PER_CPU;
#ifdef CONFIG_SMP
	irq_desc[IPI_IRQ].action = &ipi_action;
	irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
#endif
}

void __init init_IRQ(void)
{
	local_irq_disable();	/* PARANOID - should already be disabled */
	mtctl(~0UL, 23);	/* EIRR : clear all pending external intr */
	claim_cpu_irqs();
#ifdef CONFIG_SMP
	if (!cpu_eiem)
		cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
#else
	cpu_eiem = EIEM_MASK(TIMER_IRQ);
#endif
        set_eiem(cpu_eiem);	/* EIEM : enable all external intr */

}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	3	*
	4	* Copyright (C) 1992 Linus Torvalds
	5	* Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
	6	* Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
	7	* Copyright (C) 1999-2000 Grant Grundler
	8	* Copyright (c) 2005 Matthew Wilcox
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2, or (at your option)
	13	* any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24	#include <linux/bitops.h>
1da177e4 LT	25	#include <linux/errno.h>
	26	#include <linux/init.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/kernel_stat.h>
	29	#include <linux/seq_file.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/types.h>
c2ab64d0	32	#include <asm/io.h>
1da177e4	33
1d4c452a KM	34	#include <asm/smp.h>
1d4c452a KM	35
1da177e4 LT	36	#undef PARISC_IRQ_CR16_COUNTS
1da177e4 LT	37
be577a52 MW	38	extern irqreturn_t timer_interrupt(int, void *);
be577a52 MW	39	extern irqreturn_t ipi_interrupt(int, void *);
1da177e4 LT	40
	41	#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
	42
	43	/* Bits in EIEM correlate with cpu_irq_action[].
	44	** Numbered Big Endian! (ie bit 0 is MSB)
	45	*/
	46	static volatile unsigned long cpu_eiem = 0;
	47
7085689e	48	/*
462b529f	49	** local ACK bitmap ... habitually set to 1, but reset to zero
7085689e JB	50	** between ->ack() and ->end() of the interrupt to prevent
	51	** re-interruption of a processing interrupt.
	52	*/
7085689e JB	53	static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
7085689e JB	54
d911aed8	55	static void cpu_disable_irq(unsigned int irq)
1da177e4 LT	56	{
	57	unsigned long eirr_bit = EIEM_MASK(irq);
	58
	59	cpu_eiem &= ~eirr_bit;
d911aed8 JB	60	/* Do nothing on the other CPUs. If they get this interrupt,
	61	* The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
	62	* handle it, and the set_eiem() at the bottom will ensure it
	63	* then gets disabled */
1da177e4 LT	64	}
	65
	66	static void cpu_enable_irq(unsigned int irq)
	67	{
	68	unsigned long eirr_bit = EIEM_MASK(irq);
	69
1da177e4	70	cpu_eiem \|= eirr_bit;
d911aed8	71
d911aed8 JB	72	/* This is just a simple NOP IPI. But what it does is cause
	73	* all the other CPUs to do a set_eiem(cpu_eiem) at the end
	74	* of the interrupt handler */
	75	smp_send_all_nop();
1da177e4 LT	76	}
	77
	78	static unsigned int cpu_startup_irq(unsigned int irq)
	79	{
	80	cpu_enable_irq(irq);
	81	return 0;
	82	}
	83
	84	void no_ack_irq(unsigned int irq) { }
	85	void no_end_irq(unsigned int irq) { }
	86
7085689e JB	87	void cpu_ack_irq(unsigned int irq)
	88	{
	89	unsigned long mask = EIEM_MASK(irq);
	90	int cpu = smp_processor_id();
	91
	92	/* Clear in EIEM so we can no longer process */
462b529f	93	per_cpu(local_ack_eiem, cpu) &= ~mask;
7085689e JB	94
7085689e JB	95	/* disable the interrupt */
462b529f GG	96	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
462b529f GG	97
7085689e JB	98	/* and now ack it */
	99	mtctl(mask, 23);
	100	}
	101
	102	void cpu_end_irq(unsigned int irq)
	103	{
	104	unsigned long mask = EIEM_MASK(irq);
	105	int cpu = smp_processor_id();
	106
	107	/* set it in the eiems---it's no longer in process */
462b529f	108	per_cpu(local_ack_eiem, cpu) \|= mask;
7085689e JB	109
7085689e JB	110	/* enable the interrupt */
462b529f	111	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	112	}
7085689e JB	113
c2ab64d0	114	#ifdef CONFIG_SMP
8b6649c5	115	int cpu_check_affinity(unsigned int irq, const struct cpumask *dest)
c2ab64d0 JB	116	{
	117	int cpu_dest;
	118
	119	/* timer and ipi have to always be received on all CPUs */
7085689e	120	if (CHECK_IRQ_PER_CPU(irq)) {
c2ab64d0 JB	121	/* Bad linux design decision. The mask has already
c2ab64d0 JB	122	* been set; we must reset it */
47b4150b	123	cpumask_setall(irq_desc[irq].affinity);
c2ab64d0 JB	124	return -EINVAL;
	125	}
	126
	127	/* whatever mask they set, we just allow one CPU */
	128	cpu_dest = first_cpu(*dest);
c2ab64d0	129
8b6649c5	130	return cpu_dest;
c2ab64d0 JB	131	}
c2ab64d0 JB	132
d5dedd45	133	static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
c2ab64d0	134	{
8b6649c5 KM	135	int cpu_dest;
	136
	137	cpu_dest = cpu_check_affinity(irq, dest);
	138	if (cpu_dest < 0)
d5dedd45	139	return -1;
c2ab64d0	140
47b4150b	141	cpumask_copy(irq_desc[irq].affinity, dest);
d5dedd45 YL	142
d5dedd45 YL	143	return 0;
c2ab64d0 JB	144	}
	145	#endif
	146
dfe07565	147	static struct irq_chip cpu_interrupt_type = {
d0608b54	148	.name = "CPU",
1da177e4 LT	149	.startup = cpu_startup_irq,
	150	.shutdown = cpu_disable_irq,
	151	.enable = cpu_enable_irq,
	152	.disable = cpu_disable_irq,
7085689e JB	153	.ack = cpu_ack_irq,
7085689e JB	154	.end = cpu_end_irq,
c2ab64d0 JB	155	#ifdef CONFIG_SMP
	156	.set_affinity = cpu_set_affinity_irq,
	157	#endif
c0ad90a3 IM	158	/* XXX: Needs to be written. We managed without it so far, but
	159	* we really ought to write it.
	160	*/
	161	.retrigger = NULL,
1da177e4 LT	162	};
	163
	164	int show_interrupts(struct seq_file p, void v)
	165	{
	166	int i = (loff_t ) v, j;
	167	unsigned long flags;
	168
	169	if (i == 0) {
	170	seq_puts(p, " ");
	171	for_each_online_cpu(j)
	172	seq_printf(p, " CPU%d", j);
	173
	174	#ifdef PARISC_IRQ_CR16_COUNTS
	175	seq_printf(p, " [min/avg/max] (CPU cycle counts)");
	176	#endif
	177	seq_putc(p, '\n');
	178	}
	179
	180	if (i < NR_IRQS) {
	181	struct irqaction *action;
	182
239007b8	183	raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
1da177e4 LT	184	action = irq_desc[i].action;
	185	if (!action)
	186	goto skip;
	187	seq_printf(p, "%3d: ", i);
	188	#ifdef CONFIG_SMP
	189	for_each_online_cpu(j)
dee4102a	190	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
1da177e4 LT	191	#else
	192	seq_printf(p, "%10u ", kstat_irqs(i));
	193	#endif
	194
d0608b54	195	seq_printf(p, " %14s", irq_desc[i].chip->name);
1da177e4 LT	196	#ifndef PARISC_IRQ_CR16_COUNTS
	197	seq_printf(p, " %s", action->name);
	198
	199	while ((action = action->next))
	200	seq_printf(p, ", %s", action->name);
	201	#else
	202	for ( ;action; action = action->next) {
	203	unsigned int k, avg, min, max;
	204
	205	min = max = action->cr16_hist[0];
	206
	207	for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
	208	int hist = action->cr16_hist[k];
	209
	210	if (hist) {
	211	avg += hist;
	212	} else
	213	break;
	214
	215	if (hist > max) max = hist;
	216	if (hist < min) min = hist;
	217	}
	218
	219	avg /= k;
	220	seq_printf(p, " %s[%d/%d/%d]", action->name,
	221	min,avg,max);
	222	}
	223	#endif
	224
	225	seq_putc(p, '\n');
	226	skip:
239007b8	227	raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
1da177e4 LT	228	}
	229
	230	return 0;
	231	}
	232
	233
	234
	235	/*
	236	** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
	237	** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
	238	**
	239	** To use txn_XXX() interfaces, get a Virtual IRQ first.
	240	** Then use that to get the Transaction address and data.
	241	*/
	242
5cfe87d3	243	int cpu_claim_irq(unsigned int irq, struct irq_chip type, void data)
1da177e4 LT	244	{
	245	if (irq_desc[irq].action)
	246	return -EBUSY;
d1bef4ed	247	if (irq_desc[irq].chip != &cpu_interrupt_type)
1da177e4 LT	248	return -EBUSY;
	249
	250	if (type) {
d1bef4ed IM	251	irq_desc[irq].chip = type;
d1bef4ed IM	252	irq_desc[irq].chip_data = data;
1da177e4 LT	253	cpu_interrupt_type.enable(irq);
	254	}
	255	return 0;
	256	}
	257
	258	int txn_claim_irq(int irq)
	259	{
	260	return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
	261	}
	262
	263	/*
	264	* The bits_wide parameter accommodates the limitations of the HW/SW which
	265	* use these bits:
	266	* Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
	267	* V-class (EPIC): 6 bits
	268	* N/L/A-class (iosapic): 8 bits
	269	* PCI 2.2 MSI: 16 bits
	270	* Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
	271	*
	272	* On the service provider side:
	273	* o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
	274	* o PA 2.0 wide mode 6-bits (per processor)
	275	* o IA64 8-bits (0-256 total)
	276	*
	277	* So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
	278	* by the processor...and the N/L-class I/O subsystem supports more bits than
	279	* PA2.0 has. The first case is the problem.
	280	*/
	281	int txn_alloc_irq(unsigned int bits_wide)
	282	{
	283	int irq;
	284
	285	/* never return irq 0 cause that's the interval timer */
	286	for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
	287	if (cpu_claim_irq(irq, NULL, NULL) < 0)
	288	continue;
	289	if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
	290	continue;
	291	return irq;
	292	}
	293
	294	/* unlikely, but be prepared */
	295	return -1;
	296	}
	297
03afe22f	298
c2ab64d0 JB	299	unsigned long txn_affinity_addr(unsigned int irq, int cpu)
c2ab64d0 JB	300	{
03afe22f	301	#ifdef CONFIG_SMP
47b4150b	302	cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu));
03afe22f	303	#endif
c2ab64d0	304
ef017beb	305	return per_cpu(cpu_data, cpu).txn_addr;
c2ab64d0 JB	306	}
c2ab64d0 JB	307
03afe22f	308
1da177e4 LT	309	unsigned long txn_alloc_addr(unsigned int virt_irq)
	310	{
	311	static int next_cpu = -1;
	312
	313	next_cpu++; /* assign to "next" CPU we want this bugger on */
	314
	315	/* validate entry */
bd071e1a	316	while ((next_cpu < nr_cpu_ids) &&
ef017beb HD	317	(!per_cpu(cpu_data, next_cpu).txn_addr \|\|
ef017beb HD	318	!cpu_online(next_cpu)))
1da177e4 LT	319	next_cpu++;
1da177e4 LT	320
bd071e1a	321	if (next_cpu >= nr_cpu_ids)
1da177e4 LT	322	next_cpu = 0; /* nothing else, assign monarch */
1da177e4 LT	323
c2ab64d0	324	return txn_affinity_addr(virt_irq, next_cpu);
1da177e4 LT	325	}
	326
	327
	328	unsigned int txn_alloc_data(unsigned int virt_irq)
	329	{
	330	return virt_irq - CPU_IRQ_BASE;
	331	}
	332
7085689e JB	333	static inline int eirr_to_irq(unsigned long eirr)
7085689e JB	334	{
0c2de3c6	335	int bit = fls_long(eirr);
7085689e JB	336	return (BITS_PER_LONG - bit) + TIMER_IRQ;
	337	}
	338
1da177e4 LT	339	/* ONLY called from entry.S:intr_extint() */
	340	void do_cpu_irq_mask(struct pt_regs *regs)
	341	{
e11e30a0	342	struct pt_regs *old_regs;
1da177e4	343	unsigned long eirr_val;
7085689e	344	int irq, cpu = smp_processor_id();
03afe22f	345	#ifdef CONFIG_SMP
7085689e	346	cpumask_t dest;
03afe22f	347	#endif
1da177e4	348
e11e30a0	349	old_regs = set_irq_regs(regs);
7085689e JB	350	local_irq_disable();
7085689e JB	351	irq_enter();
1da177e4	352
462b529f	353	eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
7085689e JB	354	if (!eirr_val)
	355	goto set_out;
	356	irq = eirr_to_irq(eirr_val);
c2ab64d0	357
7085689e	358	#ifdef CONFIG_SMP
47b4150b	359	cpumask_copy(&dest, irq_desc[irq].affinity);
7085689e JB	360	if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) &&
	361	!cpu_isset(smp_processor_id(), dest)) {
	362	int cpu = first_cpu(dest);
	363
	364	printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
	365	irq, smp_processor_id(), cpu);
	366	gsc_writel(irq + CPU_IRQ_BASE,
ef017beb	367	per_cpu(cpu_data, cpu).hpa);
7085689e	368	goto set_out;
1da177e4	369	}
7085689e	370	#endif
be577a52	371	__do_IRQ(irq);
3f902886	372
7085689e	373	out:
1da177e4	374	irq_exit();
e11e30a0	375	set_irq_regs(old_regs);
7085689e	376	return;
1da177e4	377
7085689e	378	set_out:
462b529f	379	set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
7085689e JB	380	goto out;
7085689e JB	381	}
1da177e4 LT	382
	383	static struct irqaction timer_action = {
	384	.handler = timer_interrupt,
	385	.name = "timer",
57501c70	386	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_PERCPU \| IRQF_IRQPOLL,
1da177e4 LT	387	};
	388
	389	#ifdef CONFIG_SMP
	390	static struct irqaction ipi_action = {
	391	.handler = ipi_interrupt,
	392	.name = "IPI",
7085689e	393	.flags = IRQF_DISABLED \| IRQF_PERCPU,
1da177e4 LT	394	};
	395	#endif
	396
	397	static void claim_cpu_irqs(void)
	398	{
	399	int i;
	400	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
d1bef4ed	401	irq_desc[i].chip = &cpu_interrupt_type;
1da177e4 LT	402	}
	403
	404	irq_desc[TIMER_IRQ].action = &timer_action;
2421ba5b	405	irq_desc[TIMER_IRQ].status = IRQ_PER_CPU;
1da177e4 LT	406	#ifdef CONFIG_SMP
	407	irq_desc[IPI_IRQ].action = &ipi_action;
	408	irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
	409	#endif
	410	}
	411
	412	void __init init_IRQ(void)
	413	{
	414	local_irq_disable(); /* PARANOID - should already be disabled */
	415	mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
	416	claim_cpu_irqs();
	417	#ifdef CONFIG_SMP
	418	if (!cpu_eiem)
	419	cpu_eiem = EIEM_MASK(IPI_IRQ) \| EIEM_MASK(TIMER_IRQ);
	420	#else
	421	cpu_eiem = EIEM_MASK(TIMER_IRQ);
	422	#endif
	423	set_eiem(cpu_eiem); /* EIEM : enable all external intr */
	424
	425	}