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init dynamic bin_attribute structures
[net-next-2.6.git] / arch / mips / txx9 / generic / setup.c
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89d63fe1 1/*
89d63fe1
AN		 2 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
3 * and RBTX49xx patch from CELF patch archive.
4 *
5 * 2003-2005 (c) MontaVista Software, Inc.
6 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
edcaf1a6
AN		 15#include <linux/interrupt.h>
16#include <linux/string.h>
17#include <linux/module.h>
18#include <linux/clk.h>
19#include <linux/err.h>
e0eb7307 20#include <linux/gpio.h>
68314725 21#include <linux/platform_device.h>
7779a5e0 22#include <linux/serial_core.h>
51f607c7 23#include <linux/mtd/physmap.h>
ae027ead 24#include <linux/leds.h>
c3b28ae2 25#include <linux/sysdev.h>
edcaf1a6 26#include <asm/bootinfo.h>
e0eb7307 27#include <asm/time.h>
a49297e8 28#include <asm/reboot.h>
d10e025f 29#include <asm/r4kcache.h>
b6263ff2 30#include <asm/sections.h>
89d63fe1 31#include <asm/txx9/generic.h>
07517529 32#include <asm/txx9/pci.h>
496a3b5c 33#include <asm/txx9tmr.h>
a591f5d3 34#include <asm/txx9/ndfmc.h>
f48c8c95 35#include <asm/txx9/dmac.h>
edcaf1a6
AN		 36#ifdef CONFIG_CPU_TX49XX
37#include <asm/txx9/tx4938.h>
38#endif
89d63fe1
AN		 39
40/* EBUSC settings of TX4927, etc. */
41struct resource txx9_ce_res[8];
42static char txx9_ce_res_name[8][4]; /* "CEn" */
43
44/* pcode, internal register */
94a4c329 45unsigned int txx9_pcode;
89d63fe1
AN		 46char txx9_pcode_str[8];
47static struct resource txx9_reg_res = {
48 .name = txx9_pcode_str,
49 .flags = IORESOURCE_MEM,
50};
51void __init
52txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
53{
54 int i;
55
56 for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
57 sprintf(txx9_ce_res_name[i], "CE%d", i);
58 txx9_ce_res[i].flags = IORESOURCE_MEM;
59 txx9_ce_res[i].name = txx9_ce_res_name[i];
60 }
61
073828d0 62 txx9_pcode = pcode;
89d63fe1
AN		 63 sprintf(txx9_pcode_str, "TX%x", pcode);
64 if (base) {
65 txx9_reg_res.start = base & 0xfffffffffULL;
66 txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
67 request_resource(&iomem_resource, &txx9_reg_res);
68 }
69}
70
71/* clocks */
72unsigned int txx9_master_clock;
73unsigned int txx9_cpu_clock;
74unsigned int txx9_gbus_clock;
edcaf1a6 75
c7b95bcb
AN		 76#ifdef CONFIG_CPU_TX39XX
77/* don't enable by default - see errata */
78int txx9_ccfg_toeon __initdata;
79#else
94a4c329 80int txx9_ccfg_toeon __initdata = 1;
c7b95bcb 81#endif
edcaf1a6
AN		 82
83/* Minimum CLK support */
84
85struct clk *clk_get(struct device *dev, const char *id)
86{
87 if (!strcmp(id, "spi-baseclk"))
fcc152f3 88 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2);
edcaf1a6 89 if (!strcmp(id, "imbus_clk"))
94a4c329 90 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
edcaf1a6
AN		 91 return ERR_PTR(-ENOENT);
92}
93EXPORT_SYMBOL(clk_get);
94
95int clk_enable(struct clk *clk)
96{
97 return 0;
98}
99EXPORT_SYMBOL(clk_enable);
100
101void clk_disable(struct clk *clk)
102{
103}
104EXPORT_SYMBOL(clk_disable);
105
106unsigned long clk_get_rate(struct clk *clk)
107{
108 return (unsigned long)clk;
109}
110EXPORT_SYMBOL(clk_get_rate);
111
112void clk_put(struct clk *clk)
113{
114}
115EXPORT_SYMBOL(clk_put);
116
8d795f2a
AN		 117/* GPIO support */
118
119#ifdef CONFIG_GENERIC_GPIO
120int gpio_to_irq(unsigned gpio)
121{
122 return -EINVAL;
123}
124EXPORT_SYMBOL(gpio_to_irq);
125
126int irq_to_gpio(unsigned irq)
127{
128 return -EINVAL;
129}
130EXPORT_SYMBOL(irq_to_gpio);
131#endif
132
860e546c
AN		 133#define BOARD_VEC(board) extern struct txx9_board_vec board;
134#include <asm/txx9/boards.h>
135#undef BOARD_VEC
edcaf1a6 136
edcaf1a6
AN		 137struct txx9_board_vec *txx9_board_vec __initdata;
138static char txx9_system_type[32];
139
860e546c
AN		 140static struct txx9_board_vec *board_vecs[] __initdata = {
141#define BOARD_VEC(board) &board,
142#include <asm/txx9/boards.h>
143#undef BOARD_VEC
144};
145
146static struct txx9_board_vec *__init find_board_byname(const char *name)
147{
148 int i;
149
150 /* search board_vecs table */
151 for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
152 if (strstr(board_vecs[i]->system, name))
153 return board_vecs[i];
154 }
155 return NULL;
156}
157
e0dfb20c 158static void __init prom_init_cmdline(void)
edcaf1a6 159{
97b0511c
GU		 160 int argc;
161 int *argv32;
edcaf1a6
AN		 162 int i; /* Always ignore the "-c" at argv[0] */
163
97b0511c
GU		 164 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
165 /*
166 * argc is not a valid number, or argv32 is not a valid
167 * pointer
168 */
169 argc = 0;
170 argv32 = NULL;
171 } else {
172 argc = (int)fw_arg0;
173 argv32 = (int *)fw_arg1;
174 }
175
e0dfb20c 176 arcs_cmdline[0] = '\0';
edcaf1a6
AN		 177
178 for (i = 1; i < argc; i++) {
e0dfb20c 179 char *str = (char *)(long)argv32[i];
edcaf1a6
AN		 180 if (i != 1)
181 strcat(arcs_cmdline, " ");
e0dfb20c
AN		 182 if (strchr(str, ' ')) {
183 strcat(arcs_cmdline, "\"");
184 strcat(arcs_cmdline, str);
185 strcat(arcs_cmdline, "\"");
186 } else
187 strcat(arcs_cmdline, str);
188 }
edcaf1a6
AN		 189}
190
d10e025f
AN		 191static int txx9_ic_disable __initdata;
192static int txx9_dc_disable __initdata;
193
194#if defined(CONFIG_CPU_TX49XX)
195/* flush all cache on very early stage (before 4k_cache_init) */
196static void __init early_flush_dcache(void)
197{
198 unsigned int conf = read_c0_config();
199 unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
200 unsigned int linesz = 32;
201 unsigned long addr, end;
202
203 end = INDEX_BASE + dc_size / 4;
204 /* 4way, waybit=0 */
205 for (addr = INDEX_BASE; addr < end; addr += linesz) {
206 cache_op(Index_Writeback_Inv_D, addr | 0);
207 cache_op(Index_Writeback_Inv_D, addr | 1);
208 cache_op(Index_Writeback_Inv_D, addr | 2);
209 cache_op(Index_Writeback_Inv_D, addr | 3);
210 }
211}
212
213static void __init txx9_cache_fixup(void)
214{
215 unsigned int conf;
216
217 conf = read_c0_config();
218 /* flush and disable */
219 if (txx9_ic_disable) {
220 conf |= TX49_CONF_IC;
221 write_c0_config(conf);
222 }
223 if (txx9_dc_disable) {
224 early_flush_dcache();
225 conf |= TX49_CONF_DC;
226 write_c0_config(conf);
227 }
228
229 /* enable cache */
230 conf = read_c0_config();
231 if (!txx9_ic_disable)
232 conf &= ~TX49_CONF_IC;
233 if (!txx9_dc_disable)
234 conf &= ~TX49_CONF_DC;
235 write_c0_config(conf);
236
237 if (conf & TX49_CONF_IC)
238 pr_info("TX49XX I-Cache disabled.\n");
239 if (conf & TX49_CONF_DC)
240 pr_info("TX49XX D-Cache disabled.\n");
241}
242#elif defined(CONFIG_CPU_TX39XX)
243/* flush all cache on very early stage (before tx39_cache_init) */
244static void __init early_flush_dcache(void)
245{
246 unsigned int conf = read_c0_config();
247 unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
248 TX39_CONF_DCS_SHIFT));
249 unsigned int linesz = 16;
250 unsigned long addr, end;
251
252 end = INDEX_BASE + dc_size / 2;
253 /* 2way, waybit=0 */
254 for (addr = INDEX_BASE; addr < end; addr += linesz) {
255 cache_op(Index_Writeback_Inv_D, addr | 0);
256 cache_op(Index_Writeback_Inv_D, addr | 1);
257 }
258}
259
260static void __init txx9_cache_fixup(void)
261{
262 unsigned int conf;
263
264 conf = read_c0_config();
265 /* flush and disable */
266 if (txx9_ic_disable) {
267 conf &= ~TX39_CONF_ICE;
268 write_c0_config(conf);
269 }
270 if (txx9_dc_disable) {
271 early_flush_dcache();
272 conf &= ~TX39_CONF_DCE;
273 write_c0_config(conf);
274 }
275
276 /* enable cache */
277 conf = read_c0_config();
278 if (!txx9_ic_disable)
279 conf |= TX39_CONF_ICE;
280 if (!txx9_dc_disable)
281 conf |= TX39_CONF_DCE;
282 write_c0_config(conf);
283
284 if (!(conf & TX39_CONF_ICE))
285 pr_info("TX39XX I-Cache disabled.\n");
286 if (!(conf & TX39_CONF_DCE))
287 pr_info("TX39XX D-Cache disabled.\n");
288}
289#else
290static inline void txx9_cache_fixup(void)
291{
292}
293#endif
294
860e546c 295static void __init preprocess_cmdline(void)
edcaf1a6 296{
7580c9c3 297 static char cmdline[COMMAND_LINE_SIZE] __initdata;
860e546c
AN		 298 char *s;
299
300 strcpy(cmdline, arcs_cmdline);
301 s = cmdline;
302 arcs_cmdline[0] = '\0';
303 while (s && *s) {
304 char *str = strsep(&s, " ");
305 if (strncmp(str, "board=", 6) == 0) {
306 txx9_board_vec = find_board_byname(str + 6);
307 continue;
308 } else if (strncmp(str, "masterclk=", 10) == 0) {
309 unsigned long val;
310 if (strict_strtoul(str + 10, 10, &val) == 0)
311 txx9_master_clock = val;
312 continue;
d10e025f
AN		 313 } else if (strcmp(str, "icdisable") == 0) {
314 txx9_ic_disable = 1;
315 continue;
316 } else if (strcmp(str, "dcdisable") == 0) {
317 txx9_dc_disable = 1;
318 continue;
c7b95bcb
AN		 319 } else if (strcmp(str, "toeoff") == 0) {
320 txx9_ccfg_toeon = 0;
321 continue;
322 } else if (strcmp(str, "toeon") == 0) {
323 txx9_ccfg_toeon = 1;
324 continue;
860e546c
AN		 325 }
326 if (arcs_cmdline[0])
327 strcat(arcs_cmdline, " ");
328 strcat(arcs_cmdline, str);
329 }
d10e025f
AN		 330
331 txx9_cache_fixup();
860e546c
AN		 332}
333
334static void __init select_board(void)
335{
336 const char *envstr;
337
338 /* first, determine by "board=" argument in preprocess_cmdline() */
339 if (txx9_board_vec)
340 return;
341 /* next, determine by "board" envvar */
342 envstr = prom_getenv("board");
343 if (envstr) {
344 txx9_board_vec = find_board_byname(envstr);
345 if (txx9_board_vec)
346 return;
347 }
348
349 /* select "default" board */
edcaf1a6 350#ifdef CONFIG_CPU_TX39XX
7a1fdf19 351 txx9_board_vec = &jmr3927_vec;
edcaf1a6
AN		 352#endif
353#ifdef CONFIG_CPU_TX49XX
354 switch (TX4938_REV_PCODE()) {
8d795f2a 355#ifdef CONFIG_TOSHIBA_RBTX4927
edcaf1a6 356 case 0x4927:
7a1fdf19 357 txx9_board_vec = &rbtx4927_vec;
edcaf1a6
AN		 358 break;
359 case 0x4937:
7a1fdf19 360 txx9_board_vec = &rbtx4937_vec;
edcaf1a6 361 break;
8d795f2a
AN		 362#endif
363#ifdef CONFIG_TOSHIBA_RBTX4938
edcaf1a6 364 case 0x4938:
7a1fdf19 365 txx9_board_vec = &rbtx4938_vec;
edcaf1a6 366 break;
b27311e1
AN		 367#endif
368#ifdef CONFIG_TOSHIBA_RBTX4939
369 case 0x4939:
370 txx9_board_vec = &rbtx4939_vec;
371 break;
8d795f2a 372#endif
edcaf1a6
AN		 373 }
374#endif
860e546c
AN		 375}
376
377void __init prom_init(void)
378{
379 prom_init_cmdline();
380 preprocess_cmdline();
381 select_board();
7a1fdf19
YY		 382
383 strcpy(txx9_system_type, txx9_board_vec->system);
384
7b226094 385 txx9_board_vec->prom_init();
edcaf1a6
AN		 386}
387
388void __init prom_free_prom_memory(void)
389{
b6263ff2
AN		 390 unsigned long saddr = PAGE_SIZE;
391 unsigned long eaddr = __pa_symbol(&_text);
392
393 if (saddr < eaddr)
394 free_init_pages("prom memory", saddr, eaddr);
edcaf1a6
AN		 395}
396
397const char *get_system_type(void)
398{
399 return txx9_system_type;
400}
401
265b89db
AN		 402const char *__init prom_getenv(const char *name)
403{
97b0511c 404 const s32 *str;
265b89db 405
97b0511c 406 if (fw_arg2 < CKSEG0)
265b89db 407 return NULL;
97b0511c
GU		 408
409 str = (const s32 *)fw_arg2;
265b89db
AN		 410 /* YAMON style ("name", "value" pairs) */
411 while (str[0] && str[1]) {
412 if (!strcmp((const char *)(unsigned long)str[0], name))
413 return (const char *)(unsigned long)str[1];
414 str += 2;
415 }
416 return NULL;
417}
418
a49297e8
AN		 419static void __noreturn txx9_machine_halt(void)
420{
421 local_irq_disable();
422 clear_c0_status(ST0_IM);
423 while (1) {
424 if (cpu_wait) {
425 (*cpu_wait)();
426 if (cpu_has_counter) {
427 /*
428 * Clear counter interrupt while it
429 * breaks WAIT instruction even if
430 * masked.
431 */
432 write_c0_compare(0);
433 }
434 }
435 }
436}
437
68314725
AN		 438/* Watchdog support */
439void __init txx9_wdt_init(unsigned long base)
440{
441 struct resource res = {
442 .start = base,
443 .end = base + 0x100 - 1,
444 .flags = IORESOURCE_MEM,
445 };
446 platform_device_register_simple("txx9wdt", -1, &res, 1);
447}
448
496a3b5c
AN		 449void txx9_wdt_now(unsigned long base)
450{
451 struct txx9_tmr_reg __iomem *tmrptr =
452 ioremap(base, sizeof(struct txx9_tmr_reg));
453 /* disable watch dog timer */
454 __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
455 __raw_writel(0, &tmrptr->tcr);
456 /* kick watchdog */
457 __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
458 __raw_writel(1, &tmrptr->cpra); /* immediate */
459 __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
460 &tmrptr->tcr);
461}
462
c49f91f5
AN		 463/* SPI support */
464void __init txx9_spi_init(int busid, unsigned long base, int irq)
465{
466 struct resource res[] = {
467 {
468 .start = base,
469 .end = base + 0x20 - 1,
470 .flags = IORESOURCE_MEM,
471 }, {
472 .start = irq,
473 .flags = IORESOURCE_IRQ,
474 },
475 };
476 platform_device_register_simple("spi_txx9", busid,
477 res, ARRAY_SIZE(res));
478}
479
480void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
481{
482 struct platform_device *pdev =
483 platform_device_alloc("tc35815-mac", id);
484 if (!pdev ||
485 platform_device_add_data(pdev, ethaddr, 6) ||
486 platform_device_add(pdev))
487 platform_device_put(pdev);
488}
489
7779a5e0
AN		 490void __init txx9_sio_init(unsigned long baseaddr, int irq,
491 unsigned int line, unsigned int sclk, int nocts)
492{
493#ifdef CONFIG_SERIAL_TXX9
494 struct uart_port req;
495
496 memset(&req, 0, sizeof(req));
497 req.line = line;
498 req.iotype = UPIO_MEM;
499 req.membase = ioremap(baseaddr, 0x24);
500 req.mapbase = baseaddr;
501 req.irq = irq;
502 if (!nocts)
503 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
504 if (sclk) {
505 req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
506 req.uartclk = sclk;
507 } else
508 req.uartclk = TXX9_IMCLK;
509 early_serial_txx9_setup(&req);
510#endif /* CONFIG_SERIAL_TXX9 */
511}
512
e352953c
AN		 513#ifdef CONFIG_EARLY_PRINTK
514static void __init null_prom_putchar(char c)
515{
516}
517void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar;
518
519void __init prom_putchar(char c)
520{
521 txx9_prom_putchar(c);
522}
523
524static void __iomem *early_txx9_sio_port;
525
526static void __init early_txx9_sio_putchar(char c)
527{
528#define TXX9_SICISR 0x0c
529#define TXX9_SITFIFO 0x1c
530#define TXX9_SICISR_TXALS 0x00000002
531 while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
532 TXX9_SICISR_TXALS))
533 ;
534 __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
535}
536
537void __init txx9_sio_putchar_init(unsigned long baseaddr)
538{
539 early_txx9_sio_port = ioremap(baseaddr, 0x24);
540 txx9_prom_putchar = early_txx9_sio_putchar;
541}
542#endif /* CONFIG_EARLY_PRINTK */
543
edcaf1a6
AN		 544/* wrappers */
545void __init plat_mem_setup(void)
546{
94a4c329
AN		 547 ioport_resource.start = 0;
548 ioport_resource.end = ~0UL; /* no limit */
549 iomem_resource.start = 0;
550 iomem_resource.end = ~0UL; /* no limit */
a49297e8
AN		 551
552 /* fallback restart/halt routines */
553 _machine_restart = (void (*)(char *))txx9_machine_halt;
554 _machine_halt = txx9_machine_halt;
555 pm_power_off = txx9_machine_halt;
556
07517529
AN		 557#ifdef CONFIG_PCI
558 pcibios_plat_setup = txx9_pcibios_setup;
559#endif
edcaf1a6
AN		 560 txx9_board_vec->mem_setup();
561}
562
563void __init arch_init_irq(void)
564{
565 txx9_board_vec->irq_setup();
566}
567
568void __init plat_time_init(void)
569{
1374d084
AN		 570#ifdef CONFIG_CPU_TX49XX
571 mips_hpt_frequency = txx9_cpu_clock / 2;
572#endif
edcaf1a6
AN		 573 txx9_board_vec->time_init();
574}
575
576static int __init _txx9_arch_init(void)
577{
578 if (txx9_board_vec->arch_init)
579 txx9_board_vec->arch_init();
580 return 0;
581}
582arch_initcall(_txx9_arch_init);
583
584static int __init _txx9_device_init(void)
585{
586 if (txx9_board_vec->device_init)
587 txx9_board_vec->device_init();
588 return 0;
589}
590device_initcall(_txx9_device_init);
591
592int (*txx9_irq_dispatch)(int pending);
593asmlinkage void plat_irq_dispatch(void)
594{
595 int pending = read_c0_status() & read_c0_cause() & ST0_IM;
596 int irq = txx9_irq_dispatch(pending);
597
598 if (likely(irq >= 0))
599 do_IRQ(irq);
600 else
601 spurious_interrupt();
602}
4c642f3f
AN		 603
604/* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
605#ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
606static unsigned long __swizzle_addr_none(unsigned long port)
607{
608 return port;
609}
610unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
611EXPORT_SYMBOL(__swizzle_addr_b);
612#endif
51f607c7 613
1ba5a176
AN		 614#ifdef NEEDS_TXX9_IOSWABW
615static u16 ioswabw_default(volatile u16 *a, u16 x)
616{
617 return le16_to_cpu(x);
618}
619static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
620{
621 return x;
622}
623u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
624EXPORT_SYMBOL(ioswabw);
625u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
626EXPORT_SYMBOL(__mem_ioswabw);
627#endif
628
51f607c7
AN		 629void __init txx9_physmap_flash_init(int no, unsigned long addr,
630 unsigned long size,
631 const struct physmap_flash_data *pdata)
632{
633#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
634 struct resource res = {
635 .start = addr,
636 .end = addr + size - 1,
637 .flags = IORESOURCE_MEM,
638 };
639 struct platform_device *pdev;
640#ifdef CONFIG_MTD_PARTITIONS
641 static struct mtd_partition parts[2];
642 struct physmap_flash_data pdata_part;
643
644 /* If this area contained boot area, make separate partition */
645 if (pdata->nr_parts == 0 && !pdata->parts &&
646 addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
647 !parts[0].name) {
648 parts[0].name = "boot";
649 parts[0].offset = 0x1fc00000 - addr;
650 parts[0].size = addr + size - 0x1fc00000;
651 parts[1].name = "user";
652 parts[1].offset = 0;
653 parts[1].size = 0x1fc00000 - addr;
654 pdata_part = *pdata;
655 pdata_part.nr_parts = ARRAY_SIZE(parts);
656 pdata_part.parts = parts;
657 pdata = &pdata_part;
658 }
659#endif
660 pdev = platform_device_alloc("physmap-flash", no);
661 if (!pdev ||
662 platform_device_add_resources(pdev, &res, 1) ||
a591f5d3
AN		 663 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
664 platform_device_add(pdev))
665 platform_device_put(pdev);
666#endif
667}
668
669void __init txx9_ndfmc_init(unsigned long baseaddr,
670 const struct txx9ndfmc_platform_data *pdata)
671{
672#if defined(CONFIG_MTD_NAND_TXX9NDFMC) || \
673 defined(CONFIG_MTD_NAND_TXX9NDFMC_MODULE)
674 struct resource res = {
675 .start = baseaddr,
676 .end = baseaddr + 0x1000 - 1,
677 .flags = IORESOURCE_MEM,
678 };
679 struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1);
680
681 if (!pdev ||
682 platform_device_add_resources(pdev, &res, 1) ||
51f607c7
AN		 683 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
684 platform_device_add(pdev))
685 platform_device_put(pdev);
686#endif
687}
ae027ead
AN		 688
689#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
690static DEFINE_SPINLOCK(txx9_iocled_lock);
691
692#define TXX9_IOCLED_MAXLEDS 8
693
694struct txx9_iocled_data {
695 struct gpio_chip chip;
696 u8 cur_val;
697 void __iomem *mmioaddr;
698 struct gpio_led_platform_data pdata;
699 struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
700 char names[TXX9_IOCLED_MAXLEDS][32];
701};
702
703static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
704{
705 struct txx9_iocled_data *data =
706 container_of(chip, struct txx9_iocled_data, chip);
707 return data->cur_val & (1 << offset);
708}
709
710static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
711 int value)
712{
713 struct txx9_iocled_data *data =
714 container_of(chip, struct txx9_iocled_data, chip);
715 unsigned long flags;
716 spin_lock_irqsave(&txx9_iocled_lock, flags);
717 if (value)
718 data->cur_val |= 1 << offset;
719 else
720 data->cur_val &= ~(1 << offset);
721 writeb(data->cur_val, data->mmioaddr);
722 mmiowb();
723 spin_unlock_irqrestore(&txx9_iocled_lock, flags);
724}
725
726static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
727{
728 return 0;
729}
730
731static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
732 int value)
733{
734 txx9_iocled_set(chip, offset, value);
735 return 0;
736}
737
738void __init txx9_iocled_init(unsigned long baseaddr,
739 int basenum, unsigned int num, int lowactive,
740 const char *color, char **deftriggers)
741{
742 struct txx9_iocled_data *iocled;
743 struct platform_device *pdev;
744 int i;
745 static char *default_triggers[] __initdata = {
746 "heartbeat",
747 "ide-disk",
748 "nand-disk",
749 NULL,
750 };
751
752 if (!deftriggers)
753 deftriggers = default_triggers;
754 iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
755 if (!iocled)
756 return;
757 iocled->mmioaddr = ioremap(baseaddr, 1);
758 if (!iocled->mmioaddr)
70ebadc8 759 goto out_free;
ae027ead
AN		 760 iocled->chip.get = txx9_iocled_get;
761 iocled->chip.set = txx9_iocled_set;
762 iocled->chip.direction_input = txx9_iocled_dir_in;
763 iocled->chip.direction_output = txx9_iocled_dir_out;
764 iocled->chip.label = "iocled";
765 iocled->chip.base = basenum;
766 iocled->chip.ngpio = num;
767 if (gpiochip_add(&iocled->chip))
70ebadc8 768 goto out_unmap;
ae027ead
AN		 769 if (basenum < 0)
770 basenum = iocled->chip.base;
771
772 pdev = platform_device_alloc("leds-gpio", basenum);
773 if (!pdev)
70ebadc8 774 goto out_gpio;
ae027ead
AN		 775 iocled->pdata.num_leds = num;
776 iocled->pdata.leds = iocled->leds;
777 for (i = 0; i < num; i++) {
778 struct gpio_led *led = &iocled->leds[i];
779 snprintf(iocled->names[i], sizeof(iocled->names[i]),
780 "iocled:%s:%u", color, i);
781 led->name = iocled->names[i];
782 led->gpio = basenum + i;
783 led->active_low = lowactive;
784 if (deftriggers && *deftriggers)
785 led->default_trigger = *deftriggers++;
786 }
787 pdev->dev.platform_data = &iocled->pdata;
788 if (platform_device_add(pdev))
70ebadc8
JL		 789 goto out_pdev;
790 return;
791out_pdev:
792 platform_device_put(pdev);
793out_gpio:
a2e62f3a
RR		 794 if (gpiochip_remove(&iocled->chip))
795 return;
70ebadc8
JL		 796out_unmap:
797 iounmap(iocled->mmioaddr);
798out_free:
799 kfree(iocled);
ae027ead
AN		 800}
801#else /* CONFIG_LEDS_GPIO */
802void __init txx9_iocled_init(unsigned long baseaddr,
803 int basenum, unsigned int num, int lowactive,
804 const char *color, char **deftriggers)
805{
806}
807#endif /* CONFIG_LEDS_GPIO */
f48c8c95
AN		 808
809void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
810 const struct txx9dmac_platform_data *pdata)
811{
812#if defined(CONFIG_TXX9_DMAC) || defined(CONFIG_TXX9_DMAC_MODULE)
813 struct resource res[] = {
814 {
815 .start = baseaddr,
816 .end = baseaddr + 0x800 - 1,
817 .flags = IORESOURCE_MEM,
818#ifndef CONFIG_MACH_TX49XX
819 }, {
820 .start = irq,
821 .flags = IORESOURCE_IRQ,
822#endif
823 }
824 };
825#ifdef CONFIG_MACH_TX49XX
826 struct resource chan_res[] = {
827 {
828 .flags = IORESOURCE_IRQ,
829 }
830 };
831#endif
832 struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
833 struct txx9dmac_chan_platform_data cpdata;
834 int i;
835
836 if (!pdev ||
837 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
838 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
839 platform_device_add(pdev)) {
840 platform_device_put(pdev);
841 return;
842 }
843 memset(&cpdata, 0, sizeof(cpdata));
844 cpdata.dmac_dev = pdev;
845 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
846#ifdef CONFIG_MACH_TX49XX
847 chan_res[0].start = irq + i;
848#endif
849 pdev = platform_device_alloc("txx9dmac-chan",
850 id * TXX9_DMA_MAX_NR_CHANNELS + i);
851 if (!pdev ||
852#ifdef CONFIG_MACH_TX49XX
853 platform_device_add_resources(pdev, chan_res,
854 ARRAY_SIZE(chan_res)) ||
855#endif
856 platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
857 platform_device_add(pdev))
858 platform_device_put(pdev);
859 }
860#endif
861}
742cd586
AN		 862
863void __init txx9_aclc_init(unsigned long baseaddr, int irq,
864 unsigned int dmac_id,
865 unsigned int dma_chan_out,
866 unsigned int dma_chan_in)
867{
868#if defined(CONFIG_SND_SOC_TXX9ACLC) || \
869 defined(CONFIG_SND_SOC_TXX9ACLC_MODULE)
870 unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
871 struct resource res[] = {
872 {
873 .start = baseaddr,
874 .end = baseaddr + 0x100 - 1,
875 .flags = IORESOURCE_MEM,
876 }, {
877 .start = irq,
878 .flags = IORESOURCE_IRQ,
879 }, {
880 .name = "txx9dmac-chan",
881 .start = dma_base + dma_chan_out,
882 .flags = IORESOURCE_DMA,
883 }, {
884 .name = "txx9dmac-chan",
885 .start = dma_base + dma_chan_in,
886 .flags = IORESOURCE_DMA,
887 }
888 };
889 struct platform_device *pdev =
890 platform_device_alloc("txx9aclc-ac97", -1);
891
892 if (!pdev ||
893 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
894 platform_device_add(pdev))
895 platform_device_put(pdev);
896#endif
897}
c3b28ae2
AN		 898
899static struct sysdev_class txx9_sramc_sysdev_class;
900
901struct txx9_sramc_sysdev {
902 struct sys_device dev;
903 struct bin_attribute bindata_attr;
904 void __iomem *base;
905};
906
907static ssize_t txx9_sram_read(struct kobject *kobj,
908 struct bin_attribute *bin_attr,
909 char *buf, loff_t pos, size_t size)
910{
911 struct txx9_sramc_sysdev *dev = bin_attr->private;
912 size_t ramsize = bin_attr->size;
913
914 if (pos >= ramsize)
915 return 0;
916 if (pos + size > ramsize)
917 size = ramsize - pos;
918 memcpy_fromio(buf, dev->base + pos, size);
919 return size;
920}
921
922static ssize_t txx9_sram_write(struct kobject *kobj,
923 struct bin_attribute *bin_attr,
924 char *buf, loff_t pos, size_t size)
925{
926 struct txx9_sramc_sysdev *dev = bin_attr->private;
927 size_t ramsize = bin_attr->size;
928
929 if (pos >= ramsize)
930 return 0;
931 if (pos + size > ramsize)
932 size = ramsize - pos;
933 memcpy_toio(dev->base + pos, buf, size);
934 return size;
935}
936
937void __init txx9_sramc_init(struct resource *r)
938{
939 struct txx9_sramc_sysdev *dev;
940 size_t size;
941 int err;
942
943 if (!txx9_sramc_sysdev_class.name) {
944 txx9_sramc_sysdev_class.name = "txx9_sram";
945 err = sysdev_class_register(&txx9_sramc_sysdev_class);
946 if (err) {
947 txx9_sramc_sysdev_class.name = NULL;
948 return;
949 }
950 }
951 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
952 if (!dev)
953 return;
954 size = resource_size(r);
955 dev->base = ioremap(r->start, size);
956 if (!dev->base)
957 goto exit;
958 dev->dev.cls = &txx9_sramc_sysdev_class;
f937331b 959 sysfs_bin_attr_init(&dev->bindata_attr);
c3b28ae2
AN		 960 dev->bindata_attr.attr.name = "bindata";
961 dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
962 dev->bindata_attr.read = txx9_sram_read;
963 dev->bindata_attr.write = txx9_sram_write;
964 dev->bindata_attr.size = size;
965 dev->bindata_attr.private = dev;
966 err = sysdev_register(&dev->dev);
967 if (err)
968 goto exit;
969 err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
970 if (err) {
971 sysdev_unregister(&dev->dev);
972 goto exit;
973 }
974 return;
975exit:
976 if (dev) {
977 if (dev->base)
978 iounmap(dev->base);
979 kfree(dev);
980 }
981}
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