[net-next-2.6.git] / arch / mips / sibyte / sb1250 / irq.c

/*
 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/kernel_stat.h>

#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/io.h>

#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_uart.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250.h>

/*
 * These are the routines that handle all the low level interrupt stuff.
 * Actions handled here are: initialization of the interrupt map, requesting of
 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
 * for interrupt lines
 */


static void end_sb1250_irq(unsigned int irq);
static void enable_sb1250_irq(unsigned int irq);
static void disable_sb1250_irq(unsigned int irq);
static void ack_sb1250_irq(unsigned int irq);
#ifdef CONFIG_SMP
static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask);
#endif

#ifdef CONFIG_SIBYTE_HAS_LDT
extern unsigned long ldt_eoi_space;
#endif

static struct irq_chip sb1250_irq_type = {
	.name = "SB1250-IMR",
	.ack = ack_sb1250_irq,
	.mask = disable_sb1250_irq,
	.mask_ack = ack_sb1250_irq,
	.unmask = enable_sb1250_irq,
	.end = end_sb1250_irq,
#ifdef CONFIG_SMP
	.set_affinity = sb1250_set_affinity
#endif
};

/* Store the CPU id (not the logical number) */
int sb1250_irq_owner[SB1250_NR_IRQS];

static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);

void sb1250_mask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints |= (((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

void sb1250_unmask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints &= ~(((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

#ifdef CONFIG_SMP
static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
{
	int i = 0, old_cpu, cpu, int_on;
	u64 cur_ints;
	unsigned long flags;

	i = cpumask_first(mask);

	/* Convert logical CPU to physical CPU */
	cpu = cpu_logical_map(i);

	/* Protect against other affinity changers and IMR manipulation */
	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);

	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	old_cpu = sb1250_irq_owner[irq];
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	int_on = !(cur_ints & (((u64) 1) << irq));
	if (int_on) {
		/* If it was on, mask it */
		cur_ints |= (((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	sb1250_irq_owner[irq] = cpu;
	if (int_on) {
		/* unmask for the new CPU */
		cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
		cur_ints &= ~(((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);

	return 0;
}
#endif

/*****************************************************************************/

static void disable_sb1250_irq(unsigned int irq)
{
	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}

static void enable_sb1250_irq(unsigned int irq)
{
	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
}


static void ack_sb1250_irq(unsigned int irq)
{
#ifdef CONFIG_SIBYTE_HAS_LDT
	u64 pending;

	/*
	 * If the interrupt was an HT interrupt, now is the time to
	 * clear it.  NOTE: we assume the HT bridge was set up to
	 * deliver the interrupts to all CPUs (which makes affinity
	 * changing easier for us)
	 */
	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
						    R_IMR_LDT_INTERRUPT)));
	pending &= ((u64)1 << (irq));
	if (pending) {
		int i;
		for (i=0; i<NR_CPUS; i++) {
			int cpu;
#ifdef CONFIG_SMP
			cpu = cpu_logical_map(i);
#else
			cpu = i;
#endif
			/*
			 * Clear for all CPUs so an affinity switch
			 * doesn't find an old status
			 */
			__raw_writeq(pending,
				     IOADDR(A_IMR_REGISTER(cpu,
						R_IMR_LDT_INTERRUPT_CLR)));
		}

		/*
		 * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
		 * Pass 2, the LDT world may be edge-triggered, but
		 * this EOI shouldn't hurt.  If they are
		 * level-sensitive, the EOI is required.
		 */
		*(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	}
#endif
	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}


static void end_sb1250_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
		sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	}
}


void __init init_sb1250_irqs(void)
{
	int i;

	for (i = 0; i < SB1250_NR_IRQS; i++) {
		set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
		sb1250_irq_owner[i] = 0;
	}
}


/*
 *  arch_init_irq is called early in the boot sequence from init/main.c via
 *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 *  installing the handler that will be responsible for dispatching interrupts
 *  to the "right" place.
 */
/*
 * For now, map all interrupts to IP[2].  We could save
 * some cycles by parceling out system interrupts to different
 * IP lines, but keep it simple for bringup.  We'll also direct
 * all interrupts to a single CPU; we should probably route
 * PCI and LDT to one cpu and everything else to the other
 * to balance the load a bit.
 *
 * On the second cpu, everything is set to IP5, which is
 * ignored, EXCEPT the mailbox interrupt.  That one is
 * set to IP[2] so it is handled.  This is needed so we
 * can do cross-cpu function calls, as required by SMP
 */

#define IMR_IP2_VAL	K_INT_MAP_I0
#define IMR_IP3_VAL	K_INT_MAP_I1
#define IMR_IP4_VAL	K_INT_MAP_I2
#define IMR_IP5_VAL	K_INT_MAP_I3
#define IMR_IP6_VAL	K_INT_MAP_I4

void __init arch_init_irq(void)
{

	unsigned int i;
	u64 tmp;
	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
		STATUSF_IP1 | STATUSF_IP0;

	/* Default everything to IP2 */
	for (i = 0; i < SB1250_NR_IRQS; i++) {	/* was I0 */
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(0,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(1,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
	}

	init_sb1250_irqs();

	/*
	 * Map the high 16 bits of the mailbox registers to IP[3], for
	 * inter-cpu messages
	 */
	/* Was I1 */
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));

	/* Clear the mailboxes.  The firmware may leave them dirty */
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));

	/* Mask everything except the mailbox registers for both cpus */
	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));

	/*
	 * Note that the timer interrupts are also mapped, but this is
	 * done in sb1250_time_init().  Also, the profiling driver
	 * does its own management of IP7.
	 */

	/* Enable necessary IPs, disable the rest */
	change_c0_status(ST0_IM, imask);
}

extern void sb1250_mailbox_interrupt(void);

static inline void dispatch_ip2(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned long long mask;

	/*
	 * Default...we've hit an IP[2] interrupt, which means we've got to
	 * check the 1250 interrupt registers to figure out what to do.  Need
	 * to detect which CPU we're on, now that smp_affinity is supported.
	 */
	mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
				  R_IMR_INTERRUPT_STATUS_BASE)));
	if (mask)
		do_IRQ(fls64(mask) - 1);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned int pending;

	/*
	 * What a pain. We have to be really careful saving the upper 32 bits
	 * of any * register across function calls if we don't want them
	 * trashed--since were running in -o32, the calling routing never saves
	 * the full 64 bits of a register across a function call.  Being the
	 * interrupt handler, we're guaranteed that interrupts are disabled
	 * during this code so we don't have to worry about random interrupts
	 * blasting the high 32 bits.
	 */

	pending = read_c0_cause() & read_c0_status() & ST0_IM;

	if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	else if (pending & CAUSEF_IP4)
		do_IRQ(K_INT_TIMER_0 + cpu); 	/* sb1250_timer_interrupt() */

#ifdef CONFIG_SMP
	else if (pending & CAUSEF_IP3)
		sb1250_mailbox_interrupt();
#endif

	else if (pending & CAUSEF_IP2)
		dispatch_ip2();
	else
		spurious_interrupt();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*/
1da177e4 LT	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/linkage.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/smp.h>
	24	#include <linux/mm.h>
	25	#include <linux/slab.h>
	26	#include <linux/kernel_stat.h>
	27
	28	#include <asm/errno.h>
	29	#include <asm/signal.h>
	30	#include <asm/system.h>
7bcf7717	31	#include <asm/time.h>
1da177e4 LT	32	#include <asm/io.h>
	33
	34	#include <asm/sibyte/sb1250_regs.h>
	35	#include <asm/sibyte/sb1250_int.h>
	36	#include <asm/sibyte/sb1250_uart.h>
	37	#include <asm/sibyte/sb1250_scd.h>
	38	#include <asm/sibyte/sb1250.h>
	39
	40	/*
	41	* These are the routines that handle all the low level interrupt stuff.
	42	* Actions handled here are: initialization of the interrupt map, requesting of
	43	* interrupt lines by handlers, dispatching if interrupts to handlers, probing
	44	* for interrupt lines
	45	*/
	46
	47
1da177e4 LT	48	static void end_sb1250_irq(unsigned int irq);
	49	static void enable_sb1250_irq(unsigned int irq);
	50	static void disable_sb1250_irq(unsigned int irq);
1da177e4 LT	51	static void ack_sb1250_irq(unsigned int irq);
1da177e4 LT	52	#ifdef CONFIG_SMP
d5dedd45	53	static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask);
1da177e4 LT	54	#endif
	55
	56	#ifdef CONFIG_SIBYTE_HAS_LDT
	57	extern unsigned long ldt_eoi_space;
	58	#endif
	59
94dee171	60	static struct irq_chip sb1250_irq_type = {
70d21cde	61	.name = "SB1250-IMR",
8ab00b9a	62	.ack = ack_sb1250_irq,
1603b5ac AN	63	.mask = disable_sb1250_irq,
	64	.mask_ack = ack_sb1250_irq,
	65	.unmask = enable_sb1250_irq,
8ab00b9a	66	.end = end_sb1250_irq,
1da177e4	67	#ifdef CONFIG_SMP
8ab00b9a	68	.set_affinity = sb1250_set_affinity
1da177e4 LT	69	#endif
	70	};
	71
	72	/* Store the CPU id (not the logical number) */
	73	int sb1250_irq_owner[SB1250_NR_IRQS];
	74
5772f6de	75	static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
1da177e4 LT	76
	77	void sb1250_mask_irq(int cpu, int irq)
	78	{
	79	unsigned long flags;
	80	u64 cur_ints;
	81
5772f6de	82	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	83	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	84	R_IMR_INTERRUPT_MASK));
1da177e4	85	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	86	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	87	R_IMR_INTERRUPT_MASK));
5772f6de	88	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
1da177e4 LT	89	}
	90
	91	void sb1250_unmask_irq(int cpu, int irq)
	92	{
	93	unsigned long flags;
	94	u64 cur_ints;
	95
5772f6de	96	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	97	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	98	R_IMR_INTERRUPT_MASK));
1da177e4	99	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	100	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	101	R_IMR_INTERRUPT_MASK));
5772f6de	102	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
1da177e4 LT	103	}
	104
	105	#ifdef CONFIG_SMP
d5dedd45	106	static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
1da177e4 LT	107	{
	108	int i = 0, old_cpu, cpu, int_on;
	109	u64 cur_ints;
1da177e4 LT	110	unsigned long flags;
1da177e4 LT	111
0de26520	112	i = cpumask_first(mask);
1da177e4	113
1da177e4 LT	114	/* Convert logical CPU to physical CPU */
	115	cpu = cpu_logical_map(i);
	116
	117	/* Protect against other affinity changers and IMR manipulation */
5772f6de	118	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
1da177e4 LT	119
	120	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	121	old_cpu = sb1250_irq_owner[irq];
65bda1a9 MR	122	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	123	R_IMR_INTERRUPT_MASK));
1da177e4 LT	124	int_on = !(cur_ints & (((u64) 1) << irq));
	125	if (int_on) {
	126	/* If it was on, mask it */
	127	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	128	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	129	R_IMR_INTERRUPT_MASK));
1da177e4 LT	130	}
	131	sb1250_irq_owner[irq] = cpu;
	132	if (int_on) {
	133	/* unmask for the new CPU */
65bda1a9 MR	134	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	135	R_IMR_INTERRUPT_MASK));
1da177e4	136	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	137	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	138	R_IMR_INTERRUPT_MASK));
1da177e4	139	}
5772f6de	140	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
d5dedd45 YL	141
d5dedd45 YL	142	return 0;
1da177e4 LT	143	}
	144	#endif
	145
1da177e4 LT	146	/*****************************************************************************/
1da177e4 LT	147
1da177e4 LT	148	static void disable_sb1250_irq(unsigned int irq)
	149	{
	150	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	151	}
	152
	153	static void enable_sb1250_irq(unsigned int irq)
	154	{
	155	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	156	}
	157
	158
	159	static void ack_sb1250_irq(unsigned int irq)
	160	{
	161	#ifdef CONFIG_SIBYTE_HAS_LDT
	162	u64 pending;
	163
	164	/*
	165	* If the interrupt was an HT interrupt, now is the time to
	166	* clear it. NOTE: we assume the HT bridge was set up to
	167	* deliver the interrupts to all CPUs (which makes affinity
	168	* changing easier for us)
	169	*/
65bda1a9 MR	170	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
65bda1a9 MR	171	R_IMR_LDT_INTERRUPT)));
1da177e4 LT	172	pending &= ((u64)1 << (irq));
	173	if (pending) {
	174	int i;
	175	for (i=0; i<NR_CPUS; i++) {
	176	int cpu;
	177	#ifdef CONFIG_SMP
	178	cpu = cpu_logical_map(i);
	179	#else
	180	cpu = i;
	181	#endif
	182	/*
	183	* Clear for all CPUs so an affinity switch
	184	* doesn't find an old status
	185	*/
65bda1a9 MR	186	__raw_writeq(pending,
65bda1a9 MR	187	IOADDR(A_IMR_REGISTER(cpu,
1da177e4 LT	188	R_IMR_LDT_INTERRUPT_CLR)));
	189	}
	190
	191	/*
	192	* Generate EOI. For Pass 1 parts, EOI is a nop. For
	193	* Pass 2, the LDT world may be edge-triggered, but
	194	* this EOI shouldn't hurt. If they are
	195	* level-sensitive, the EOI is required.
	196	*/
	197	(uint32_t )(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	198	}
	199	#endif
	200	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	201	}
	202
	203
	204	static void end_sb1250_irq(unsigned int irq)
	205	{
	206	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS))) {
	207	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	208	}
	209	}
	210
	211
	212	void __init init_sb1250_irqs(void)
	213	{
	214	int i;
	215
1603b5ac	216	for (i = 0; i < SB1250_NR_IRQS; i++) {
c87e0909	217	set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
1603b5ac	218	sb1250_irq_owner[i] = 0;
1da177e4 LT	219	}
	220	}
	221
	222
1da177e4 LT	223	/*
	224	* arch_init_irq is called early in the boot sequence from init/main.c via
	225	* init_IRQ. It is responsible for setting up the interrupt mapper and
	226	* installing the handler that will be responsible for dispatching interrupts
	227	* to the "right" place.
	228	*/
	229	/*
	230	* For now, map all interrupts to IP[2]. We could save
	231	* some cycles by parceling out system interrupts to different
	232	* IP lines, but keep it simple for bringup. We'll also direct
	233	* all interrupts to a single CPU; we should probably route
	234	* PCI and LDT to one cpu and everything else to the other
	235	* to balance the load a bit.
	236	*
	237	* On the second cpu, everything is set to IP5, which is
	238	* ignored, EXCEPT the mailbox interrupt. That one is
	239	* set to IP[2] so it is handled. This is needed so we
f77f13e2	240	* can do cross-cpu function calls, as required by SMP
1da177e4 LT	241	*/
	242
	243	#define IMR_IP2_VAL K_INT_MAP_I0
	244	#define IMR_IP3_VAL K_INT_MAP_I1
	245	#define IMR_IP4_VAL K_INT_MAP_I2
	246	#define IMR_IP5_VAL K_INT_MAP_I3
	247	#define IMR_IP6_VAL K_INT_MAP_I4
	248
	249	void __init arch_init_irq(void)
	250	{
	251
	252	unsigned int i;
	253	u64 tmp;
	254	unsigned int imask = STATUSF_IP4 \| STATUSF_IP3 \| STATUSF_IP2 \|
	255	STATUSF_IP1 \| STATUSF_IP0;
	256
	257	/* Default everything to IP2 */
	258	for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
65bda1a9 MR	259	__raw_writeq(IMR_IP2_VAL,
	260	IOADDR(A_IMR_REGISTER(0,
	261	R_IMR_INTERRUPT_MAP_BASE) +
	262	(i << 3)));
	263	__raw_writeq(IMR_IP2_VAL,
	264	IOADDR(A_IMR_REGISTER(1,
	265	R_IMR_INTERRUPT_MAP_BASE) +
	266	(i << 3)));
1da177e4 LT	267	}
	268
	269	init_sb1250_irqs();
	270
	271	/*
	272	* Map the high 16 bits of the mailbox registers to IP[3], for
	273	* inter-cpu messages
	274	*/
	275	/* Was I1 */
65bda1a9 MR	276	__raw_writeq(IMR_IP3_VAL,
	277	IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
	278	(K_INT_MBOX_0 << 3)));
	279	__raw_writeq(IMR_IP3_VAL,
	280	IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
	281	(K_INT_MBOX_0 << 3)));
1da177e4 LT	282
1da177e4 LT	283	/* Clear the mailboxes. The firmware may leave them dirty */
65bda1a9 MR	284	__raw_writeq(0xffffffffffffffffULL,
	285	IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	286	__raw_writeq(0xffffffffffffffffULL,
	287	IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
1da177e4 LT	288
	289	/* Mask everything except the mailbox registers for both cpus */
	290	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
65bda1a9 MR	291	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
65bda1a9 MR	292	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
1da177e4	293
1da177e4 LT	294	/*
1da177e4 LT	295	* Note that the timer interrupts are also mapped, but this is
42a3b4f2	296	* done in sb1250_time_init(). Also, the profiling driver
1da177e4 LT	297	* does its own management of IP7.
	298	*/
	299
1da177e4 LT	300	/* Enable necessary IPs, disable the rest */
1da177e4 LT	301	change_c0_status(ST0_IM, imask);
1da177e4 LT	302	}
1da177e4 LT	303
937a8015	304	extern void sb1250_mailbox_interrupt(void);
4fb60a4b	305
d0453365 RB	306	static inline void dispatch_ip2(void)
	307	{
	308	unsigned int cpu = smp_processor_id();
	309	unsigned long long mask;
	310
	311	/*
	312	* Default...we've hit an IP[2] interrupt, which means we've got to
	313	* check the 1250 interrupt registers to figure out what to do. Need
	314	* to detect which CPU we're on, now that smp_affinity is supported.
	315	*/
	316	mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
	317	R_IMR_INTERRUPT_STATUS_BASE)));
	318	if (mask)
	319	do_IRQ(fls64(mask) - 1);
	320	}
	321
937a8015	322	asmlinkage void plat_irq_dispatch(void)
e4ac58af	323	{
d527eef5	324	unsigned int cpu = smp_processor_id();
e4ac58af RB	325	unsigned int pending;
e4ac58af RB	326
e4ac58af RB	327	/*
	328	* What a pain. We have to be really careful saving the upper 32 bits
	329	* of any * register across function calls if we don't want them
	330	* trashed--since were running in -o32, the calling routing never saves
	331	* the full 64 bits of a register across a function call. Being the
	332	* interrupt handler, we're guaranteed that interrupts are disabled
	333	* during this code so we don't have to worry about random interrupts
	334	* blasting the high 32 bits.
	335	*/
	336
119537c0	337	pending = read_c0_cause() & read_c0_status() & ST0_IM;
e4ac58af	338
7bcf7717 RB	339	if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
	340	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	341	else if (pending & CAUSEF_IP4)
d527eef5	342	do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
e4ac58af RB	343
e4ac58af RB	344	#ifdef CONFIG_SMP
6e61e85b	345	else if (pending & CAUSEF_IP3)
937a8015	346	sb1250_mailbox_interrupt();
e4ac58af RB	347	#endif
e4ac58af RB	348
d0453365 RB	349	else if (pending & CAUSEF_IP2)
	350	dispatch_ip2();
	351	else
937a8015	352	spurious_interrupt();
e4ac58af	353	}