[net-next-2.6.git] / arch / mips / sgi-ip22 / ip22-time.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Time operations for IP22 machines. Original code may come from
 * Ralf Baechle or David S. Miller (sorry guys, i'm really not sure)
 *
 * Copyright (C) 2001 by Ladislav Michl
 * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/bcd.h>
#include <linux/ds1286.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/time.h>

#include <asm/cpu.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/sgialib.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>

/*
 * note that mktime uses month from 1 to 12 while to_tm
 * uses 0 to 11.
 */
static unsigned long indy_rtc_get_time(void)
{
	unsigned int yrs, mon, day, hrs, min, sec;
	unsigned int save_control;
	unsigned long flags;

	spin_lock_irqsave(&rtc_lock, flags);
	save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
	hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;

	sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff);
	min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff);
	hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x3f);
	day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff);
	mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f);
	yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff);

	hpc3c0->rtcregs[RTC_CMD] = save_control;
	spin_unlock_irqrestore(&rtc_lock, flags);

	if (yrs < 45)
		yrs += 30;
	if ((yrs += 40) < 70)
		yrs += 100;

	return mktime(yrs + 1900, mon, day, hrs, min, sec);
}

static int indy_rtc_set_time(unsigned long tim)
{
	struct rtc_time tm;
	unsigned int save_control;
	unsigned long flags;

	to_tm(tim, &tm);

	tm.tm_mon += 1;		/* tm_mon starts at zero */
	tm.tm_year -= 1940;
	if (tm.tm_year >= 100)
		tm.tm_year -= 100;

	spin_lock_irqsave(&rtc_lock, flags);
	save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
	hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;

	hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_year);
	hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon);
	hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday);
	hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour);
	hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min);
	hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec);
	hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0;

	hpc3c0->rtcregs[RTC_CMD] = save_control;
	spin_unlock_irqrestore(&rtc_lock, flags);

	return 0;
}

static unsigned long dosample(void)
{
	u32 ct0, ct1;
	volatile u8 msb, lsb;

	/* Start the counter. */
	sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
			 SGINT_TCWORD_MRGEN);
	sgint->tcnt2 = SGINT_TCSAMP_COUNTER & 0xff;
	sgint->tcnt2 = SGINT_TCSAMP_COUNTER >> 8;

	/* Get initial counter invariant */
	ct0 = read_c0_count();

	/* Latch and spin until top byte of counter2 is zero */
	do {
		sgint->tcword = SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT;
		lsb = sgint->tcnt2;
		msb = sgint->tcnt2;
		ct1 = read_c0_count();
	} while (msb);

	/* Stop the counter. */
	sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
			 SGINT_TCWORD_MSWST);
	/*
	 * Return the difference, this is how far the r4k counter increments
	 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
	 * clock (= 1000000 / HZ / 2).
	 */
	/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
	return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
}

/*
 * Here we need to calibrate the cycle counter to at least be close.
 */
static __init void indy_time_init(void)
{
	unsigned long r4k_ticks[3];
	unsigned long r4k_tick;

	/*
	 * Figure out the r4k offset, the algorithm is very simple and works in
	 * _all_ cases as long as the 8254 counter register itself works ok (as
	 * an interrupt driving timer it does not because of bug, this is why
	 * we are using the onchip r4k counter/compare register to serve this
	 * purpose, but for r4k_offset calculation it will work ok for us).
	 * There are other very complicated ways of performing this calculation
	 * but this one works just fine so I am not going to futz around. ;-)
	 */
	printk(KERN_INFO "Calibrating system timer... ");
	dosample();	/* Prime cache. */
	dosample();	/* Prime cache. */
	/* Zero is NOT an option. */
	do {
		r4k_ticks[0] = dosample();
	} while (!r4k_ticks[0]);
	do {
		r4k_ticks[1] = dosample();
	} while (!r4k_ticks[1]);

	if (r4k_ticks[0] != r4k_ticks[1]) {
		printk("warning: timer counts differ, retrying... ");
		r4k_ticks[2] = dosample();
		if (r4k_ticks[2] == r4k_ticks[0]
		    || r4k_ticks[2] == r4k_ticks[1])
			r4k_tick = r4k_ticks[2];
		else {
			printk("disagreement, using average... ");
			r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
				   + r4k_ticks[2]) / 3;
		}
	} else
		r4k_tick = r4k_ticks[0];

	printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
		(int) (r4k_tick / (500000 / HZ)),
		(int) (r4k_tick % (500000 / HZ)));

	mips_hpt_frequency = r4k_tick * HZ;
}

/* Generic SGI handler for (spurious) 8254 interrupts */
void indy_8254timer_irq(struct pt_regs *regs)
{
	int irq = SGI_8254_0_IRQ;
	ULONG cnt;
	char c;

	irq_enter();
	kstat_this_cpu.irqs[irq]++;
	printk(KERN_ALERT "Oops, got 8254 interrupt.\n");
	ArcRead(0, &c, 1, &cnt);
	ArcEnterInteractiveMode();
	irq_exit();
}

void indy_r4k_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	int irq = SGI_TIMER_IRQ;

	irq_enter();
	kstat_this_cpu.irqs[irq]++;
	timer_interrupt(irq, NULL);
	irq_exit();
	set_irq_regs(old_regs);
}

void __init plat_timer_setup(struct irqaction *irq)
{
	/* over-write the handler, we use our own way */
	irq->handler = no_action;

	/* setup irqaction */
	setup_irq(SGI_TIMER_IRQ, irq);
}

void __init ip22_time_init(void)
{
	/* setup hookup functions */
	rtc_mips_get_time = indy_rtc_get_time;
	rtc_mips_set_time = indy_rtc_set_time;

	board_time_init = indy_time_init;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Time operations for IP22 machines. Original code may come from
	7	* Ralf Baechle or David S. Miller (sorry guys, i'm really not sure)
	8	*
	9	* Copyright (C) 2001 by Ladislav Michl
54d0a216	10	* Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org)
1da177e4 LT	11	*/
	12	#include <linux/bcd.h>
	13	#include <linux/ds1286.h>
	14	#include <linux/init.h>
046f8f70	15	#include <linux/irq.h>
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/kernel_stat.h>
	19	#include <linux/time.h>
	20
	21	#include <asm/cpu.h>
	22	#include <asm/mipsregs.h>
	23	#include <asm/io.h>
	24	#include <asm/irq.h>
	25	#include <asm/time.h>
	26	#include <asm/sgialib.h>
	27	#include <asm/sgi/ioc.h>
	28	#include <asm/sgi/hpc3.h>
	29	#include <asm/sgi/ip22.h>
	30
	31	/*
	32	* note that mktime uses month from 1 to 12 while to_tm
	33	* uses 0 to 11.
	34	*/
	35	static unsigned long indy_rtc_get_time(void)
	36	{
	37	unsigned int yrs, mon, day, hrs, min, sec;
	38	unsigned int save_control;
53c2df2f	39	unsigned long flags;
1da177e4	40
53c2df2f	41	spin_lock_irqsave(&rtc_lock, flags);
1da177e4 LT	42	save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
	43	hpc3c0->rtcregs[RTC_CMD] = save_control \| RTC_TE;
	44
	45	sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff);
	46	min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff);
	47	hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x3f);
	48	day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff);
	49	mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f);
	50	yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff);
	51
	52	hpc3c0->rtcregs[RTC_CMD] = save_control;
53c2df2f	53	spin_unlock_irqrestore(&rtc_lock, flags);
1da177e4 LT	54
	55	if (yrs < 45)
	56	yrs += 30;
	57	if ((yrs += 40) < 70)
	58	yrs += 100;
	59
	60	return mktime(yrs + 1900, mon, day, hrs, min, sec);
	61	}
	62
	63	static int indy_rtc_set_time(unsigned long tim)
	64	{
	65	struct rtc_time tm;
	66	unsigned int save_control;
53c2df2f	67	unsigned long flags;
1da177e4 LT	68
	69	to_tm(tim, &tm);
	70
	71	tm.tm_mon += 1; /* tm_mon starts at zero */
	72	tm.tm_year -= 1940;
	73	if (tm.tm_year >= 100)
	74	tm.tm_year -= 100;
	75
53c2df2f	76	spin_lock_irqsave(&rtc_lock, flags);
1da177e4 LT	77	save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
	78	hpc3c0->rtcregs[RTC_CMD] = save_control \| RTC_TE;
	79
d1d60ded	80	hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_year);
1da177e4 LT	81	hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon);
	82	hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday);
	83	hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour);
	84	hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min);
	85	hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec);
	86	hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0;
	87
	88	hpc3c0->rtcregs[RTC_CMD] = save_control;
53c2df2f	89	spin_unlock_irqrestore(&rtc_lock, flags);
1da177e4 LT	90
	91	return 0;
	92	}
	93
	94	static unsigned long dosample(void)
	95	{
	96	u32 ct0, ct1;
	97	volatile u8 msb, lsb;
	98
	99	/* Start the counter. */
	100	sgint->tcword = (SGINT_TCWORD_CNT2 \| SGINT_TCWORD_CALL \|
	101	SGINT_TCWORD_MRGEN);
	102	sgint->tcnt2 = SGINT_TCSAMP_COUNTER & 0xff;
	103	sgint->tcnt2 = SGINT_TCSAMP_COUNTER >> 8;
	104
	105	/* Get initial counter invariant */
	106	ct0 = read_c0_count();
	107
	108	/* Latch and spin until top byte of counter2 is zero */
	109	do {
	110	sgint->tcword = SGINT_TCWORD_CNT2 \| SGINT_TCWORD_CLAT;
	111	lsb = sgint->tcnt2;
	112	msb = sgint->tcnt2;
	113	ct1 = read_c0_count();
	114	} while (msb);
	115
	116	/* Stop the counter. */
	117	sgint->tcword = (SGINT_TCWORD_CNT2 \| SGINT_TCWORD_CALL \|
	118	SGINT_TCWORD_MSWST);
	119	/*
	120	* Return the difference, this is how far the r4k counter increments
	121	* for every 1/HZ seconds. We round off the nearest 1 MHz of master
	122	* clock (= 1000000 / HZ / 2).
	123	*/
	124	/return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) (500000/HZ);*/
	125	return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
	126	}
	127
	128	/*
	129	* Here we need to calibrate the cycle counter to at least be close.
	130	*/
	131	static __init void indy_time_init(void)
	132	{
	133	unsigned long r4k_ticks[3];
	134	unsigned long r4k_tick;
	135
42a3b4f2	136	/*
1da177e4 LT	137	* Figure out the r4k offset, the algorithm is very simple and works in
	138	* _all_ cases as long as the 8254 counter register itself works ok (as
	139	* an interrupt driving timer it does not because of bug, this is why
	140	* we are using the onchip r4k counter/compare register to serve this
	141	* purpose, but for r4k_offset calculation it will work ok for us).
	142	* There are other very complicated ways of performing this calculation
	143	* but this one works just fine so I am not going to futz around. ;-)
	144	*/
	145	printk(KERN_INFO "Calibrating system timer... ");
	146	dosample(); /* Prime cache. */
	147	dosample(); /* Prime cache. */
	148	/* Zero is NOT an option. */
	149	do {
	150	r4k_ticks[0] = dosample();
	151	} while (!r4k_ticks[0]);
	152	do {
	153	r4k_ticks[1] = dosample();
	154	} while (!r4k_ticks[1]);
	155
	156	if (r4k_ticks[0] != r4k_ticks[1]) {
	157	printk("warning: timer counts differ, retrying... ");
	158	r4k_ticks[2] = dosample();
	159	if (r4k_ticks[2] == r4k_ticks[0]
	160	\|\| r4k_ticks[2] == r4k_ticks[1])
	161	r4k_tick = r4k_ticks[2];
	162	else {
	163	printk("disagreement, using average... ");
	164	r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
	165	+ r4k_ticks[2]) / 3;
	166	}
	167	} else
	168	r4k_tick = r4k_ticks[0];
	169
	170	printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
	171	(int) (r4k_tick / (500000 / HZ)),
	172	(int) (r4k_tick % (500000 / HZ)));
	173
	174	mips_hpt_frequency = r4k_tick * HZ;
	175	}
	176
	177	/* Generic SGI handler for (spurious) 8254 interrupts */
	178	void indy_8254timer_irq(struct pt_regs *regs)
	179	{
	180	int irq = SGI_8254_0_IRQ;
	181	ULONG cnt;
	182	char c;
	183
	184	irq_enter();
	185	kstat_this_cpu.irqs[irq]++;
	186	printk(KERN_ALERT "Oops, got 8254 interrupt.\n");
	187	ArcRead(0, &c, 1, &cnt);
	188	ArcEnterInteractiveMode();
	189	irq_exit();
	190	}
	191
	192	void indy_r4k_timer_interrupt(struct pt_regs *regs)
	193	{
7d12e780	194	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	195	int irq = SGI_TIMER_IRQ;
	196
	197	irq_enter();
	198	kstat_this_cpu.irqs[irq]++;
7d12e780	199	timer_interrupt(irq, NULL);
1da177e4	200	irq_exit();
7d12e780	201	set_irq_regs(old_regs);
1da177e4 LT	202	}
1da177e4 LT	203
54d0a216	204	void __init plat_timer_setup(struct irqaction *irq)
1da177e4 LT	205	{
	206	/* over-write the handler, we use our own way */
	207	irq->handler = no_action;
	208
	209	/* setup irqaction */
	210	setup_irq(SGI_TIMER_IRQ, irq);
	211	}
	212
	213	void __init ip22_time_init(void)
	214	{
	215	/* setup hookup functions */
d23ee8fe YY	216	rtc_mips_get_time = indy_rtc_get_time;
d23ee8fe YY	217	rtc_mips_set_time = indy_rtc_set_time;
1da177e4 LT	218
1da177e4 LT	219	board_time_init = indy_time_init;
1da177e4	220	}