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e30ec452
TS		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18
19#include <asm/inst.h>
20#include <asm/elf.h>
21#include <asm/bugs.h>
3482d713 22#include <asm/uasm.h>
e30ec452
TS		 23
24enum fields {
25 RS = 0x001,
26 RT = 0x002,
27 RD = 0x004,
28 RE = 0x008,
29 SIMM = 0x010,
30 UIMM = 0x020,
31 BIMM = 0x040,
32 JIMM = 0x080,
33 FUNC = 0x100,
58b9e223
DD		 34 SET = 0x200,
35 SCIMM = 0x400
e30ec452
TS		 36};
37
38#define OP_MASK 0x3f
39#define OP_SH 26
40#define RS_MASK 0x1f
41#define RS_SH 21
42#define RT_MASK 0x1f
43#define RT_SH 16
44#define RD_MASK 0x1f
45#define RD_SH 11
46#define RE_MASK 0x1f
47#define RE_SH 6
48#define IMM_MASK 0xffff
49#define IMM_SH 0
50#define JIMM_MASK 0x3ffffff
51#define JIMM_SH 0
52#define FUNC_MASK 0x3f
53#define FUNC_SH 0
54#define SET_MASK 0x7
55#define SET_SH 0
58b9e223
DD		 56#define SCIMM_MASK 0xfffff
57#define SCIMM_SH 6
e30ec452
TS		 58
59enum opcode {
60 insn_invalid,
61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
fb2a27e7
TS		 63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
de6d5b55
DD		 65 insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
66 insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
67 insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
68 insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
69 insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
70 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
5b97c3f7 71 insn_dins, insn_syscall, insn_bbit0, insn_bbit1
e30ec452
TS		 72};
73
74struct insn {
75 enum opcode opcode;
76 u32 match;
77 enum fields fields;
78};
79
80/* This macro sets the non-variable bits of an instruction. */
81#define M(a, b, c, d, e, f) \
82 ((a) << OP_SH \
83 | (b) << RS_SH \
84 | (c) << RT_SH \
85 | (d) << RD_SH \
86 | (e) << RE_SH \
87 | (f) << FUNC_SH)
88
22b0763a 89static struct insn insn_table[] __uasminitdata = {
e30ec452
TS		 90 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
91 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
92 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
93 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
94 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
95 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
96 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
97 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
98 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
99 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
100 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
fb2a27e7 101 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
e30ec452
TS		 102 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
104 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
105 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
106 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
107 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
108 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
109 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
110 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
92078e06 111 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
de6d5b55 112 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
e30ec452
TS		 113 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
114 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
115 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
116 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
117 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
118 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
119 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
120 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
122 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
124 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
5808184f 125 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
e30ec452 126 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
fb2a27e7 127 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
e30ec452
TS		 128 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
129 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
130 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
131 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
132 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
133 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
134 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
32546f38 135 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
e30ec452
TS		 136 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
137 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
138 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
32546f38 139 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
e30ec452
TS		 140 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
141 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
142 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
143 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
92078e06 144 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
58b9e223 145 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
5b97c3f7
DD		 146 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
147 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
e30ec452
TS		 148 { insn_invalid, 0, 0 }
149};
150
151#undef M
152
22b0763a 153static inline __uasminit u32 build_rs(u32 arg)
e30ec452
TS		 154{
155 if (arg & ~RS_MASK)
156 printk(KERN_WARNING "Micro-assembler field overflow\n");
157
158 return (arg & RS_MASK) << RS_SH;
159}
160
22b0763a 161static inline __uasminit u32 build_rt(u32 arg)
e30ec452
TS		 162{
163 if (arg & ~RT_MASK)
164 printk(KERN_WARNING "Micro-assembler field overflow\n");
165
166 return (arg & RT_MASK) << RT_SH;
167}
168
22b0763a 169static inline __uasminit u32 build_rd(u32 arg)
e30ec452
TS		 170{
171 if (arg & ~RD_MASK)
172 printk(KERN_WARNING "Micro-assembler field overflow\n");
173
174 return (arg & RD_MASK) << RD_SH;
175}
176
22b0763a 177static inline __uasminit u32 build_re(u32 arg)
e30ec452
TS		 178{
179 if (arg & ~RE_MASK)
180 printk(KERN_WARNING "Micro-assembler field overflow\n");
181
182 return (arg & RE_MASK) << RE_SH;
183}
184
22b0763a 185static inline __uasminit u32 build_simm(s32 arg)
e30ec452
TS		 186{
187 if (arg > 0x7fff || arg < -0x8000)
188 printk(KERN_WARNING "Micro-assembler field overflow\n");
189
190 return arg & 0xffff;
191}
192
22b0763a 193static inline __uasminit u32 build_uimm(u32 arg)
e30ec452
TS		 194{
195 if (arg & ~IMM_MASK)
196 printk(KERN_WARNING "Micro-assembler field overflow\n");
197
198 return arg & IMM_MASK;
199}
200
22b0763a 201static inline __uasminit u32 build_bimm(s32 arg)
e30ec452
TS		 202{
203 if (arg > 0x1ffff || arg < -0x20000)
204 printk(KERN_WARNING "Micro-assembler field overflow\n");
205
206 if (arg & 0x3)
207 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
208
209 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
210}
211
22b0763a 212static inline __uasminit u32 build_jimm(u32 arg)
e30ec452
TS		 213{
214 if (arg & ~((JIMM_MASK) << 2))
215 printk(KERN_WARNING "Micro-assembler field overflow\n");
216
217 return (arg >> 2) & JIMM_MASK;
218}
219
22b0763a 220static inline __uasminit u32 build_scimm(u32 arg)
58b9e223
DD		 221{
222 if (arg & ~SCIMM_MASK)
223 printk(KERN_WARNING "Micro-assembler field overflow\n");
224
225 return (arg & SCIMM_MASK) << SCIMM_SH;
226}
227
22b0763a 228static inline __uasminit u32 build_func(u32 arg)
e30ec452
TS		 229{
230 if (arg & ~FUNC_MASK)
231 printk(KERN_WARNING "Micro-assembler field overflow\n");
232
233 return arg & FUNC_MASK;
234}
235
22b0763a 236static inline __uasminit u32 build_set(u32 arg)
e30ec452
TS		 237{
238 if (arg & ~SET_MASK)
239 printk(KERN_WARNING "Micro-assembler field overflow\n");
240
241 return arg & SET_MASK;
242}
243
244/*
245 * The order of opcode arguments is implicitly left to right,
246 * starting with RS and ending with FUNC or IMM.
247 */
22b0763a 248static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
e30ec452
TS		 249{
250 struct insn *ip = NULL;
251 unsigned int i;
252 va_list ap;
253 u32 op;
254
255 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
256 if (insn_table[i].opcode == opc) {
257 ip = &insn_table[i];
258 break;
259 }
260
261 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
262 panic("Unsupported Micro-assembler instruction %d", opc);
263
264 op = ip->match;
265 va_start(ap, opc);
266 if (ip->fields & RS)
267 op |= build_rs(va_arg(ap, u32));
268 if (ip->fields & RT)
269 op |= build_rt(va_arg(ap, u32));
270 if (ip->fields & RD)
271 op |= build_rd(va_arg(ap, u32));
272 if (ip->fields & RE)
273 op |= build_re(va_arg(ap, u32));
274 if (ip->fields & SIMM)
275 op |= build_simm(va_arg(ap, s32));
276 if (ip->fields & UIMM)
277 op |= build_uimm(va_arg(ap, u32));
278 if (ip->fields & BIMM)
279 op |= build_bimm(va_arg(ap, s32));
280 if (ip->fields & JIMM)
281 op |= build_jimm(va_arg(ap, u32));
282 if (ip->fields & FUNC)
283 op |= build_func(va_arg(ap, u32));
284 if (ip->fields & SET)
285 op |= build_set(va_arg(ap, u32));
58b9e223
DD		 286 if (ip->fields & SCIMM)
287 op |= build_scimm(va_arg(ap, u32));
e30ec452
TS		 288 va_end(ap);
289
290 **buf = op;
291 (*buf)++;
292}
293
294#define I_u1u2u3(op) \
295Ip_u1u2u3(op) \
296{ \
297 build_insn(buf, insn##op, a, b, c); \
22b0763a
DD		 298} \
299UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 300
301#define I_u2u1u3(op) \
302Ip_u2u1u3(op) \
303{ \
304 build_insn(buf, insn##op, b, a, c); \
22b0763a
DD		 305} \
306UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 307
308#define I_u3u1u2(op) \
309Ip_u3u1u2(op) \
310{ \
311 build_insn(buf, insn##op, b, c, a); \
22b0763a
DD		 312} \
313UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 314
315#define I_u1u2s3(op) \
316Ip_u1u2s3(op) \
317{ \
318 build_insn(buf, insn##op, a, b, c); \
22b0763a
DD		 319} \
320UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 321
322#define I_u2s3u1(op) \
323Ip_u2s3u1(op) \
324{ \
325 build_insn(buf, insn##op, c, a, b); \
22b0763a
DD		 326} \
327UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 328
329#define I_u2u1s3(op) \
330Ip_u2u1s3(op) \
331{ \
332 build_insn(buf, insn##op, b, a, c); \
22b0763a
DD		 333} \
334UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 335
92078e06
DD		 336#define I_u2u1msbu3(op) \
337Ip_u2u1msbu3(op) \
338{ \
339 build_insn(buf, insn##op, b, a, c+d-1, c); \
22b0763a
DD		 340} \
341UASM_EXPORT_SYMBOL(uasm_i##op);
92078e06 342
e30ec452
TS		 343#define I_u1u2(op) \
344Ip_u1u2(op) \
345{ \
346 build_insn(buf, insn##op, a, b); \
22b0763a
DD		 347} \
348UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 349
350#define I_u1s2(op) \
351Ip_u1s2(op) \
352{ \
353 build_insn(buf, insn##op, a, b); \
22b0763a
DD		 354} \
355UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 356
357#define I_u1(op) \
358Ip_u1(op) \
359{ \
360 build_insn(buf, insn##op, a); \
22b0763a
DD		 361} \
362UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 363
364#define I_0(op) \
365Ip_0(op) \
366{ \
367 build_insn(buf, insn##op); \
22b0763a
DD		 368} \
369UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452
TS		 370
371I_u2u1s3(_addiu)
372I_u3u1u2(_addu)
373I_u2u1u3(_andi)
374I_u3u1u2(_and)
375I_u1u2s3(_beq)
376I_u1u2s3(_beql)
377I_u1s2(_bgez)
378I_u1s2(_bgezl)
379I_u1s2(_bltz)
380I_u1s2(_bltzl)
381I_u1u2s3(_bne)
fb2a27e7 382I_u2s3u1(_cache)
e30ec452
TS		 383I_u1u2u3(_dmfc0)
384I_u1u2u3(_dmtc0)
385I_u2u1s3(_daddiu)
386I_u3u1u2(_daddu)
387I_u2u1u3(_dsll)
388I_u2u1u3(_dsll32)
389I_u2u1u3(_dsra)
390I_u2u1u3(_dsrl)
391I_u2u1u3(_dsrl32)
92078e06 392I_u2u1u3(_drotr)
de6d5b55 393I_u2u1u3(_drotr32)
e30ec452
TS		 394I_u3u1u2(_dsubu)
395I_0(_eret)
396I_u1(_j)
397I_u1(_jal)
398I_u1(_jr)
399I_u2s3u1(_ld)
400I_u2s3u1(_ll)
401I_u2s3u1(_lld)
402I_u1s2(_lui)
403I_u2s3u1(_lw)
404I_u1u2u3(_mfc0)
405I_u1u2u3(_mtc0)
406I_u2u1u3(_ori)
5808184f 407I_u3u1u2(_or)
e30ec452
TS		 408I_0(_rfe)
409I_u2s3u1(_sc)
410I_u2s3u1(_scd)
411I_u2s3u1(_sd)
412I_u2u1u3(_sll)
413I_u2u1u3(_sra)
414I_u2u1u3(_srl)
32546f38 415I_u2u1u3(_rotr)
e30ec452
TS		 416I_u3u1u2(_subu)
417I_u2s3u1(_sw)
418I_0(_tlbp)
32546f38 419I_0(_tlbr)
e30ec452
TS		 420I_0(_tlbwi)
421I_0(_tlbwr)
422I_u3u1u2(_xor)
423I_u2u1u3(_xori)
92078e06 424I_u2u1msbu3(_dins);
58b9e223 425I_u1(_syscall);
5b97c3f7
DD		 426I_u1u2s3(_bbit0);
427I_u1u2s3(_bbit1);
e30ec452 428
c9941158
DD		 429#ifdef CONFIG_CPU_CAVIUM_OCTEON
430#include <asm/octeon/octeon.h>
431void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
432 unsigned int c)
433{
434 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
435 /*
436 * As per erratum Core-14449, replace prefetches 0-4,
437 * 6-24 with 'pref 28'.
438 */
439 build_insn(buf, insn_pref, c, 28, b);
440 else
441 build_insn(buf, insn_pref, c, a, b);
442}
443UASM_EXPORT_SYMBOL(uasm_i_pref);
444#else
445I_u2s3u1(_pref)
446#endif
447
e30ec452 448/* Handle labels. */
22b0763a 449void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
e30ec452
TS		 450{
451 (*lab)->addr = addr;
452 (*lab)->lab = lid;
453 (*lab)++;
454}
22b0763a 455UASM_EXPORT_SYMBOL(uasm_build_label);
e30ec452 456
22b0763a 457int __uasminit uasm_in_compat_space_p(long addr)
e30ec452
TS		 458{
459 /* Is this address in 32bit compat space? */
460#ifdef CONFIG_64BIT
461 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
462#else
463 return 1;
464#endif
465}
22b0763a 466UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
e30ec452 467
22b0763a 468static int __uasminit uasm_rel_highest(long val)
e30ec452
TS		 469{
470#ifdef CONFIG_64BIT
471 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
472#else
473 return 0;
474#endif
475}
476
22b0763a 477static int __uasminit uasm_rel_higher(long val)
e30ec452
TS		 478{
479#ifdef CONFIG_64BIT
480 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
481#else
482 return 0;
483#endif
484}
485
22b0763a 486int __uasminit uasm_rel_hi(long val)
e30ec452
TS		 487{
488 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
489}
22b0763a 490UASM_EXPORT_SYMBOL(uasm_rel_hi);
e30ec452 491
22b0763a 492int __uasminit uasm_rel_lo(long val)
e30ec452
TS		 493{
494 return ((val & 0xffff) ^ 0x8000) - 0x8000;
495}
22b0763a 496UASM_EXPORT_SYMBOL(uasm_rel_lo);
e30ec452 497
22b0763a 498void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
e30ec452
TS		 499{
500 if (!uasm_in_compat_space_p(addr)) {
501 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
502 if (uasm_rel_higher(addr))
503 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
504 if (uasm_rel_hi(addr)) {
505 uasm_i_dsll(buf, rs, rs, 16);
506 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
507 uasm_i_dsll(buf, rs, rs, 16);
508 } else
509 uasm_i_dsll32(buf, rs, rs, 0);
510 } else
511 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
512}
22b0763a 513UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
e30ec452 514
22b0763a 515void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
e30ec452
TS		 516{
517 UASM_i_LA_mostly(buf, rs, addr);
518 if (uasm_rel_lo(addr)) {
519 if (!uasm_in_compat_space_p(addr))
520 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
521 else
522 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
523 }
524}
22b0763a 525UASM_EXPORT_SYMBOL(UASM_i_LA);
e30ec452
TS		 526
527/* Handle relocations. */
22b0763a 528void __uasminit
e30ec452
TS		 529uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
530{
531 (*rel)->addr = addr;
532 (*rel)->type = R_MIPS_PC16;
533 (*rel)->lab = lid;
534 (*rel)++;
535}
22b0763a 536UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
e30ec452 537
22b0763a 538static inline void __uasminit
e30ec452
TS		 539__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
540{
541 long laddr = (long)lab->addr;
542 long raddr = (long)rel->addr;
543
544 switch (rel->type) {
545 case R_MIPS_PC16:
546 *rel->addr |= build_bimm(laddr - (raddr + 4));
547 break;
548
549 default:
550 panic("Unsupported Micro-assembler relocation %d",
551 rel->type);
552 }
553}
554
22b0763a 555void __uasminit
e30ec452
TS		 556uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
557{
558 struct uasm_label *l;
559
560 for (; rel->lab != UASM_LABEL_INVALID; rel++)
561 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
562 if (rel->lab == l->lab)
563 __resolve_relocs(rel, l);
564}
22b0763a 565UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
e30ec452 566
22b0763a 567void __uasminit
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TS		 568uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
569{
570 for (; rel->lab != UASM_LABEL_INVALID; rel++)
571 if (rel->addr >= first && rel->addr < end)
572 rel->addr += off;
573}
22b0763a 574UASM_EXPORT_SYMBOL(uasm_move_relocs);
e30ec452 575
22b0763a 576void __uasminit
e30ec452
TS		 577uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
578{
579 for (; lab->lab != UASM_LABEL_INVALID; lab++)
580 if (lab->addr >= first && lab->addr < end)
581 lab->addr += off;
582}
22b0763a 583UASM_EXPORT_SYMBOL(uasm_move_labels);
e30ec452 584
22b0763a 585void __uasminit
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TS		 586uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
587 u32 *end, u32 *target)
588{
589 long off = (long)(target - first);
590
591 memcpy(target, first, (end - first) * sizeof(u32));
592
593 uasm_move_relocs(rel, first, end, off);
594 uasm_move_labels(lab, first, end, off);
595}
22b0763a 596UASM_EXPORT_SYMBOL(uasm_copy_handler);
e30ec452 597
22b0763a 598int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
e30ec452
TS		 599{
600 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
601 if (rel->addr == addr
602 && (rel->type == R_MIPS_PC16
603 || rel->type == R_MIPS_26))
604 return 1;
605 }
606
607 return 0;
608}
22b0763a 609UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
e30ec452
TS		 610
611/* Convenience functions for labeled branches. */
22b0763a 612void __uasminit
e30ec452
TS		 613uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
614{
615 uasm_r_mips_pc16(r, *p, lid);
616 uasm_i_bltz(p, reg, 0);
617}
22b0763a 618UASM_EXPORT_SYMBOL(uasm_il_bltz);
e30ec452 619
22b0763a 620void __uasminit
e30ec452
TS		 621uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
622{
623 uasm_r_mips_pc16(r, *p, lid);
624 uasm_i_b(p, 0);
625}
22b0763a 626UASM_EXPORT_SYMBOL(uasm_il_b);
e30ec452 627
22b0763a 628void __uasminit
e30ec452
TS		 629uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
630{
631 uasm_r_mips_pc16(r, *p, lid);
632 uasm_i_beqz(p, reg, 0);
633}
22b0763a 634UASM_EXPORT_SYMBOL(uasm_il_beqz);
e30ec452 635
22b0763a 636void __uasminit
e30ec452
TS		 637uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
638{
639 uasm_r_mips_pc16(r, *p, lid);
640 uasm_i_beqzl(p, reg, 0);
641}
22b0763a 642UASM_EXPORT_SYMBOL(uasm_il_beqzl);
e30ec452 643
22b0763a 644void __uasminit
fb2a27e7
TS		 645uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
646 unsigned int reg2, int lid)
647{
648 uasm_r_mips_pc16(r, *p, lid);
649 uasm_i_bne(p, reg1, reg2, 0);
650}
22b0763a 651UASM_EXPORT_SYMBOL(uasm_il_bne);
fb2a27e7 652
22b0763a 653void __uasminit
e30ec452
TS		 654uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
655{
656 uasm_r_mips_pc16(r, *p, lid);
657 uasm_i_bnez(p, reg, 0);
658}
22b0763a 659UASM_EXPORT_SYMBOL(uasm_il_bnez);
e30ec452 660
22b0763a 661void __uasminit
e30ec452
TS		 662uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
663{
664 uasm_r_mips_pc16(r, *p, lid);
665 uasm_i_bgezl(p, reg, 0);
666}
22b0763a 667UASM_EXPORT_SYMBOL(uasm_il_bgezl);
e30ec452 668
22b0763a 669void __uasminit
e30ec452
TS		 670uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
671{
672 uasm_r_mips_pc16(r, *p, lid);
673 uasm_i_bgez(p, reg, 0);
674}
22b0763a 675UASM_EXPORT_SYMBOL(uasm_il_bgez);
5b97c3f7 676
22b0763a 677void __uasminit
5b97c3f7
DD		 678uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
679 unsigned int bit, int lid)
680{
681 uasm_r_mips_pc16(r, *p, lid);
682 uasm_i_bbit0(p, reg, bit, 0);
683}
22b0763a 684UASM_EXPORT_SYMBOL(uasm_il_bbit0);
5b97c3f7 685
22b0763a 686void __uasminit
5b97c3f7
DD		 687uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
688 unsigned int bit, int lid)
689{
690 uasm_r_mips_pc16(r, *p, lid);
691 uasm_i_bbit1(p, reg, bit, 0);
692}
22b0763a 693UASM_EXPORT_SYMBOL(uasm_il_bbit1);
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