[net-next-2.6.git] / arch / mips / mm / cerr-sb1.c

/*
 * Copyright (C) 2001,2002,2003 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/sched.h>
#include <asm/mipsregs.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>

#if !defined(CONFIG_SIBYTE_BUS_WATCHER) || defined(CONFIG_SIBYTE_BW_TRACE)
#include <asm/io.h>
#include <asm/sibyte/sb1250_scd.h>
#endif

/*
 * We'd like to dump the L2_ECC_TAG register on errors, but errata make
 * that unsafe... So for now we don't.  (BCM1250/BCM112x erratum SOC-48.)
 */
#undef DUMP_L2_ECC_TAG_ON_ERROR

/* SB1 definitions */

/* XXX should come from config1 XXX */
#define SB1_CACHE_INDEX_MASK   0x1fe0

#define CP0_ERRCTL_RECOVERABLE (1 << 31)
#define CP0_ERRCTL_DCACHE      (1 << 30)
#define CP0_ERRCTL_ICACHE      (1 << 29)
#define CP0_ERRCTL_MULTIBUS    (1 << 23)
#define CP0_ERRCTL_MC_TLB      (1 << 15)
#define CP0_ERRCTL_MC_TIMEOUT  (1 << 14)

#define CP0_CERRI_TAG_PARITY   (1 << 29)
#define CP0_CERRI_DATA_PARITY  (1 << 28)
#define CP0_CERRI_EXTERNAL     (1 << 26)

#define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL))
#define CP0_CERRI_DATA         (CP0_CERRI_DATA_PARITY)

#define CP0_CERRD_MULTIPLE     (1 << 31)
#define CP0_CERRD_TAG_STATE    (1 << 30)
#define CP0_CERRD_TAG_ADDRESS  (1 << 29)
#define CP0_CERRD_DATA_SBE     (1 << 28)
#define CP0_CERRD_DATA_DBE     (1 << 27)
#define CP0_CERRD_EXTERNAL     (1 << 26)
#define CP0_CERRD_LOAD         (1 << 25)
#define CP0_CERRD_STORE        (1 << 24)
#define CP0_CERRD_FILLWB       (1 << 23)
#define CP0_CERRD_COHERENCY    (1 << 22)
#define CP0_CERRD_DUPTAG       (1 << 21)

#define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL))
#define CP0_CERRD_IDX_VALID(c) \
   (((c) & (CP0_CERRD_LOAD | CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0)
#define CP0_CERRD_CAUSES \
   (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG)
#define CP0_CERRD_TYPES \
   (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL)
#define CP0_CERRD_DATA         (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE)

static uint32_t	extract_ic(unsigned short addr, int data);
static uint32_t	extract_dc(unsigned short addr, int data);

static inline void breakout_errctl(unsigned int val)
{
	if (val & CP0_ERRCTL_RECOVERABLE)
		printk(" recoverable");
	if (val & CP0_ERRCTL_DCACHE)
		printk(" dcache");
	if (val & CP0_ERRCTL_ICACHE)
		printk(" icache");
	if (val & CP0_ERRCTL_MULTIBUS)
		printk(" multiple-buserr");
	printk("\n");
}

static inline void breakout_cerri(unsigned int val)
{
	if (val & CP0_CERRI_TAG_PARITY)
		printk(" tag-parity");
	if (val & CP0_CERRI_DATA_PARITY)
		printk(" data-parity");
	if (val & CP0_CERRI_EXTERNAL)
		printk(" external");
	printk("\n");
}

static inline void breakout_cerrd(unsigned int val)
{
	switch (val & CP0_CERRD_CAUSES) {
	case CP0_CERRD_LOAD:
		printk(" load,");
		break;
	case CP0_CERRD_STORE:
		printk(" store,");
		break;
	case CP0_CERRD_FILLWB:
		printk(" fill/wb,");
		break;
	case CP0_CERRD_COHERENCY:
		printk(" coherency,");
		break;
	case CP0_CERRD_DUPTAG:
		printk(" duptags,");
		break;
	default:
		printk(" NO CAUSE,");
		break;
	}
	if (!(val & CP0_CERRD_TYPES))
		printk(" NO TYPE");
	else {
		if (val & CP0_CERRD_MULTIPLE)
			printk(" multi-err");
		if (val & CP0_CERRD_TAG_STATE)
			printk(" tag-state");
		if (val & CP0_CERRD_TAG_ADDRESS)
			printk(" tag-address");
		if (val & CP0_CERRD_DATA_SBE)
			printk(" data-SBE");
		if (val & CP0_CERRD_DATA_DBE)
			printk(" data-DBE");
		if (val & CP0_CERRD_EXTERNAL)
			printk(" external");
	}
	printk("\n");
}

#ifndef CONFIG_SIBYTE_BUS_WATCHER

static void check_bus_watcher(void)
{
	uint32_t status, l2_err, memio_err;
#ifdef DUMP_L2_ECC_TAG_ON_ERROR
	uint64_t l2_tag;
#endif

	/* Destructive read, clears register and interrupt */
	status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
	/* Bit 31 is always on, but there's no #define for that */
	if (status & ~(1UL << 31)) {
		l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
#ifdef DUMP_L2_ECC_TAG_ON_ERROR
		l2_tag = in64(IOADDR(A_L2_ECC_TAG));
#endif
		memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
		printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
		printk("\nLast recorded signature:\n");
		printk("Request %02x from %d, answered by %d with Dcode %d\n",
		       (unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
		       (int)(G_SCD_BERR_TID(status) >> 6),
		       (int)G_SCD_BERR_RID(status),
		       (int)G_SCD_BERR_DCODE(status));
#ifdef DUMP_L2_ECC_TAG_ON_ERROR
		printk("Last L2 tag w/ bad ECC: %016llx\n", l2_tag);
#endif
	} else {
		printk("Bus watcher indicates no error\n");
	}
}
#else
extern void check_bus_watcher(void);
#endif

asmlinkage void sb1_cache_error(void)
{
	uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res;
	unsigned long long cerr_dpa;

#ifdef CONFIG_SIBYTE_BW_TRACE
	/* Freeze the trace buffer now */
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
	csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
#else
	csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
#endif
	printk("Trace buffer frozen\n");
#endif

	printk("Cache error exception on CPU %x:\n",
	       (read_c0_prid() >> 25) & 0x7);

	__asm__ __volatile__ (
	"	.set	push\n\t"
	"	.set	mips64\n\t"
	"	.set	noat\n\t"
	"	mfc0	%0, $26\n\t"
	"	mfc0	%1, $27\n\t"
	"	mfc0	%2, $27, 1\n\t"
	"	dmfc0	$1, $27, 3\n\t"
	"	dsrl32	%3, $1, 0 \n\t"
	"	sll	%4, $1, 0 \n\t"
	"	mfc0	%5, $30\n\t"
	"	.set	pop"
	: "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d),
	  "=r" (dpahi), "=r" (dpalo), "=r" (eepc));

	cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo;
	printk(" c0_errorepc ==   %08x\n", eepc);
	printk(" c0_errctl   ==   %08x", errctl);
	breakout_errctl(errctl);
	if (errctl & CP0_ERRCTL_ICACHE) {
		printk(" c0_cerr_i   ==   %08x", cerr_i);
		breakout_cerri(cerr_i);
		if (CP0_CERRI_IDX_VALID(cerr_i)) {
			/* Check index of EPC, allowing for delay slot */
			if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) &&
			    ((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4)))
				printk(" cerr_i idx doesn't match eepc\n");
			else {
				res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK,
						 (cerr_i & CP0_CERRI_DATA) != 0);
				if (!(res & cerr_i))
					printk("...didn't see indicated icache problem\n");
			}
		}
	}
	if (errctl & CP0_ERRCTL_DCACHE) {
		printk(" c0_cerr_d   ==   %08x", cerr_d);
		breakout_cerrd(cerr_d);
		if (CP0_CERRD_DPA_VALID(cerr_d)) {
			printk(" c0_cerr_dpa == %010llx\n", cerr_dpa);
			if (!CP0_CERRD_IDX_VALID(cerr_d)) {
				res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK,
						 (cerr_d & CP0_CERRD_DATA) != 0);
				if (!(res & cerr_d))
					printk("...didn't see indicated dcache problem\n");
			} else {
				if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK))
					printk(" cerr_d idx doesn't match cerr_dpa\n");
				else {
					res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK,
							 (cerr_d & CP0_CERRD_DATA) != 0);
					if (!(res & cerr_d))
						printk("...didn't see indicated problem\n");
				}
			}
		}
	}

	check_bus_watcher();

	/*
	 * Calling panic() when a fatal cache error occurs scrambles the
	 * state of the system (and the cache), making it difficult to
	 * investigate after the fact.  However, if you just stall the CPU,
	 * the other CPU may keep on running, which is typically very
	 * undesirable.
	 */
#ifdef CONFIG_SB1_CERR_STALL
	while (1)
		;
#else
	panic("unhandled cache error");
#endif
}


/* Parity lookup table. */
static const uint8_t parity[256] = {
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0
};

/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
static const uint64_t mask_72_64[8] = {
	0x0738C808099264FFULL,
	0x38C808099264FF07ULL,
	0xC808099264FF0738ULL,
	0x08099264FF0738C8ULL,
	0x099264FF0738C808ULL,
	0x9264FF0738C80809ULL,
	0x64FF0738C8080992ULL,
	0xFF0738C808099264ULL
};

/* Calculate the parity on a range of bits */
static char range_parity(uint64_t dword, int max, int min)
{
	char parity = 0;
	int i;
	dword >>= min;
	for (i=max-min; i>=0; i--) {
		if (dword & 0x1)
			parity = !parity;
		dword >>= 1;
	}
	return parity;
}

/* Calculate the 4-bit even byte-parity for an instruction */
static unsigned char inst_parity(uint32_t word)
{
	int i, j;
	char parity = 0;
	for (j=0; j<4; j++) {
		char byte_parity = 0;
		for (i=0; i<8; i++) {
			if (word & 0x80000000)
				byte_parity = !byte_parity;
			word <<= 1;
		}
		parity <<= 1;
		parity |= byte_parity;
	}
	return parity;
}

static uint32_t extract_ic(unsigned short addr, int data)
{
	unsigned short way;
	int valid;
	uint32_t taghi, taglolo, taglohi;
	unsigned long long taglo, va;
	uint64_t tlo_tmp;
	uint8_t lru;
	int res = 0;

	printk("Icache index 0x%04x  ", addr);
	for (way = 0; way < 4; way++) {
		/* Index-load-tag-I */
		__asm__ __volatile__ (
		"	.set	push		\n\t"
		"	.set	noreorder	\n\t"
		"	.set	mips64		\n\t"
		"	.set	noat		\n\t"
		"	cache	4, 0(%3)	\n\t"
		"	mfc0	%0, $29		\n\t"
		"	dmfc0	$1, $28		\n\t"
		"	dsrl32	%1, $1, 0	\n\t"
		"	sll	%2, $1, 0	\n\t"
		"	.set	pop"
		: "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
		: "r" ((way << 13) | addr));

		taglo = ((unsigned long long)taglohi << 32) | taglolo;
		if (way == 0) {
			lru = (taghi >> 14) & 0xff;
			printk("[Bank %d Set 0x%02x]  LRU > %d %d %d %d > MRU\n",
				    ((addr >> 5) & 0x3), /* bank */
				    ((addr >> 7) & 0x3f), /* index */
				    (lru & 0x3),
				    ((lru >> 2) & 0x3),
				    ((lru >> 4) & 0x3),
				    ((lru >> 6) & 0x3));
		}
		va = (taglo & 0xC0000FFFFFFFE000ULL) | addr;
		if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3))
			va |= 0x3FFFF00000000000ULL;
		valid = ((taghi >> 29) & 1);
		if (valid) {
			tlo_tmp = taglo & 0xfff3ff;
			if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) {
				printk("   ** bad parity in VTag0/G/ASID\n");
				res |= CP0_CERRI_TAG_PARITY;
			}
			if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) {
				printk("   ** bad parity in R/VTag1\n");
				res |= CP0_CERRI_TAG_PARITY;
			}
		}
		if (valid ^ ((taghi >> 27) & 1)) {
			printk("   ** bad parity for valid bit\n");
			res |= CP0_CERRI_TAG_PARITY;
		}
		printk(" %d  [VA %016llx]  [Vld? %d]  raw tags: %08X-%016llX\n",
			    way, va, valid, taghi, taglo);

		if (data) {
			uint32_t datahi, insta, instb;
			uint8_t predecode;
			int offset;

			/* (hit all banks and ways) */
			for (offset = 0; offset < 4; offset++) {
				/* Index-load-data-I */
				__asm__ __volatile__ (
				"	.set	push\n\t"
				"	.set	noreorder\n\t"
				"	.set	mips64\n\t"
				"	.set	noat\n\t"
				"	cache	6, 0(%3)  \n\t"
				"	mfc0	%0, $29, 1\n\t"
				"	dmfc0  $1, $28, 1\n\t"
				"	dsrl32 %1, $1, 0 \n\t"
				"	sll    %2, $1, 0 \n\t"
				"	.set	pop         \n"
				: "=r" (datahi), "=r" (insta), "=r" (instb)
				: "r" ((way << 13) | addr | (offset << 3)));
				predecode = (datahi >> 8) & 0xff;
				if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) {
					printk("   ** bad parity in predecode\n");
					res |= CP0_CERRI_DATA_PARITY;
				}
				/* XXXKW should/could check predecode bits themselves */
				if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) {
					printk("   ** bad parity in instruction a\n");
					res |= CP0_CERRI_DATA_PARITY;
				}
				if ((datahi & 0xf) ^ inst_parity(instb)) {
					printk("   ** bad parity in instruction b\n");
					res |= CP0_CERRI_DATA_PARITY;
				}
				printk("  %05X-%08X%08X", datahi, insta, instb);
			}
			printk("\n");
		}
	}
	return res;
}

/* Compute the ECC for a data doubleword */
static uint8_t dc_ecc(uint64_t dword)
{
	uint64_t t;
	uint32_t w;
	uint8_t  p;
	int      i;

	p = 0;
	for (i = 7; i >= 0; i--)
	{
		p <<= 1;
		t = dword & mask_72_64[i];
		w = (uint32_t)(t >> 32);
		p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
		      ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
		w = (uint32_t)(t & 0xFFFFFFFF);
		p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
		      ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
	}
	return p;
}

struct dc_state {
	unsigned char val;
	char *name;
};

static struct dc_state dc_states[] = {
	{ 0x00, "INVALID" },
	{ 0x0f, "COH-SHD" },
	{ 0x13, "NCO-E-C" },
	{ 0x19, "NCO-E-D" },
	{ 0x16, "COH-E-C" },
	{ 0x1c, "COH-E-D" },
	{ 0xff, "*ERROR*" }
};

#define DC_TAG_VALID(state) \
    (((state) == 0x0) || ((state) == 0xf) || ((state) == 0x13) || \
     ((state) == 0x19) || ((state) == 0x16) || ((state) == 0x1c))

static char *dc_state_str(unsigned char state)
{
	struct dc_state *dsc = dc_states;
	while (dsc->val != 0xff) {
		if (dsc->val == state)
			break;
		dsc++;
	}
	return dsc->name;
}

static uint32_t extract_dc(unsigned short addr, int data)
{
	int valid, way;
	unsigned char state;
	uint32_t taghi, taglolo, taglohi;
	unsigned long long taglo, pa;
	uint8_t ecc, lru;
	int res = 0;

	printk("Dcache index 0x%04x  ", addr);
	for (way = 0; way < 4; way++) {
		__asm__ __volatile__ (
		"	.set	push\n\t"
		"	.set	noreorder\n\t"
		"	.set	mips64\n\t"
		"	.set	noat\n\t"
		"	cache	5, 0(%3)\n\t"	/* Index-load-tag-D */
		"	mfc0	%0, $29, 2\n\t"
		"	dmfc0	$1, $28, 2\n\t"
		"	dsrl32	%1, $1, 0\n\t"
		"	sll	%2, $1, 0\n\t"
		"	.set	pop"
		: "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
		: "r" ((way << 13) | addr));

		taglo = ((unsigned long long)taglohi << 32) | taglolo;
		pa = (taglo & 0xFFFFFFE000ULL) | addr;
		if (way == 0) {
			lru = (taghi >> 14) & 0xff;
			printk("[Bank %d Set 0x%02x]  LRU > %d %d %d %d > MRU\n",
				    ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */
				    ((addr >> 6) & 0x3f), /* index */
				    (lru & 0x3),
				    ((lru >> 2) & 0x3),
				    ((lru >> 4) & 0x3),
				    ((lru >> 6) & 0x3));
		}
		state = (taghi >> 25) & 0x1f;
		valid = DC_TAG_VALID(state);
		printk(" %d  [PA %010llx]  [state %s (%02x)]  raw tags: %08X-%016llX\n",
			    way, pa, dc_state_str(state), state, taghi, taglo);
		if (valid) {
			if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) {
				printk("   ** bad parity in PTag1\n");
				res |= CP0_CERRD_TAG_ADDRESS;
			}
			if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) {
				printk("   ** bad parity in PTag0\n");
				res |= CP0_CERRD_TAG_ADDRESS;
			}
		} else {
			res |= CP0_CERRD_TAG_STATE;
		}

		if (data) {
			uint32_t datalohi, datalolo, datahi;
			unsigned long long datalo;
			int offset;
			char bad_ecc = 0;

			for (offset = 0; offset < 4; offset++) {
				/* Index-load-data-D */
				__asm__ __volatile__ (
				"	.set	push\n\t"
				"	.set	noreorder\n\t"
				"	.set	mips64\n\t"
				"	.set	noat\n\t"
				"	cache	7, 0(%3)\n\t" /* Index-load-data-D */
				"	mfc0	%0, $29, 3\n\t"
				"	dmfc0	$1, $28, 3\n\t"
				"	dsrl32	%1, $1, 0 \n\t"
				"	sll	%2, $1, 0 \n\t"
				"	.set	pop"
				: "=r" (datahi), "=r" (datalohi), "=r" (datalolo)
				: "r" ((way << 13) | addr | (offset << 3)));
				datalo = ((unsigned long long)datalohi << 32) | datalolo;
				ecc = dc_ecc(datalo);
				if (ecc != datahi) {
					int bits;
					bad_ecc |= 1 << (3-offset);
					ecc ^= datahi;
					bits = hweight8(ecc);
					res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
				}
				printk("  %02X-%016llX", datahi, datalo);
			}
			printk("\n");
			if (bad_ecc)
				printk("  dwords w/ bad ECC: %d %d %d %d\n",
				       !!(bad_ecc & 8), !!(bad_ecc & 4),
				       !!(bad_ecc & 2), !!(bad_ecc & 1));
		}
	}
	return res;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2001,2002,2003 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*/
1da177e4 LT	18	#include <linux/sched.h>
	19	#include <asm/mipsregs.h>
	20	#include <asm/sibyte/sb1250.h>
a4b5bd9a	21	#include <asm/sibyte/sb1250_regs.h>
1da177e4	22
a4b5bd9a	23	#if !defined(CONFIG_SIBYTE_BUS_WATCHER) \|\| defined(CONFIG_SIBYTE_BW_TRACE)
1da177e4	24	#include <asm/io.h>
1da177e4 LT	25	#include <asm/sibyte/sb1250_scd.h>
1da177e4 LT	26	#endif
42a3b4f2	27
a4b5bd9a AI	28	/*
	29	* We'd like to dump the L2_ECC_TAG register on errors, but errata make
	30	* that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
	31	*/
	32	#undef DUMP_L2_ECC_TAG_ON_ERROR
	33
1da177e4 LT	34	/* SB1 definitions */
	35
	36	/* XXX should come from config1 XXX */
	37	#define SB1_CACHE_INDEX_MASK 0x1fe0
	38
	39	#define CP0_ERRCTL_RECOVERABLE (1 << 31)
	40	#define CP0_ERRCTL_DCACHE (1 << 30)
	41	#define CP0_ERRCTL_ICACHE (1 << 29)
	42	#define CP0_ERRCTL_MULTIBUS (1 << 23)
	43	#define CP0_ERRCTL_MC_TLB (1 << 15)
	44	#define CP0_ERRCTL_MC_TIMEOUT (1 << 14)
	45
	46	#define CP0_CERRI_TAG_PARITY (1 << 29)
	47	#define CP0_CERRI_DATA_PARITY (1 << 28)
	48	#define CP0_CERRI_EXTERNAL (1 << 26)
	49
	50	#define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL))
	51	#define CP0_CERRI_DATA (CP0_CERRI_DATA_PARITY)
	52
	53	#define CP0_CERRD_MULTIPLE (1 << 31)
	54	#define CP0_CERRD_TAG_STATE (1 << 30)
	55	#define CP0_CERRD_TAG_ADDRESS (1 << 29)
	56	#define CP0_CERRD_DATA_SBE (1 << 28)
	57	#define CP0_CERRD_DATA_DBE (1 << 27)
	58	#define CP0_CERRD_EXTERNAL (1 << 26)
	59	#define CP0_CERRD_LOAD (1 << 25)
	60	#define CP0_CERRD_STORE (1 << 24)
	61	#define CP0_CERRD_FILLWB (1 << 23)
	62	#define CP0_CERRD_COHERENCY (1 << 22)
	63	#define CP0_CERRD_DUPTAG (1 << 21)
	64
	65	#define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL))
	66	#define CP0_CERRD_IDX_VALID(c) \
	67	(((c) & (CP0_CERRD_LOAD \| CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0)
	68	#define CP0_CERRD_CAUSES \
	69	(CP0_CERRD_LOAD \| CP0_CERRD_STORE \| CP0_CERRD_FILLWB \| CP0_CERRD_COHERENCY \| CP0_CERRD_DUPTAG)
	70	#define CP0_CERRD_TYPES \
	71	(CP0_CERRD_TAG_STATE \| CP0_CERRD_TAG_ADDRESS \| CP0_CERRD_DATA_SBE \| CP0_CERRD_DATA_DBE \| CP0_CERRD_EXTERNAL)
	72	#define CP0_CERRD_DATA (CP0_CERRD_DATA_SBE \| CP0_CERRD_DATA_DBE)
	73
	74	static uint32_t extract_ic(unsigned short addr, int data);
	75	static uint32_t extract_dc(unsigned short addr, int data);
	76
	77	static inline void breakout_errctl(unsigned int val)
	78	{
	79	if (val & CP0_ERRCTL_RECOVERABLE)
36a88530	80	printk(" recoverable");
1da177e4	81	if (val & CP0_ERRCTL_DCACHE)
36a88530	82	printk(" dcache");
1da177e4	83	if (val & CP0_ERRCTL_ICACHE)
36a88530	84	printk(" icache");
1da177e4	85	if (val & CP0_ERRCTL_MULTIBUS)
36a88530 RB	86	printk(" multiple-buserr");
36a88530 RB	87	printk("\n");
1da177e4 LT	88	}
	89
	90	static inline void breakout_cerri(unsigned int val)
	91	{
	92	if (val & CP0_CERRI_TAG_PARITY)
36a88530	93	printk(" tag-parity");
1da177e4	94	if (val & CP0_CERRI_DATA_PARITY)
36a88530	95	printk(" data-parity");
1da177e4	96	if (val & CP0_CERRI_EXTERNAL)
36a88530 RB	97	printk(" external");
36a88530 RB	98	printk("\n");
1da177e4 LT	99	}
	100
	101	static inline void breakout_cerrd(unsigned int val)
	102	{
	103	switch (val & CP0_CERRD_CAUSES) {
	104	case CP0_CERRD_LOAD:
36a88530	105	printk(" load,");
1da177e4 LT	106	break;
1da177e4 LT	107	case CP0_CERRD_STORE:
36a88530	108	printk(" store,");
1da177e4 LT	109	break;
1da177e4 LT	110	case CP0_CERRD_FILLWB:
36a88530	111	printk(" fill/wb,");
1da177e4 LT	112	break;
1da177e4 LT	113	case CP0_CERRD_COHERENCY:
36a88530	114	printk(" coherency,");
1da177e4 LT	115	break;
1da177e4 LT	116	case CP0_CERRD_DUPTAG:
36a88530	117	printk(" duptags,");
1da177e4 LT	118	break;
1da177e4 LT	119	default:
36a88530	120	printk(" NO CAUSE,");
1da177e4 LT	121	break;
	122	}
	123	if (!(val & CP0_CERRD_TYPES))
36a88530	124	printk(" NO TYPE");
1da177e4 LT	125	else {
1da177e4 LT	126	if (val & CP0_CERRD_MULTIPLE)
36a88530	127	printk(" multi-err");
1da177e4	128	if (val & CP0_CERRD_TAG_STATE)
36a88530	129	printk(" tag-state");
1da177e4	130	if (val & CP0_CERRD_TAG_ADDRESS)
36a88530	131	printk(" tag-address");
1da177e4	132	if (val & CP0_CERRD_DATA_SBE)
36a88530	133	printk(" data-SBE");
1da177e4	134	if (val & CP0_CERRD_DATA_DBE)
36a88530	135	printk(" data-DBE");
1da177e4	136	if (val & CP0_CERRD_EXTERNAL)
36a88530	137	printk(" external");
1da177e4	138	}
36a88530	139	printk("\n");
1da177e4 LT	140	}
	141
	142	#ifndef CONFIG_SIBYTE_BUS_WATCHER
	143
42a3b4f2 RB	144	static void check_bus_watcher(void)
42a3b4f2 RB	145	{
1da177e4	146	uint32_t status, l2_err, memio_err;
a4b5bd9a AI	147	#ifdef DUMP_L2_ECC_TAG_ON_ERROR
	148	uint64_t l2_tag;
	149	#endif
1da177e4 LT	150
	151	/* Destructive read, clears register and interrupt */
	152	status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
	153	/* Bit 31 is always on, but there's no #define for that */
42a3b4f2	154	if (status & ~(1UL << 31)) {
1da177e4	155	l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
a4b5bd9a	156	#ifdef DUMP_L2_ECC_TAG_ON_ERROR
33b75e5c	157	l2_tag = in64(IOADDR(A_L2_ECC_TAG));
a4b5bd9a	158	#endif
1da177e4	159	memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
36a88530 RB	160	printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
	161	printk("\nLast recorded signature:\n");
	162	printk("Request %02x from %d, answered by %d with Dcode %d\n",
1da177e4 LT	163	(unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
	164	(int)(G_SCD_BERR_TID(status) >> 6),
	165	(int)G_SCD_BERR_RID(status),
	166	(int)G_SCD_BERR_DCODE(status));
a4b5bd9a	167	#ifdef DUMP_L2_ECC_TAG_ON_ERROR
36a88530	168	printk("Last L2 tag w/ bad ECC: %016llx\n", l2_tag);
a4b5bd9a	169	#endif
42a3b4f2	170	} else {
36a88530	171	printk("Bus watcher indicates no error\n");
42a3b4f2 RB	172	}
	173	}
	174	#else
	175	extern void check_bus_watcher(void);
	176	#endif
	177
1da177e4 LT	178	asmlinkage void sb1_cache_error(void)
1da177e4 LT	179	{
1da177e4	180	uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res;
41a8198f	181	unsigned long long cerr_dpa;
1da177e4	182
a4b5bd9a AI	183	#ifdef CONFIG_SIBYTE_BW_TRACE
	184	/* Freeze the trace buffer now */
	185	#if defined(CONFIG_SIBYTE_BCM1x55) \|\| defined(CONFIG_SIBYTE_BCM1x80)
33b75e5c	186	csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
a4b5bd9a	187	#else
33b75e5c	188	csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
a4b5bd9a	189	#endif
36a88530	190	printk("Trace buffer frozen\n");
a4b5bd9a AI	191	#endif
a4b5bd9a AI	192
36a88530 RB	193	printk("Cache error exception on CPU %x:\n",
36a88530 RB	194	(read_c0_prid() >> 25) & 0x7);
1da177e4 LT	195
	196	__asm__ __volatile__ (
	197	" .set push\n\t"
	198	" .set mips64\n\t"
	199	" .set noat\n\t"
	200	" mfc0 %0, $26\n\t"
	201	" mfc0 %1, $27\n\t"
	202	" mfc0 %2, $27, 1\n\t"
	203	" dmfc0 $1, $27, 3\n\t"
	204	" dsrl32 %3, $1, 0 \n\t"
	205	" sll %4, $1, 0 \n\t"
	206	" mfc0 %5, $30\n\t"
	207	" .set pop"
	208	: "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d),
	209	"=r" (dpahi), "=r" (dpalo), "=r" (eepc));
	210
	211	cerr_dpa = (((uint64_t)dpahi) << 32) \| dpalo;
36a88530 RB	212	printk(" c0_errorepc == %08x\n", eepc);
36a88530 RB	213	printk(" c0_errctl == %08x", errctl);
1da177e4 LT	214	breakout_errctl(errctl);
1da177e4 LT	215	if (errctl & CP0_ERRCTL_ICACHE) {
36a88530	216	printk(" c0_cerr_i == %08x", cerr_i);
1da177e4 LT	217	breakout_cerri(cerr_i);
	218	if (CP0_CERRI_IDX_VALID(cerr_i)) {
	219	/* Check index of EPC, allowing for delay slot */
	220	if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) &&
	221	((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4)))
36a88530	222	printk(" cerr_i idx doesn't match eepc\n");
1da177e4 LT	223	else {
	224	res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK,
	225	(cerr_i & CP0_CERRI_DATA) != 0);
	226	if (!(res & cerr_i))
36a88530	227	printk("...didn't see indicated icache problem\n");
1da177e4 LT	228	}
	229	}
	230	}
	231	if (errctl & CP0_ERRCTL_DCACHE) {
36a88530	232	printk(" c0_cerr_d == %08x", cerr_d);
1da177e4 LT	233	breakout_cerrd(cerr_d);
1da177e4 LT	234	if (CP0_CERRD_DPA_VALID(cerr_d)) {
36a88530	235	printk(" c0_cerr_dpa == %010llx\n", cerr_dpa);
1da177e4 LT	236	if (!CP0_CERRD_IDX_VALID(cerr_d)) {
	237	res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK,
	238	(cerr_d & CP0_CERRD_DATA) != 0);
	239	if (!(res & cerr_d))
36a88530	240	printk("...didn't see indicated dcache problem\n");
1da177e4 LT	241	} else {
1da177e4 LT	242	if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK))
36a88530	243	printk(" cerr_d idx doesn't match cerr_dpa\n");
1da177e4 LT	244	else {
	245	res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK,
	246	(cerr_d & CP0_CERRD_DATA) != 0);
	247	if (!(res & cerr_d))
36a88530	248	printk("...didn't see indicated problem\n");
1da177e4 LT	249	}
	250	}
	251	}
	252	}
	253
	254	check_bus_watcher();
	255
1da177e4	256	/*
a4b5bd9a AI	257	* Calling panic() when a fatal cache error occurs scrambles the
	258	* state of the system (and the cache), making it difficult to
	259	* investigate after the fact. However, if you just stall the CPU,
	260	* the other CPU may keep on running, which is typically very
	261	* undesirable.
1da177e4	262	*/
a4b5bd9a AI	263	#ifdef CONFIG_SB1_CERR_STALL
	264	while (1)
	265	;
	266	#else
	267	panic("unhandled cache error");
	268	#endif
1da177e4 LT	269	}
	270
	271
	272	/* Parity lookup table. */
	273	static const uint8_t parity[256] = {
21a151d8 RB	274	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	275	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	276	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	277	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	278	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	279	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	280	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	281	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	282	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	283	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	284	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	285	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	286	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
	287	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	288	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
	289	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0
1da177e4 LT	290	};
	291
	292	/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
	293	static const uint64_t mask_72_64[8] = {
	294	0x0738C808099264FFULL,
	295	0x38C808099264FF07ULL,
	296	0xC808099264FF0738ULL,
	297	0x08099264FF0738C8ULL,
	298	0x099264FF0738C808ULL,
	299	0x9264FF0738C80809ULL,
	300	0x64FF0738C8080992ULL,
	301	0xFF0738C808099264ULL
	302	};
	303
	304	/* Calculate the parity on a range of bits */
	305	static char range_parity(uint64_t dword, int max, int min)
	306	{
	307	char parity = 0;
	308	int i;
	309	dword >>= min;
	310	for (i=max-min; i>=0; i--) {
	311	if (dword & 0x1)
	312	parity = !parity;
	313	dword >>= 1;
	314	}
	315	return parity;
	316	}
	317
	318	/* Calculate the 4-bit even byte-parity for an instruction */
	319	static unsigned char inst_parity(uint32_t word)
	320	{
	321	int i, j;
	322	char parity = 0;
	323	for (j=0; j<4; j++) {
	324	char byte_parity = 0;
	325	for (i=0; i<8; i++) {
	326	if (word & 0x80000000)
	327	byte_parity = !byte_parity;
	328	word <<= 1;
	329	}
	330	parity <<= 1;
	331	parity \|= byte_parity;
	332	}
	333	return parity;
	334	}
	335
	336	static uint32_t extract_ic(unsigned short addr, int data)
	337	{
	338	unsigned short way;
	339	int valid;
1da177e4	340	uint32_t taghi, taglolo, taglohi;
41a8198f RB	341	unsigned long long taglo, va;
41a8198f RB	342	uint64_t tlo_tmp;
1da177e4 LT	343	uint8_t lru;
	344	int res = 0;
	345
36a88530	346	printk("Icache index 0x%04x ", addr);
1da177e4 LT	347	for (way = 0; way < 4; way++) {
	348	/* Index-load-tag-I */
	349	__asm__ __volatile__ (
	350	" .set push \n\t"
	351	" .set noreorder \n\t"
	352	" .set mips64 \n\t"
	353	" .set noat \n\t"
	354	" cache 4, 0(%3) \n\t"
	355	" mfc0 %0, $29 \n\t"
	356	" dmfc0 $1, $28 \n\t"
	357	" dsrl32 %1, $1, 0 \n\t"
	358	" sll %2, $1, 0 \n\t"
	359	" .set pop"
	360	: "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
	361	: "r" ((way << 13) \| addr));
	362
	363	taglo = ((unsigned long long)taglohi << 32) \| taglolo;
	364	if (way == 0) {
	365	lru = (taghi >> 14) & 0xff;
36a88530	366	printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
1da177e4 LT	367	((addr >> 5) & 0x3), /* bank */
	368	((addr >> 7) & 0x3f), /* index */
	369	(lru & 0x3),
	370	((lru >> 2) & 0x3),
	371	((lru >> 4) & 0x3),
	372	((lru >> 6) & 0x3));
	373	}
	374	va = (taglo & 0xC0000FFFFFFFE000ULL) \| addr;
	375	if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3))
	376	va \|= 0x3FFFF00000000000ULL;
	377	valid = ((taghi >> 29) & 1);
	378	if (valid) {
	379	tlo_tmp = taglo & 0xfff3ff;
	380	if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) {
36a88530	381	printk(" ** bad parity in VTag0/G/ASID\n");
1da177e4 LT	382	res \|= CP0_CERRI_TAG_PARITY;
	383	}
	384	if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) {
36a88530	385	printk(" ** bad parity in R/VTag1\n");
1da177e4 LT	386	res \|= CP0_CERRI_TAG_PARITY;
	387	}
	388	}
	389	if (valid ^ ((taghi >> 27) & 1)) {
36a88530	390	printk(" ** bad parity for valid bit\n");
1da177e4 LT	391	res \|= CP0_CERRI_TAG_PARITY;
1da177e4 LT	392	}
36a88530	393	printk(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n",
1da177e4 LT	394	way, va, valid, taghi, taglo);
	395
	396	if (data) {
	397	uint32_t datahi, insta, instb;
	398	uint8_t predecode;
	399	int offset;
	400
	401	/* (hit all banks and ways) */
	402	for (offset = 0; offset < 4; offset++) {
	403	/* Index-load-data-I */
	404	__asm__ __volatile__ (
	405	" .set push\n\t"
	406	" .set noreorder\n\t"
	407	" .set mips64\n\t"
	408	" .set noat\n\t"
	409	" cache 6, 0(%3) \n\t"
	410	" mfc0 %0, $29, 1\n\t"
	411	" dmfc0 $1, $28, 1\n\t"
	412	" dsrl32 %1, $1, 0 \n\t"
	413	" sll %2, $1, 0 \n\t"
	414	" .set pop \n"
	415	: "=r" (datahi), "=r" (insta), "=r" (instb)
	416	: "r" ((way << 13) \| addr \| (offset << 3)));
	417	predecode = (datahi >> 8) & 0xff;
	418	if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) {
36a88530	419	printk(" ** bad parity in predecode\n");
1da177e4 LT	420	res \|= CP0_CERRI_DATA_PARITY;
	421	}
	422	/* XXXKW should/could check predecode bits themselves */
	423	if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) {
36a88530	424	printk(" ** bad parity in instruction a\n");
1da177e4 LT	425	res \|= CP0_CERRI_DATA_PARITY;
	426	}
	427	if ((datahi & 0xf) ^ inst_parity(instb)) {
36a88530	428	printk(" ** bad parity in instruction b\n");
1da177e4 LT	429	res \|= CP0_CERRI_DATA_PARITY;
1da177e4 LT	430	}
36a88530	431	printk(" %05X-%08X%08X", datahi, insta, instb);
1da177e4	432	}
36a88530	433	printk("\n");
1da177e4 LT	434	}
	435	}
	436	return res;
	437	}
	438
	439	/* Compute the ECC for a data doubleword */
	440	static uint8_t dc_ecc(uint64_t dword)
	441	{
	442	uint64_t t;
	443	uint32_t w;
	444	uint8_t p;
	445	int i;
	446
	447	p = 0;
	448	for (i = 7; i >= 0; i--)
	449	{
	450	p <<= 1;
	451	t = dword & mask_72_64[i];
	452	w = (uint32_t)(t >> 32);
	453	p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
	454	^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
	455	w = (uint32_t)(t & 0xFFFFFFFF);
	456	p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
	457	^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
	458	}
	459	return p;
	460	}
	461
	462	struct dc_state {
	463	unsigned char val;
	464	char *name;
	465	};
	466
	467	static struct dc_state dc_states[] = {
	468	{ 0x00, "INVALID" },
	469	{ 0x0f, "COH-SHD" },
	470	{ 0x13, "NCO-E-C" },
	471	{ 0x19, "NCO-E-D" },
	472	{ 0x16, "COH-E-C" },
	473	{ 0x1c, "COH-E-D" },
	474	{ 0xff, "ERROR" }
	475	};
	476
	477	#define DC_TAG_VALID(state) \
a4b5bd9a AI	478	(((state) == 0x0) \|\| ((state) == 0xf) \|\| ((state) == 0x13) \|\| \
a4b5bd9a AI	479	((state) == 0x19) \|\| ((state) == 0x16) \|\| ((state) == 0x1c))
1da177e4 LT	480
	481	static char *dc_state_str(unsigned char state)
	482	{
	483	struct dc_state *dsc = dc_states;
	484	while (dsc->val != 0xff) {
	485	if (dsc->val == state)
	486	break;
	487	dsc++;
	488	}
	489	return dsc->name;
	490	}
	491
	492	static uint32_t extract_dc(unsigned short addr, int data)
	493	{
	494	int valid, way;
	495	unsigned char state;
1da177e4	496	uint32_t taghi, taglolo, taglohi;
41a8198f	497	unsigned long long taglo, pa;
1da177e4 LT	498	uint8_t ecc, lru;
	499	int res = 0;
	500
36a88530	501	printk("Dcache index 0x%04x ", addr);
1da177e4 LT	502	for (way = 0; way < 4; way++) {
	503	__asm__ __volatile__ (
	504	" .set push\n\t"
	505	" .set noreorder\n\t"
	506	" .set mips64\n\t"
	507	" .set noat\n\t"
	508	" cache 5, 0(%3)\n\t" /* Index-load-tag-D */
	509	" mfc0 %0, $29, 2\n\t"
	510	" dmfc0 $1, $28, 2\n\t"
	511	" dsrl32 %1, $1, 0\n\t"
	512	" sll %2, $1, 0\n\t"
	513	" .set pop"
	514	: "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
	515	: "r" ((way << 13) \| addr));
	516
	517	taglo = ((unsigned long long)taglohi << 32) \| taglolo;
	518	pa = (taglo & 0xFFFFFFE000ULL) \| addr;
	519	if (way == 0) {
	520	lru = (taghi >> 14) & 0xff;
36a88530	521	printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
1da177e4 LT	522	((addr >> 11) & 0x2) \| ((addr >> 5) & 1), /* bank */
	523	((addr >> 6) & 0x3f), /* index */
	524	(lru & 0x3),
	525	((lru >> 2) & 0x3),
	526	((lru >> 4) & 0x3),
	527	((lru >> 6) & 0x3));
	528	}
	529	state = (taghi >> 25) & 0x1f;
	530	valid = DC_TAG_VALID(state);
36a88530	531	printk(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n",
1da177e4 LT	532	way, pa, dc_state_str(state), state, taghi, taglo);
	533	if (valid) {
	534	if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) {
36a88530	535	printk(" ** bad parity in PTag1\n");
1da177e4 LT	536	res \|= CP0_CERRD_TAG_ADDRESS;
	537	}
	538	if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) {
36a88530	539	printk(" ** bad parity in PTag0\n");
1da177e4 LT	540	res \|= CP0_CERRD_TAG_ADDRESS;
	541	}
	542	} else {
	543	res \|= CP0_CERRD_TAG_STATE;
	544	}
	545
	546	if (data) {
1da177e4	547	uint32_t datalohi, datalolo, datahi;
41a8198f	548	unsigned long long datalo;
1da177e4	549	int offset;
a4b5bd9a	550	char bad_ecc = 0;
1da177e4 LT	551
	552	for (offset = 0; offset < 4; offset++) {
	553	/* Index-load-data-D */
	554	__asm__ __volatile__ (
	555	" .set push\n\t"
	556	" .set noreorder\n\t"
	557	" .set mips64\n\t"
	558	" .set noat\n\t"
	559	" cache 7, 0(%3)\n\t" /* Index-load-data-D */
	560	" mfc0 %0, $29, 3\n\t"
	561	" dmfc0 $1, $28, 3\n\t"
	562	" dsrl32 %1, $1, 0 \n\t"
	563	" sll %2, $1, 0 \n\t"
	564	" .set pop"
	565	: "=r" (datahi), "=r" (datalohi), "=r" (datalolo)
	566	: "r" ((way << 13) \| addr \| (offset << 3)));
	567	datalo = ((unsigned long long)datalohi << 32) \| datalolo;
	568	ecc = dc_ecc(datalo);
	569	if (ecc != datahi) {
13e79b46	570	int bits;
a4b5bd9a	571	bad_ecc \|= 1 << (3-offset);
1da177e4	572	ecc ^= datahi;
13e79b46	573	bits = hweight8(ecc);
1da177e4 LT	574	res \|= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
1da177e4 LT	575	}
36a88530	576	printk(" %02X-%016llX", datahi, datalo);
1da177e4	577	}
36a88530	578	printk("\n");
a4b5bd9a	579	if (bad_ecc)
36a88530 RB	580	printk(" dwords w/ bad ECC: %d %d %d %d\n",
	581	!!(bad_ecc & 8), !!(bad_ecc & 4),
	582	!!(bad_ecc & 2), !!(bad_ecc & 1));
1da177e4 LT	583	}
	584	}
	585	return res;
	586	}