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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
60b0d655 | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/smp.h> | |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | #include <linux/kallsyms.h> | |
e01402b1 | 23 | #include <linux/bootmem.h> |
d4fd1989 | 24 | #include <linux/interrupt.h> |
39b8d525 | 25 | #include <linux/ptrace.h> |
1da177e4 LT |
26 | |
27 | #include <asm/bootinfo.h> | |
28 | #include <asm/branch.h> | |
29 | #include <asm/break.h> | |
30 | #include <asm/cpu.h> | |
e50c0a8f | 31 | #include <asm/dsp.h> |
1da177e4 | 32 | #include <asm/fpu.h> |
340ee4b9 RB |
33 | #include <asm/mipsregs.h> |
34 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
35 | #include <asm/module.h> |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/ptrace.h> | |
38 | #include <asm/sections.h> | |
39 | #include <asm/system.h> | |
40 | #include <asm/tlbdebug.h> | |
41 | #include <asm/traps.h> | |
42 | #include <asm/uaccess.h> | |
43 | #include <asm/mmu_context.h> | |
1da177e4 | 44 | #include <asm/types.h> |
1df0f0ff | 45 | #include <asm/stacktrace.h> |
1da177e4 | 46 | |
e4ac58af | 47 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
48 | extern asmlinkage void handle_tlbm(void); |
49 | extern asmlinkage void handle_tlbl(void); | |
50 | extern asmlinkage void handle_tlbs(void); | |
51 | extern asmlinkage void handle_adel(void); | |
52 | extern asmlinkage void handle_ades(void); | |
53 | extern asmlinkage void handle_ibe(void); | |
54 | extern asmlinkage void handle_dbe(void); | |
55 | extern asmlinkage void handle_sys(void); | |
56 | extern asmlinkage void handle_bp(void); | |
57 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
58 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
59 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
60 | extern asmlinkage void handle_cpu(void); |
61 | extern asmlinkage void handle_ov(void); | |
62 | extern asmlinkage void handle_tr(void); | |
63 | extern asmlinkage void handle_fpe(void); | |
64 | extern asmlinkage void handle_mdmx(void); | |
65 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 66 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 67 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
68 | extern asmlinkage void handle_mcheck(void); |
69 | extern asmlinkage void handle_reserved(void); | |
70 | ||
12616ed2 | 71 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
e04582b7 | 72 | struct mips_fpu_struct *ctx, int has_fpu); |
1da177e4 | 73 | |
9267a30d | 74 | void (*board_watchpoint_handler)(struct pt_regs *regs); |
1da177e4 LT |
75 | void (*board_be_init)(void); |
76 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
77 | void (*board_nmi_handler_setup)(void); |
78 | void (*board_ejtag_handler_setup)(void); | |
79 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 | 80 | |
1da177e4 | 81 | |
4d157d5e | 82 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 83 | { |
39b8d525 | 84 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
85 | unsigned long addr; |
86 | ||
87 | printk("Call Trace:"); | |
88 | #ifdef CONFIG_KALLSYMS | |
89 | printk("\n"); | |
90 | #endif | |
39b8d525 RB |
91 | #define IS_KVA01(a) ((((unsigned int)a) & 0xc0000000) == 0x80000000) |
92 | if (IS_KVA01(sp)) { | |
93 | while (!kstack_end(sp)) { | |
94 | addr = *sp++; | |
95 | if (__kernel_text_address(addr)) | |
96 | print_ip_sym(addr); | |
97 | } | |
98 | printk("\n"); | |
e889d78f | 99 | } |
e889d78f AN |
100 | } |
101 | ||
f66686f7 | 102 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 103 | int raw_show_trace; |
f66686f7 AN |
104 | static int __init set_raw_show_trace(char *str) |
105 | { | |
106 | raw_show_trace = 1; | |
107 | return 1; | |
108 | } | |
109 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 110 | #endif |
4d157d5e | 111 | |
eae23f2c | 112 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 113 | { |
4d157d5e FBH |
114 | unsigned long sp = regs->regs[29]; |
115 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 116 | unsigned long pc = regs->cp0_epc; |
f66686f7 AN |
117 | |
118 | if (raw_show_trace || !__kernel_text_address(pc)) { | |
87151ae3 | 119 | show_raw_backtrace(sp); |
f66686f7 AN |
120 | return; |
121 | } | |
122 | printk("Call Trace:\n"); | |
4d157d5e | 123 | do { |
87151ae3 | 124 | print_ip_sym(pc); |
1924600c | 125 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 126 | } while (pc); |
f66686f7 AN |
127 | printk("\n"); |
128 | } | |
f66686f7 | 129 | |
1da177e4 LT |
130 | /* |
131 | * This routine abuses get_user()/put_user() to reference pointers | |
132 | * with at least a bit of error checking ... | |
133 | */ | |
eae23f2c RB |
134 | static void show_stacktrace(struct task_struct *task, |
135 | const struct pt_regs *regs) | |
1da177e4 LT |
136 | { |
137 | const int field = 2 * sizeof(unsigned long); | |
138 | long stackdata; | |
139 | int i; | |
5e0373b8 | 140 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
141 | |
142 | printk("Stack :"); | |
143 | i = 0; | |
144 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
145 | if (i && ((i % (64 / field)) == 0)) | |
146 | printk("\n "); | |
147 | if (i > 39) { | |
148 | printk(" ..."); | |
149 | break; | |
150 | } | |
151 | ||
152 | if (__get_user(stackdata, sp++)) { | |
153 | printk(" (Bad stack address)"); | |
154 | break; | |
155 | } | |
156 | ||
157 | printk(" %0*lx", field, stackdata); | |
158 | i++; | |
159 | } | |
160 | printk("\n"); | |
87151ae3 | 161 | show_backtrace(task, regs); |
f66686f7 AN |
162 | } |
163 | ||
f66686f7 AN |
164 | void show_stack(struct task_struct *task, unsigned long *sp) |
165 | { | |
166 | struct pt_regs regs; | |
167 | if (sp) { | |
168 | regs.regs[29] = (unsigned long)sp; | |
169 | regs.regs[31] = 0; | |
170 | regs.cp0_epc = 0; | |
171 | } else { | |
172 | if (task && task != current) { | |
173 | regs.regs[29] = task->thread.reg29; | |
174 | regs.regs[31] = 0; | |
175 | regs.cp0_epc = task->thread.reg31; | |
176 | } else { | |
177 | prepare_frametrace(®s); | |
178 | } | |
179 | } | |
180 | show_stacktrace(task, ®s); | |
1da177e4 LT |
181 | } |
182 | ||
183 | /* | |
184 | * The architecture-independent dump_stack generator | |
185 | */ | |
186 | void dump_stack(void) | |
187 | { | |
1666a6fc | 188 | struct pt_regs regs; |
1da177e4 | 189 | |
1666a6fc FBH |
190 | prepare_frametrace(®s); |
191 | show_backtrace(current, ®s); | |
1da177e4 LT |
192 | } |
193 | ||
194 | EXPORT_SYMBOL(dump_stack); | |
195 | ||
e1bb8289 | 196 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
197 | { |
198 | long i; | |
39b8d525 | 199 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
200 | |
201 | printk("\nCode:"); | |
202 | ||
39b8d525 RB |
203 | if ((unsigned long)pc & 1) |
204 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
205 | for(i = -3 ; i < 6 ; i++) { |
206 | unsigned int insn; | |
39b8d525 | 207 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
208 | printk(" (Bad address in epc)\n"); |
209 | break; | |
210 | } | |
39b8d525 | 211 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
212 | } |
213 | } | |
214 | ||
eae23f2c | 215 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
216 | { |
217 | const int field = 2 * sizeof(unsigned long); | |
218 | unsigned int cause = regs->cp0_cause; | |
219 | int i; | |
220 | ||
221 | printk("Cpu %d\n", smp_processor_id()); | |
222 | ||
223 | /* | |
224 | * Saved main processor registers | |
225 | */ | |
226 | for (i = 0; i < 32; ) { | |
227 | if ((i % 4) == 0) | |
228 | printk("$%2d :", i); | |
229 | if (i == 0) | |
230 | printk(" %0*lx", field, 0UL); | |
231 | else if (i == 26 || i == 27) | |
232 | printk(" %*s", field, ""); | |
233 | else | |
234 | printk(" %0*lx", field, regs->regs[i]); | |
235 | ||
236 | i++; | |
237 | if ((i % 4) == 0) | |
238 | printk("\n"); | |
239 | } | |
240 | ||
9693a853 FBH |
241 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
242 | printk("Acx : %0*lx\n", field, regs->acx); | |
243 | #endif | |
1da177e4 LT |
244 | printk("Hi : %0*lx\n", field, regs->hi); |
245 | printk("Lo : %0*lx\n", field, regs->lo); | |
246 | ||
247 | /* | |
248 | * Saved cp0 registers | |
249 | */ | |
250 | printk("epc : %0*lx ", field, regs->cp0_epc); | |
251 | print_symbol("%s ", regs->cp0_epc); | |
252 | printk(" %s\n", print_tainted()); | |
253 | printk("ra : %0*lx ", field, regs->regs[31]); | |
254 | print_symbol("%s\n", regs->regs[31]); | |
255 | ||
256 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
257 | ||
3b2396d9 MR |
258 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
259 | if (regs->cp0_status & ST0_KUO) | |
260 | printk("KUo "); | |
261 | if (regs->cp0_status & ST0_IEO) | |
262 | printk("IEo "); | |
263 | if (regs->cp0_status & ST0_KUP) | |
264 | printk("KUp "); | |
265 | if (regs->cp0_status & ST0_IEP) | |
266 | printk("IEp "); | |
267 | if (regs->cp0_status & ST0_KUC) | |
268 | printk("KUc "); | |
269 | if (regs->cp0_status & ST0_IEC) | |
270 | printk("IEc "); | |
271 | } else { | |
272 | if (regs->cp0_status & ST0_KX) | |
273 | printk("KX "); | |
274 | if (regs->cp0_status & ST0_SX) | |
275 | printk("SX "); | |
276 | if (regs->cp0_status & ST0_UX) | |
277 | printk("UX "); | |
278 | switch (regs->cp0_status & ST0_KSU) { | |
279 | case KSU_USER: | |
280 | printk("USER "); | |
281 | break; | |
282 | case KSU_SUPERVISOR: | |
283 | printk("SUPERVISOR "); | |
284 | break; | |
285 | case KSU_KERNEL: | |
286 | printk("KERNEL "); | |
287 | break; | |
288 | default: | |
289 | printk("BAD_MODE "); | |
290 | break; | |
291 | } | |
292 | if (regs->cp0_status & ST0_ERL) | |
293 | printk("ERL "); | |
294 | if (regs->cp0_status & ST0_EXL) | |
295 | printk("EXL "); | |
296 | if (regs->cp0_status & ST0_IE) | |
297 | printk("IE "); | |
1da177e4 | 298 | } |
1da177e4 LT |
299 | printk("\n"); |
300 | ||
301 | printk("Cause : %08x\n", cause); | |
302 | ||
303 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
304 | if (1 <= cause && cause <= 5) | |
305 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
306 | ||
9966db25 RB |
307 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
308 | cpu_name_string()); | |
1da177e4 LT |
309 | } |
310 | ||
eae23f2c RB |
311 | /* |
312 | * FIXME: really the generic show_regs should take a const pointer argument. | |
313 | */ | |
314 | void show_regs(struct pt_regs *regs) | |
315 | { | |
316 | __show_regs((struct pt_regs *)regs); | |
317 | } | |
318 | ||
319 | void show_registers(const struct pt_regs *regs) | |
1da177e4 | 320 | { |
39b8d525 RB |
321 | const int field = 2 * sizeof(unsigned long); |
322 | ||
eae23f2c | 323 | __show_regs(regs); |
1da177e4 | 324 | print_modules(); |
39b8d525 RB |
325 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
326 | current->comm, current->pid, current_thread_info(), current, | |
327 | field, current_thread_info()->tp_value); | |
328 | if (cpu_has_userlocal) { | |
329 | unsigned long tls; | |
330 | ||
331 | tls = read_c0_userlocal(); | |
332 | if (tls != current_thread_info()->tp_value) | |
333 | printk("*HwTLS: %0*lx\n", field, tls); | |
334 | } | |
335 | ||
f66686f7 | 336 | show_stacktrace(current, regs); |
e1bb8289 | 337 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
338 | printk("\n"); |
339 | } | |
340 | ||
341 | static DEFINE_SPINLOCK(die_lock); | |
342 | ||
eae23f2c | 343 | void __noreturn die(const char * str, const struct pt_regs * regs) |
1da177e4 LT |
344 | { |
345 | static int die_counter; | |
41c594ab RB |
346 | #ifdef CONFIG_MIPS_MT_SMTC |
347 | unsigned long dvpret = dvpe(); | |
348 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
349 | |
350 | console_verbose(); | |
351 | spin_lock_irq(&die_lock); | |
41c594ab RB |
352 | bust_spinlocks(1); |
353 | #ifdef CONFIG_MIPS_MT_SMTC | |
354 | mips_mt_regdump(dvpret); | |
355 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
178086c8 | 356 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 357 | show_registers(regs); |
bcdcd8e7 | 358 | add_taint(TAINT_DIE); |
1da177e4 | 359 | spin_unlock_irq(&die_lock); |
d4fd1989 MB |
360 | |
361 | if (in_interrupt()) | |
362 | panic("Fatal exception in interrupt"); | |
363 | ||
364 | if (panic_on_oops) { | |
365 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
366 | ssleep(5); | |
367 | panic("Fatal exception"); | |
368 | } | |
369 | ||
1da177e4 LT |
370 | do_exit(SIGSEGV); |
371 | } | |
372 | ||
1da177e4 LT |
373 | extern const struct exception_table_entry __start___dbe_table[]; |
374 | extern const struct exception_table_entry __stop___dbe_table[]; | |
375 | ||
b6dcec9b RB |
376 | __asm__( |
377 | " .section __dbe_table, \"a\"\n" | |
378 | " .previous \n"); | |
1da177e4 LT |
379 | |
380 | /* Given an address, look for it in the exception tables. */ | |
381 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
382 | { | |
383 | const struct exception_table_entry *e; | |
384 | ||
385 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
386 | if (!e) | |
387 | e = search_module_dbetables(addr); | |
388 | return e; | |
389 | } | |
390 | ||
391 | asmlinkage void do_be(struct pt_regs *regs) | |
392 | { | |
393 | const int field = 2 * sizeof(unsigned long); | |
394 | const struct exception_table_entry *fixup = NULL; | |
395 | int data = regs->cp0_cause & 4; | |
396 | int action = MIPS_BE_FATAL; | |
397 | ||
398 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
399 | if (data && !user_mode(regs)) | |
400 | fixup = search_dbe_tables(exception_epc(regs)); | |
401 | ||
402 | if (fixup) | |
403 | action = MIPS_BE_FIXUP; | |
404 | ||
405 | if (board_be_handler) | |
28fc582c | 406 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
407 | |
408 | switch (action) { | |
409 | case MIPS_BE_DISCARD: | |
410 | return; | |
411 | case MIPS_BE_FIXUP: | |
412 | if (fixup) { | |
413 | regs->cp0_epc = fixup->nextinsn; | |
414 | return; | |
415 | } | |
416 | break; | |
417 | default: | |
418 | break; | |
419 | } | |
420 | ||
421 | /* | |
422 | * Assume it would be too dangerous to continue ... | |
423 | */ | |
424 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
425 | data ? "Data" : "Instruction", | |
426 | field, regs->cp0_epc, field, regs->regs[31]); | |
427 | die_if_kernel("Oops", regs); | |
428 | force_sig(SIGBUS, current); | |
429 | } | |
430 | ||
1da177e4 | 431 | /* |
60b0d655 | 432 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
433 | */ |
434 | ||
435 | #define OPCODE 0xfc000000 | |
436 | #define BASE 0x03e00000 | |
437 | #define RT 0x001f0000 | |
438 | #define OFFSET 0x0000ffff | |
439 | #define LL 0xc0000000 | |
440 | #define SC 0xe0000000 | |
60b0d655 | 441 | #define SPEC0 0x00000000 |
3c37026d RB |
442 | #define SPEC3 0x7c000000 |
443 | #define RD 0x0000f800 | |
444 | #define FUNC 0x0000003f | |
60b0d655 | 445 | #define SYNC 0x0000000f |
3c37026d | 446 | #define RDHWR 0x0000003b |
1da177e4 LT |
447 | |
448 | /* | |
449 | * The ll_bit is cleared by r*_switch.S | |
450 | */ | |
451 | ||
452 | unsigned long ll_bit; | |
453 | ||
454 | static struct task_struct *ll_task = NULL; | |
455 | ||
60b0d655 | 456 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 457 | { |
fe00f943 | 458 | unsigned long value, __user *vaddr; |
1da177e4 | 459 | long offset; |
1da177e4 LT |
460 | |
461 | /* | |
462 | * analyse the ll instruction that just caused a ri exception | |
463 | * and put the referenced address to addr. | |
464 | */ | |
465 | ||
466 | /* sign extend offset */ | |
467 | offset = opcode & OFFSET; | |
468 | offset <<= 16; | |
469 | offset >>= 16; | |
470 | ||
fe00f943 RB |
471 | vaddr = (unsigned long __user *) |
472 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 | 473 | |
60b0d655 MR |
474 | if ((unsigned long)vaddr & 3) |
475 | return SIGBUS; | |
476 | if (get_user(value, vaddr)) | |
477 | return SIGSEGV; | |
1da177e4 LT |
478 | |
479 | preempt_disable(); | |
480 | ||
481 | if (ll_task == NULL || ll_task == current) { | |
482 | ll_bit = 1; | |
483 | } else { | |
484 | ll_bit = 0; | |
485 | } | |
486 | ll_task = current; | |
487 | ||
488 | preempt_enable(); | |
489 | ||
490 | regs->regs[(opcode & RT) >> 16] = value; | |
491 | ||
60b0d655 | 492 | return 0; |
1da177e4 LT |
493 | } |
494 | ||
60b0d655 | 495 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 496 | { |
fe00f943 RB |
497 | unsigned long __user *vaddr; |
498 | unsigned long reg; | |
1da177e4 | 499 | long offset; |
1da177e4 LT |
500 | |
501 | /* | |
502 | * analyse the sc instruction that just caused a ri exception | |
503 | * and put the referenced address to addr. | |
504 | */ | |
505 | ||
506 | /* sign extend offset */ | |
507 | offset = opcode & OFFSET; | |
508 | offset <<= 16; | |
509 | offset >>= 16; | |
510 | ||
fe00f943 RB |
511 | vaddr = (unsigned long __user *) |
512 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
513 | reg = (opcode & RT) >> 16; |
514 | ||
60b0d655 MR |
515 | if ((unsigned long)vaddr & 3) |
516 | return SIGBUS; | |
1da177e4 LT |
517 | |
518 | preempt_disable(); | |
519 | ||
520 | if (ll_bit == 0 || ll_task != current) { | |
521 | regs->regs[reg] = 0; | |
522 | preempt_enable(); | |
60b0d655 | 523 | return 0; |
1da177e4 LT |
524 | } |
525 | ||
526 | preempt_enable(); | |
527 | ||
60b0d655 MR |
528 | if (put_user(regs->regs[reg], vaddr)) |
529 | return SIGSEGV; | |
1da177e4 LT |
530 | |
531 | regs->regs[reg] = 1; | |
532 | ||
60b0d655 | 533 | return 0; |
1da177e4 LT |
534 | } |
535 | ||
536 | /* | |
537 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
538 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
539 | * executed on ll/sc-less processors. That's the theory. In practice a | |
540 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
541 | * instead, so we're doing the emulation thing in both exception handlers. | |
542 | */ | |
60b0d655 | 543 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 544 | { |
60b0d655 MR |
545 | if ((opcode & OPCODE) == LL) |
546 | return simulate_ll(regs, opcode); | |
547 | if ((opcode & OPCODE) == SC) | |
548 | return simulate_sc(regs, opcode); | |
1da177e4 | 549 | |
60b0d655 | 550 | return -1; /* Must be something else ... */ |
1da177e4 LT |
551 | } |
552 | ||
3c37026d RB |
553 | /* |
554 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 555 | * registers not implemented in hardware. |
3c37026d | 556 | */ |
60b0d655 | 557 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
3c37026d | 558 | { |
dc8f6029 | 559 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
560 | |
561 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
562 | int rd = (opcode & RD) >> 11; | |
563 | int rt = (opcode & RT) >> 16; | |
564 | switch (rd) { | |
1f5826bd CD |
565 | case 0: /* CPU number */ |
566 | regs->regs[rt] = smp_processor_id(); | |
567 | return 0; | |
568 | case 1: /* SYNCI length */ | |
569 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
570 | current_cpu_data.icache.linesz); | |
571 | return 0; | |
572 | case 2: /* Read count register */ | |
573 | regs->regs[rt] = read_c0_count(); | |
574 | return 0; | |
575 | case 3: /* Count register resolution */ | |
576 | switch (current_cpu_data.cputype) { | |
577 | case CPU_20KC: | |
578 | case CPU_25KF: | |
579 | regs->regs[rt] = 1; | |
580 | break; | |
3c37026d | 581 | default: |
1f5826bd CD |
582 | regs->regs[rt] = 2; |
583 | } | |
584 | return 0; | |
585 | case 29: | |
586 | regs->regs[rt] = ti->tp_value; | |
587 | return 0; | |
588 | default: | |
589 | return -1; | |
3c37026d RB |
590 | } |
591 | } | |
592 | ||
56ebd51b | 593 | /* Not ours. */ |
60b0d655 MR |
594 | return -1; |
595 | } | |
e5679882 | 596 | |
60b0d655 MR |
597 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
598 | { | |
599 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) | |
600 | return 0; | |
601 | ||
602 | return -1; /* Must be something else ... */ | |
3c37026d RB |
603 | } |
604 | ||
1da177e4 LT |
605 | asmlinkage void do_ov(struct pt_regs *regs) |
606 | { | |
607 | siginfo_t info; | |
608 | ||
36ccf1c0 RB |
609 | die_if_kernel("Integer overflow", regs); |
610 | ||
1da177e4 LT |
611 | info.si_code = FPE_INTOVF; |
612 | info.si_signo = SIGFPE; | |
613 | info.si_errno = 0; | |
fe00f943 | 614 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
615 | force_sig_info(SIGFPE, &info, current); |
616 | } | |
617 | ||
618 | /* | |
619 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
620 | */ | |
621 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
622 | { | |
948a34cf TS |
623 | siginfo_t info; |
624 | ||
57725f9e CD |
625 | die_if_kernel("FP exception in kernel code", regs); |
626 | ||
1da177e4 LT |
627 | if (fcr31 & FPU_CSR_UNI_X) { |
628 | int sig; | |
629 | ||
1da177e4 | 630 | /* |
a3dddd56 | 631 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
632 | * software emulator on-board, let's use it... |
633 | * | |
634 | * Force FPU to dump state into task/thread context. We're | |
635 | * moving a lot of data here for what is probably a single | |
636 | * instruction, but the alternative is to pre-decode the FP | |
637 | * register operands before invoking the emulator, which seems | |
638 | * a bit extreme for what should be an infrequent event. | |
639 | */ | |
cd21dfcf | 640 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 641 | lose_fpu(1); |
1da177e4 LT |
642 | |
643 | /* Run the emulator */ | |
49a89efb | 644 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); |
1da177e4 LT |
645 | |
646 | /* | |
647 | * We can't allow the emulated instruction to leave any of | |
648 | * the cause bit set in $fcr31. | |
649 | */ | |
eae89076 | 650 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
651 | |
652 | /* Restore the hardware register state */ | |
53dc8028 | 653 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
654 | |
655 | /* If something went wrong, signal */ | |
656 | if (sig) | |
657 | force_sig(sig, current); | |
658 | ||
659 | return; | |
948a34cf TS |
660 | } else if (fcr31 & FPU_CSR_INV_X) |
661 | info.si_code = FPE_FLTINV; | |
662 | else if (fcr31 & FPU_CSR_DIV_X) | |
663 | info.si_code = FPE_FLTDIV; | |
664 | else if (fcr31 & FPU_CSR_OVF_X) | |
665 | info.si_code = FPE_FLTOVF; | |
666 | else if (fcr31 & FPU_CSR_UDF_X) | |
667 | info.si_code = FPE_FLTUND; | |
668 | else if (fcr31 & FPU_CSR_INE_X) | |
669 | info.si_code = FPE_FLTRES; | |
670 | else | |
671 | info.si_code = __SI_FAULT; | |
672 | info.si_signo = SIGFPE; | |
673 | info.si_errno = 0; | |
674 | info.si_addr = (void __user *) regs->cp0_epc; | |
675 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
676 | } |
677 | ||
678 | asmlinkage void do_bp(struct pt_regs *regs) | |
679 | { | |
680 | unsigned int opcode, bcode; | |
681 | siginfo_t info; | |
682 | ||
ba755f8e | 683 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 684 | goto out_sigsegv; |
1da177e4 LT |
685 | |
686 | /* | |
687 | * There is the ancient bug in the MIPS assemblers that the break | |
688 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
689 | * Gas is bug-compatible, but not always, grrr... | |
690 | * We handle both cases with a simple heuristics. --macro | |
691 | */ | |
692 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
693 | if (bcode < (1 << 10)) | |
694 | bcode <<= 10; | |
695 | ||
696 | /* | |
697 | * (A short test says that IRIX 5.3 sends SIGTRAP for all break | |
698 | * insns, even for break codes that indicate arithmetic failures. | |
699 | * Weird ...) | |
700 | * But should we continue the brokenness??? --macro | |
701 | */ | |
702 | switch (bcode) { | |
703 | case BRK_OVERFLOW << 10: | |
704 | case BRK_DIVZERO << 10: | |
63dc68a8 | 705 | die_if_kernel("Break instruction in kernel code", regs); |
1da177e4 LT |
706 | if (bcode == (BRK_DIVZERO << 10)) |
707 | info.si_code = FPE_INTDIV; | |
708 | else | |
709 | info.si_code = FPE_INTOVF; | |
710 | info.si_signo = SIGFPE; | |
711 | info.si_errno = 0; | |
fe00f943 | 712 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
713 | force_sig_info(SIGFPE, &info, current); |
714 | break; | |
63dc68a8 RB |
715 | case BRK_BUG: |
716 | die("Kernel bug detected", regs); | |
717 | break; | |
1da177e4 | 718 | default: |
63dc68a8 | 719 | die_if_kernel("Break instruction in kernel code", regs); |
1da177e4 LT |
720 | force_sig(SIGTRAP, current); |
721 | } | |
90fccb13 | 722 | return; |
e5679882 RB |
723 | |
724 | out_sigsegv: | |
725 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
726 | } |
727 | ||
728 | asmlinkage void do_tr(struct pt_regs *regs) | |
729 | { | |
730 | unsigned int opcode, tcode = 0; | |
731 | siginfo_t info; | |
732 | ||
ba755f8e | 733 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 734 | goto out_sigsegv; |
1da177e4 LT |
735 | |
736 | /* Immediate versions don't provide a code. */ | |
737 | if (!(opcode & OPCODE)) | |
738 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
739 | ||
740 | /* | |
741 | * (A short test says that IRIX 5.3 sends SIGTRAP for all trap | |
742 | * insns, even for trap codes that indicate arithmetic failures. | |
743 | * Weird ...) | |
744 | * But should we continue the brokenness??? --macro | |
745 | */ | |
746 | switch (tcode) { | |
747 | case BRK_OVERFLOW: | |
748 | case BRK_DIVZERO: | |
63dc68a8 | 749 | die_if_kernel("Trap instruction in kernel code", regs); |
1da177e4 LT |
750 | if (tcode == BRK_DIVZERO) |
751 | info.si_code = FPE_INTDIV; | |
752 | else | |
753 | info.si_code = FPE_INTOVF; | |
754 | info.si_signo = SIGFPE; | |
755 | info.si_errno = 0; | |
fe00f943 | 756 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
757 | force_sig_info(SIGFPE, &info, current); |
758 | break; | |
63dc68a8 RB |
759 | case BRK_BUG: |
760 | die("Kernel bug detected", regs); | |
761 | break; | |
1da177e4 | 762 | default: |
63dc68a8 | 763 | die_if_kernel("Trap instruction in kernel code", regs); |
1da177e4 LT |
764 | force_sig(SIGTRAP, current); |
765 | } | |
90fccb13 | 766 | return; |
e5679882 RB |
767 | |
768 | out_sigsegv: | |
769 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
770 | } |
771 | ||
772 | asmlinkage void do_ri(struct pt_regs *regs) | |
773 | { | |
60b0d655 MR |
774 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
775 | unsigned long old_epc = regs->cp0_epc; | |
776 | unsigned int opcode = 0; | |
777 | int status = -1; | |
1da177e4 | 778 | |
60b0d655 | 779 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 780 | |
60b0d655 | 781 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
782 | return; |
783 | ||
60b0d655 MR |
784 | if (unlikely(get_user(opcode, epc) < 0)) |
785 | status = SIGSEGV; | |
786 | ||
787 | if (!cpu_has_llsc && status < 0) | |
788 | status = simulate_llsc(regs, opcode); | |
789 | ||
790 | if (status < 0) | |
791 | status = simulate_rdhwr(regs, opcode); | |
792 | ||
793 | if (status < 0) | |
794 | status = simulate_sync(regs, opcode); | |
795 | ||
796 | if (status < 0) | |
797 | status = SIGILL; | |
798 | ||
799 | if (unlikely(status > 0)) { | |
800 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
801 | force_sig(status, current); | |
802 | } | |
1da177e4 LT |
803 | } |
804 | ||
d223a861 RB |
805 | /* |
806 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
807 | * emulated more than some threshold number of instructions, force migration to | |
808 | * a "CPU" that has FP support. | |
809 | */ | |
810 | static void mt_ase_fp_affinity(void) | |
811 | { | |
812 | #ifdef CONFIG_MIPS_MT_FPAFF | |
813 | if (mt_fpemul_threshold > 0 && | |
814 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
815 | /* | |
816 | * If there's no FPU present, or if the application has already | |
817 | * restricted the allowed set to exclude any CPUs with FPUs, | |
818 | * we'll skip the procedure. | |
819 | */ | |
820 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
821 | cpumask_t tmask; | |
822 | ||
823 | cpus_and(tmask, current->thread.user_cpus_allowed, | |
824 | mt_fpu_cpumask); | |
825 | set_cpus_allowed(current, tmask); | |
293c5bd1 | 826 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
827 | } |
828 | } | |
829 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
830 | } | |
831 | ||
1da177e4 LT |
832 | asmlinkage void do_cpu(struct pt_regs *regs) |
833 | { | |
60b0d655 MR |
834 | unsigned int __user *epc; |
835 | unsigned long old_epc; | |
836 | unsigned int opcode; | |
1da177e4 | 837 | unsigned int cpid; |
60b0d655 | 838 | int status; |
1da177e4 | 839 | |
5323180d AN |
840 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
841 | ||
1da177e4 LT |
842 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
843 | ||
844 | switch (cpid) { | |
845 | case 0: | |
60b0d655 MR |
846 | epc = (unsigned int __user *)exception_epc(regs); |
847 | old_epc = regs->cp0_epc; | |
848 | opcode = 0; | |
849 | status = -1; | |
1da177e4 | 850 | |
60b0d655 | 851 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 852 | return; |
3c37026d | 853 | |
60b0d655 MR |
854 | if (unlikely(get_user(opcode, epc) < 0)) |
855 | status = SIGSEGV; | |
856 | ||
857 | if (!cpu_has_llsc && status < 0) | |
858 | status = simulate_llsc(regs, opcode); | |
859 | ||
860 | if (status < 0) | |
861 | status = simulate_rdhwr(regs, opcode); | |
862 | ||
863 | if (status < 0) | |
864 | status = SIGILL; | |
865 | ||
866 | if (unlikely(status > 0)) { | |
867 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
868 | force_sig(status, current); | |
869 | } | |
870 | ||
871 | return; | |
1da177e4 LT |
872 | |
873 | case 1: | |
53dc8028 AN |
874 | if (used_math()) /* Using the FPU again. */ |
875 | own_fpu(1); | |
876 | else { /* First time FPU user. */ | |
1da177e4 LT |
877 | init_fpu(); |
878 | set_used_math(); | |
879 | } | |
880 | ||
5323180d | 881 | if (!raw_cpu_has_fpu) { |
e04582b7 | 882 | int sig; |
e04582b7 AN |
883 | sig = fpu_emulator_cop1Handler(regs, |
884 | ¤t->thread.fpu, 0); | |
1da177e4 LT |
885 | if (sig) |
886 | force_sig(sig, current); | |
d223a861 RB |
887 | else |
888 | mt_ase_fp_affinity(); | |
1da177e4 LT |
889 | } |
890 | ||
1da177e4 LT |
891 | return; |
892 | ||
893 | case 2: | |
894 | case 3: | |
895 | break; | |
896 | } | |
897 | ||
898 | force_sig(SIGILL, current); | |
899 | } | |
900 | ||
901 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
902 | { | |
903 | force_sig(SIGILL, current); | |
904 | } | |
905 | ||
906 | asmlinkage void do_watch(struct pt_regs *regs) | |
907 | { | |
9267a30d MSJ |
908 | if (board_watchpoint_handler) { |
909 | (*board_watchpoint_handler)(regs); | |
910 | return; | |
911 | } | |
912 | ||
1da177e4 LT |
913 | /* |
914 | * We use the watch exception where available to detect stack | |
915 | * overflows. | |
916 | */ | |
917 | dump_tlb_all(); | |
918 | show_regs(regs); | |
919 | panic("Caught WATCH exception - probably caused by stack overflow."); | |
920 | } | |
921 | ||
922 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
923 | { | |
cac4bcbc RB |
924 | const int field = 2 * sizeof(unsigned long); |
925 | int multi_match = regs->cp0_status & ST0_TS; | |
926 | ||
1da177e4 | 927 | show_regs(regs); |
cac4bcbc RB |
928 | |
929 | if (multi_match) { | |
930 | printk("Index : %0x\n", read_c0_index()); | |
931 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
932 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
933 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
934 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
935 | printk("\n"); | |
936 | dump_tlb_all(); | |
937 | } | |
938 | ||
e1bb8289 | 939 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 940 | |
1da177e4 LT |
941 | /* |
942 | * Some chips may have other causes of machine check (e.g. SB1 | |
943 | * graduation timer) | |
944 | */ | |
945 | panic("Caught Machine Check exception - %scaused by multiple " | |
946 | "matching entries in the TLB.", | |
cac4bcbc | 947 | (multi_match) ? "" : "not "); |
1da177e4 LT |
948 | } |
949 | ||
340ee4b9 RB |
950 | asmlinkage void do_mt(struct pt_regs *regs) |
951 | { | |
41c594ab RB |
952 | int subcode; |
953 | ||
41c594ab RB |
954 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
955 | >> VPECONTROL_EXCPT_SHIFT; | |
956 | switch (subcode) { | |
957 | case 0: | |
e35a5e35 | 958 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
959 | break; |
960 | case 1: | |
e35a5e35 | 961 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
962 | break; |
963 | case 2: | |
e35a5e35 | 964 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
965 | break; |
966 | case 3: | |
e35a5e35 | 967 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
968 | break; |
969 | case 4: | |
e35a5e35 | 970 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
971 | break; |
972 | case 5: | |
e35a5e35 | 973 | printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); |
41c594ab RB |
974 | break; |
975 | default: | |
e35a5e35 | 976 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
977 | subcode); |
978 | break; | |
979 | } | |
340ee4b9 RB |
980 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
981 | ||
982 | force_sig(SIGILL, current); | |
983 | } | |
984 | ||
985 | ||
e50c0a8f RB |
986 | asmlinkage void do_dsp(struct pt_regs *regs) |
987 | { | |
988 | if (cpu_has_dsp) | |
989 | panic("Unexpected DSP exception\n"); | |
990 | ||
991 | force_sig(SIGILL, current); | |
992 | } | |
993 | ||
1da177e4 LT |
994 | asmlinkage void do_reserved(struct pt_regs *regs) |
995 | { | |
996 | /* | |
997 | * Game over - no way to handle this if it ever occurs. Most probably | |
998 | * caused by a new unknown cpu type or after another deadly | |
999 | * hard/software error. | |
1000 | */ | |
1001 | show_regs(regs); | |
1002 | panic("Caught reserved exception %ld - should not happen.", | |
1003 | (regs->cp0_cause & 0x7f) >> 2); | |
1004 | } | |
1005 | ||
39b8d525 RB |
1006 | static int __initdata l1parity = 1; |
1007 | static int __init nol1parity(char *s) | |
1008 | { | |
1009 | l1parity = 0; | |
1010 | return 1; | |
1011 | } | |
1012 | __setup("nol1par", nol1parity); | |
1013 | static int __initdata l2parity = 1; | |
1014 | static int __init nol2parity(char *s) | |
1015 | { | |
1016 | l2parity = 0; | |
1017 | return 1; | |
1018 | } | |
1019 | __setup("nol2par", nol2parity); | |
1020 | ||
1da177e4 LT |
1021 | /* |
1022 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1023 | * it different ways. | |
1024 | */ | |
1025 | static inline void parity_protection_init(void) | |
1026 | { | |
10cc3529 | 1027 | switch (current_cpu_type()) { |
1da177e4 | 1028 | case CPU_24K: |
98a41de9 | 1029 | case CPU_34K: |
39b8d525 RB |
1030 | case CPU_74K: |
1031 | case CPU_1004K: | |
1032 | { | |
1033 | #define ERRCTL_PE 0x80000000 | |
1034 | #define ERRCTL_L2P 0x00800000 | |
1035 | unsigned long errctl; | |
1036 | unsigned int l1parity_present, l2parity_present; | |
1037 | ||
1038 | errctl = read_c0_ecc(); | |
1039 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1040 | ||
1041 | /* probe L1 parity support */ | |
1042 | write_c0_ecc(errctl | ERRCTL_PE); | |
1043 | back_to_back_c0_hazard(); | |
1044 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1045 | ||
1046 | /* probe L2 parity support */ | |
1047 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1048 | back_to_back_c0_hazard(); | |
1049 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1050 | ||
1051 | if (l1parity_present && l2parity_present) { | |
1052 | if (l1parity) | |
1053 | errctl |= ERRCTL_PE; | |
1054 | if (l1parity ^ l2parity) | |
1055 | errctl |= ERRCTL_L2P; | |
1056 | } else if (l1parity_present) { | |
1057 | if (l1parity) | |
1058 | errctl |= ERRCTL_PE; | |
1059 | } else if (l2parity_present) { | |
1060 | if (l2parity) | |
1061 | errctl |= ERRCTL_L2P; | |
1062 | } else { | |
1063 | /* No parity available */ | |
1064 | } | |
1065 | ||
1066 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1067 | ||
1068 | write_c0_ecc(errctl); | |
1069 | back_to_back_c0_hazard(); | |
1070 | errctl = read_c0_ecc(); | |
1071 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1072 | ||
1073 | if (l1parity_present) | |
1074 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1075 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1076 | ||
1077 | if (l2parity_present) { | |
1078 | if (l1parity_present && l1parity) | |
1079 | errctl ^= ERRCTL_L2P; | |
1080 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1081 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1082 | } | |
1083 | } | |
1084 | break; | |
1085 | ||
1da177e4 | 1086 | case CPU_5KC: |
14f18b7f RB |
1087 | write_c0_ecc(0x80000000); |
1088 | back_to_back_c0_hazard(); | |
1089 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1090 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1091 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1092 | break; |
1093 | case CPU_20KC: | |
1094 | case CPU_25KF: | |
1095 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1096 | printk(KERN_INFO "Enable cache parity protection for " | |
1097 | "MIPS 20KC/25KF CPUs.\n"); | |
1098 | clear_c0_status(ST0_DE); | |
1099 | break; | |
1100 | default: | |
1101 | break; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | asmlinkage void cache_parity_error(void) | |
1106 | { | |
1107 | const int field = 2 * sizeof(unsigned long); | |
1108 | unsigned int reg_val; | |
1109 | ||
1110 | /* For the moment, report the problem and hang. */ | |
1111 | printk("Cache error exception:\n"); | |
1112 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1113 | reg_val = read_c0_cacheerr(); | |
1114 | printk("c0_cacheerr == %08x\n", reg_val); | |
1115 | ||
1116 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1117 | reg_val & (1<<30) ? "secondary" : "primary", | |
1118 | reg_val & (1<<31) ? "data" : "insn"); | |
1119 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1120 | reg_val & (1<<29) ? "ED " : "", | |
1121 | reg_val & (1<<28) ? "ET " : "", | |
1122 | reg_val & (1<<26) ? "EE " : "", | |
1123 | reg_val & (1<<25) ? "EB " : "", | |
1124 | reg_val & (1<<24) ? "EI " : "", | |
1125 | reg_val & (1<<23) ? "E1 " : "", | |
1126 | reg_val & (1<<22) ? "E0 " : ""); | |
1127 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1128 | ||
ec917c2c | 1129 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1130 | if (reg_val & (1<<22)) |
1131 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1132 | ||
1133 | if (reg_val & (1<<23)) | |
1134 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1135 | #endif | |
1136 | ||
1137 | panic("Can't handle the cache error!"); | |
1138 | } | |
1139 | ||
1140 | /* | |
1141 | * SDBBP EJTAG debug exception handler. | |
1142 | * We skip the instruction and return to the next instruction. | |
1143 | */ | |
1144 | void ejtag_exception_handler(struct pt_regs *regs) | |
1145 | { | |
1146 | const int field = 2 * sizeof(unsigned long); | |
1147 | unsigned long depc, old_epc; | |
1148 | unsigned int debug; | |
1149 | ||
70ae6126 | 1150 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1151 | depc = read_c0_depc(); |
1152 | debug = read_c0_debug(); | |
70ae6126 | 1153 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1154 | if (debug & 0x80000000) { |
1155 | /* | |
1156 | * In branch delay slot. | |
1157 | * We cheat a little bit here and use EPC to calculate the | |
1158 | * debug return address (DEPC). EPC is restored after the | |
1159 | * calculation. | |
1160 | */ | |
1161 | old_epc = regs->cp0_epc; | |
1162 | regs->cp0_epc = depc; | |
1163 | __compute_return_epc(regs); | |
1164 | depc = regs->cp0_epc; | |
1165 | regs->cp0_epc = old_epc; | |
1166 | } else | |
1167 | depc += 4; | |
1168 | write_c0_depc(depc); | |
1169 | ||
1170 | #if 0 | |
70ae6126 | 1171 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1172 | write_c0_debug(debug | 0x100); |
1173 | #endif | |
1174 | } | |
1175 | ||
1176 | /* | |
1177 | * NMI exception handler. | |
1178 | */ | |
34412c72 | 1179 | NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1180 | { |
41c594ab | 1181 | bust_spinlocks(1); |
1da177e4 LT |
1182 | printk("NMI taken!!!!\n"); |
1183 | die("NMI", regs); | |
1da177e4 LT |
1184 | } |
1185 | ||
e01402b1 RB |
1186 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1187 | ||
1188 | unsigned long ebase; | |
1da177e4 | 1189 | unsigned long exception_handlers[32]; |
e01402b1 | 1190 | unsigned long vi_handlers[64]; |
1da177e4 LT |
1191 | |
1192 | /* | |
1193 | * As a side effect of the way this is implemented we're limited | |
1194 | * to interrupt handlers in the address range from | |
1195 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
1196 | */ | |
1197 | void *set_except_vector(int n, void *addr) | |
1198 | { | |
1199 | unsigned long handler = (unsigned long) addr; | |
1200 | unsigned long old_handler = exception_handlers[n]; | |
1201 | ||
1202 | exception_handlers[n] = handler; | |
1203 | if (n == 0 && cpu_has_divec) { | |
ec70f65e RB |
1204 | *(u32 *)(ebase + 0x200) = 0x08000000 | |
1205 | (0x03ffffff & (handler >> 2)); | |
e01402b1 RB |
1206 | flush_icache_range(ebase + 0x200, ebase + 0x204); |
1207 | } | |
1208 | return (void *)old_handler; | |
1209 | } | |
1210 | ||
6ba07e59 AN |
1211 | static asmlinkage void do_default_vi(void) |
1212 | { | |
1213 | show_regs(get_irq_regs()); | |
1214 | panic("Caught unexpected vectored interrupt."); | |
1215 | } | |
1216 | ||
ef300e42 | 1217 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1218 | { |
1219 | unsigned long handler; | |
1220 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1221 | int srssets = current_cpu_data.srsets; |
e01402b1 RB |
1222 | u32 *w; |
1223 | unsigned char *b; | |
1224 | ||
1225 | if (!cpu_has_veic && !cpu_has_vint) | |
1226 | BUG(); | |
1227 | ||
1228 | if (addr == NULL) { | |
1229 | handler = (unsigned long) do_default_vi; | |
1230 | srs = 0; | |
41c594ab | 1231 | } else |
e01402b1 RB |
1232 | handler = (unsigned long) addr; |
1233 | vi_handlers[n] = (unsigned long) addr; | |
1234 | ||
1235 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1236 | ||
f6771dbb | 1237 | if (srs >= srssets) |
e01402b1 RB |
1238 | panic("Shadow register set %d not supported", srs); |
1239 | ||
1240 | if (cpu_has_veic) { | |
1241 | if (board_bind_eic_interrupt) | |
49a89efb | 1242 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1243 | } else if (cpu_has_vint) { |
e01402b1 | 1244 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1245 | if (srssets > 1) |
49a89efb | 1246 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1247 | } |
1248 | ||
1249 | if (srs == 0) { | |
1250 | /* | |
1251 | * If no shadow set is selected then use the default handler | |
1252 | * that does normal register saving and a standard interrupt exit | |
1253 | */ | |
1254 | ||
1255 | extern char except_vec_vi, except_vec_vi_lui; | |
1256 | extern char except_vec_vi_ori, except_vec_vi_end; | |
41c594ab RB |
1257 | #ifdef CONFIG_MIPS_MT_SMTC |
1258 | /* | |
1259 | * We need to provide the SMTC vectored interrupt handler | |
1260 | * not only with the address of the handler, but with the | |
1261 | * Status.IM bit to be masked before going there. | |
1262 | */ | |
1263 | extern char except_vec_vi_mori; | |
1264 | const int mori_offset = &except_vec_vi_mori - &except_vec_vi; | |
1265 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1266 | const int handler_len = &except_vec_vi_end - &except_vec_vi; |
1267 | const int lui_offset = &except_vec_vi_lui - &except_vec_vi; | |
1268 | const int ori_offset = &except_vec_vi_ori - &except_vec_vi; | |
1269 | ||
1270 | if (handler_len > VECTORSPACING) { | |
1271 | /* | |
1272 | * Sigh... panicing won't help as the console | |
1273 | * is probably not configured :( | |
1274 | */ | |
49a89efb | 1275 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1276 | } |
1277 | ||
49a89efb | 1278 | memcpy(b, &except_vec_vi, handler_len); |
41c594ab | 1279 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1280 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1281 | ||
41c594ab RB |
1282 | w = (u32 *)(b + mori_offset); |
1283 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1284 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1285 | w = (u32 *)(b + lui_offset); |
1286 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1287 | w = (u32 *)(b + ori_offset); | |
1288 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
1289 | flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); | |
1290 | } | |
1291 | else { | |
1292 | /* | |
1293 | * In other cases jump directly to the interrupt handler | |
1294 | * | |
1295 | * It is the handlers responsibility to save registers if required | |
1296 | * (eg hi/lo) and return from the exception using "eret" | |
1297 | */ | |
1298 | w = (u32 *)b; | |
1299 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1300 | *w = 0; | |
1301 | flush_icache_range((unsigned long)b, (unsigned long)(b+8)); | |
1da177e4 | 1302 | } |
e01402b1 | 1303 | |
1da177e4 LT |
1304 | return (void *)old_handler; |
1305 | } | |
1306 | ||
ef300e42 | 1307 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1308 | { |
ff3eab2a | 1309 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1310 | } |
f41ae0b2 | 1311 | |
1da177e4 LT |
1312 | /* |
1313 | * This is used by native signal handling | |
1314 | */ | |
53dc8028 AN |
1315 | asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); |
1316 | asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); | |
1da177e4 | 1317 | |
53dc8028 AN |
1318 | extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); |
1319 | extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); | |
1da177e4 | 1320 | |
53dc8028 AN |
1321 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); |
1322 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); | |
1da177e4 | 1323 | |
41c594ab | 1324 | #ifdef CONFIG_SMP |
53dc8028 | 1325 | static int smp_save_fp_context(struct sigcontext __user *sc) |
41c594ab | 1326 | { |
53dc8028 | 1327 | return raw_cpu_has_fpu |
41c594ab RB |
1328 | ? _save_fp_context(sc) |
1329 | : fpu_emulator_save_context(sc); | |
1330 | } | |
1331 | ||
53dc8028 | 1332 | static int smp_restore_fp_context(struct sigcontext __user *sc) |
41c594ab | 1333 | { |
53dc8028 | 1334 | return raw_cpu_has_fpu |
41c594ab RB |
1335 | ? _restore_fp_context(sc) |
1336 | : fpu_emulator_restore_context(sc); | |
1337 | } | |
1338 | #endif | |
1339 | ||
1da177e4 LT |
1340 | static inline void signal_init(void) |
1341 | { | |
41c594ab RB |
1342 | #ifdef CONFIG_SMP |
1343 | /* For now just do the cpu_has_fpu check when the functions are invoked */ | |
1344 | save_fp_context = smp_save_fp_context; | |
1345 | restore_fp_context = smp_restore_fp_context; | |
1346 | #else | |
1da177e4 LT |
1347 | if (cpu_has_fpu) { |
1348 | save_fp_context = _save_fp_context; | |
1349 | restore_fp_context = _restore_fp_context; | |
1350 | } else { | |
1351 | save_fp_context = fpu_emulator_save_context; | |
1352 | restore_fp_context = fpu_emulator_restore_context; | |
1353 | } | |
41c594ab | 1354 | #endif |
1da177e4 LT |
1355 | } |
1356 | ||
1357 | #ifdef CONFIG_MIPS32_COMPAT | |
1358 | ||
1359 | /* | |
1360 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
1361 | */ | |
53dc8028 AN |
1362 | asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); |
1363 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); | |
1da177e4 | 1364 | |
53dc8028 AN |
1365 | extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); |
1366 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); | |
1da177e4 | 1367 | |
53dc8028 AN |
1368 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); |
1369 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); | |
1da177e4 LT |
1370 | |
1371 | static inline void signal32_init(void) | |
1372 | { | |
1373 | if (cpu_has_fpu) { | |
1374 | save_fp_context32 = _save_fp_context32; | |
1375 | restore_fp_context32 = _restore_fp_context32; | |
1376 | } else { | |
1377 | save_fp_context32 = fpu_emulator_save_context32; | |
1378 | restore_fp_context32 = fpu_emulator_restore_context32; | |
1379 | } | |
1380 | } | |
1381 | #endif | |
1382 | ||
1383 | extern void cpu_cache_init(void); | |
1384 | extern void tlb_init(void); | |
1d40cfcd | 1385 | extern void flush_tlb_handlers(void); |
1da177e4 | 1386 | |
42f77542 RB |
1387 | /* |
1388 | * Timer interrupt | |
1389 | */ | |
1390 | int cp0_compare_irq; | |
1391 | ||
1392 | /* | |
1393 | * Performance counter IRQ or -1 if shared with timer | |
1394 | */ | |
1395 | int cp0_perfcount_irq; | |
1396 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1397 | ||
bdc94eb4 CD |
1398 | static int __cpuinitdata noulri; |
1399 | ||
1400 | static int __init ulri_disable(char *s) | |
1401 | { | |
1402 | pr_info("Disabling ulri\n"); | |
1403 | noulri = 1; | |
1404 | ||
1405 | return 1; | |
1406 | } | |
1407 | __setup("noulri", ulri_disable); | |
1408 | ||
234fcd14 | 1409 | void __cpuinit per_cpu_trap_init(void) |
1da177e4 LT |
1410 | { |
1411 | unsigned int cpu = smp_processor_id(); | |
1412 | unsigned int status_set = ST0_CU0; | |
41c594ab RB |
1413 | #ifdef CONFIG_MIPS_MT_SMTC |
1414 | int secondaryTC = 0; | |
1415 | int bootTC = (cpu == 0); | |
1416 | ||
1417 | /* | |
1418 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1419 | * Note that this hack assumes that the SMTC init code | |
1420 | * assigns TCs consecutively and in ascending order. | |
1421 | */ | |
1422 | ||
1423 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1424 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1425 | secondaryTC = 1; | |
1426 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1427 | |
1428 | /* | |
1429 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1430 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1431 | * flag that some firmware may have left set and the TS bit (for | |
1432 | * IP27). Set XX for ISA IV code to work. | |
1433 | */ | |
875d43e7 | 1434 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1435 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1436 | #endif | |
1437 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1438 | status_set |= ST0_XX; | |
bbaf238b CD |
1439 | if (cpu_has_dsp) |
1440 | status_set |= ST0_MX; | |
1441 | ||
b38c7399 | 1442 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1443 | status_set); |
1444 | ||
a3692020 RB |
1445 | if (cpu_has_mips_r2) { |
1446 | unsigned int enable = 0x0000000f; | |
1447 | ||
bdc94eb4 | 1448 | if (!noulri && cpu_has_userlocal) |
a3692020 RB |
1449 | enable |= (1 << 29); |
1450 | ||
1451 | write_c0_hwrena(enable); | |
1452 | } | |
e01402b1 | 1453 | |
41c594ab RB |
1454 | #ifdef CONFIG_MIPS_MT_SMTC |
1455 | if (!secondaryTC) { | |
1456 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1457 | ||
e01402b1 | 1458 | if (cpu_has_veic || cpu_has_vint) { |
49a89efb | 1459 | write_c0_ebase(ebase); |
e01402b1 | 1460 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1461 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1462 | } |
d03d0a57 RB |
1463 | if (cpu_has_divec) { |
1464 | if (cpu_has_mipsmt) { | |
1465 | unsigned int vpflags = dvpe(); | |
1466 | set_c0_cause(CAUSEF_IV); | |
1467 | evpe(vpflags); | |
1468 | } else | |
1469 | set_c0_cause(CAUSEF_IV); | |
1470 | } | |
3b1d4ed5 RB |
1471 | |
1472 | /* | |
1473 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1474 | * | |
1475 | * o read IntCtl.IPTI to determine the timer interrupt | |
1476 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1477 | */ | |
1478 | if (cpu_has_mips_r2) { | |
49a89efb RB |
1479 | cp0_compare_irq = (read_c0_intctl() >> 29) & 7; |
1480 | cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; | |
c3e838a2 | 1481 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1482 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1483 | } else { |
1484 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
1485 | cp0_perfcount_irq = -1; | |
3b1d4ed5 RB |
1486 | } |
1487 | ||
41c594ab RB |
1488 | #ifdef CONFIG_MIPS_MT_SMTC |
1489 | } | |
1490 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1491 | |
1492 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1493 | TLBMISS_HANDLER_SETUP(); | |
1494 | ||
1495 | atomic_inc(&init_mm.mm_count); | |
1496 | current->active_mm = &init_mm; | |
1497 | BUG_ON(current->mm); | |
1498 | enter_lazy_tlb(&init_mm, current); | |
1499 | ||
41c594ab RB |
1500 | #ifdef CONFIG_MIPS_MT_SMTC |
1501 | if (bootTC) { | |
1502 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1503 | cpu_cache_init(); | |
1504 | tlb_init(); | |
1505 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1506 | } else if (!secondaryTC) { |
1507 | /* | |
1508 | * First TC in non-boot VPE must do subset of tlb_init() | |
1509 | * for MMU countrol registers. | |
1510 | */ | |
1511 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1512 | write_c0_wired(0); | |
41c594ab RB |
1513 | } |
1514 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1515 | } |
1516 | ||
e01402b1 | 1517 | /* Install CPU exception handler */ |
49a89efb | 1518 | void __init set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 RB |
1519 | { |
1520 | memcpy((void *)(ebase + offset), addr, size); | |
1521 | flush_icache_range(ebase + offset, ebase + offset + size); | |
1522 | } | |
1523 | ||
234fcd14 | 1524 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1525 | "Trying to set NULL cache error exception handler"; |
1526 | ||
e01402b1 | 1527 | /* Install uncached CPU exception handler */ |
234fcd14 RB |
1528 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1529 | unsigned long size) | |
e01402b1 RB |
1530 | { |
1531 | #ifdef CONFIG_32BIT | |
1532 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | |
1533 | #endif | |
1534 | #ifdef CONFIG_64BIT | |
1535 | unsigned long uncached_ebase = TO_UNCAC(ebase); | |
1536 | #endif | |
1537 | ||
641e97f3 RB |
1538 | if (!addr) |
1539 | panic(panic_null_cerr); | |
1540 | ||
e01402b1 RB |
1541 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1542 | } | |
1543 | ||
5b10496b AN |
1544 | static int __initdata rdhwr_noopt; |
1545 | static int __init set_rdhwr_noopt(char *str) | |
1546 | { | |
1547 | rdhwr_noopt = 1; | |
1548 | return 1; | |
1549 | } | |
1550 | ||
1551 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1552 | ||
1da177e4 LT |
1553 | void __init trap_init(void) |
1554 | { | |
1555 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1556 | extern char except_vec4; |
1557 | unsigned long i; | |
1558 | ||
e01402b1 | 1559 | if (cpu_has_veic || cpu_has_vint) |
49a89efb | 1560 | ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); |
e01402b1 RB |
1561 | else |
1562 | ebase = CAC_BASE; | |
1563 | ||
1da177e4 LT |
1564 | per_cpu_trap_init(); |
1565 | ||
1566 | /* | |
1567 | * Copy the generic exception handlers to their final destination. | |
1568 | * This will be overriden later as suitable for a particular | |
1569 | * configuration. | |
1570 | */ | |
e01402b1 | 1571 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1572 | |
1573 | /* | |
1574 | * Setup default vectors | |
1575 | */ | |
1576 | for (i = 0; i <= 31; i++) | |
1577 | set_except_vector(i, handle_reserved); | |
1578 | ||
1579 | /* | |
1580 | * Copy the EJTAG debug exception vector handler code to it's final | |
1581 | * destination. | |
1582 | */ | |
e01402b1 | 1583 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1584 | board_ejtag_handler_setup(); |
1da177e4 LT |
1585 | |
1586 | /* | |
1587 | * Only some CPUs have the watch exceptions. | |
1588 | */ | |
1589 | if (cpu_has_watch) | |
1590 | set_except_vector(23, handle_watch); | |
1591 | ||
1592 | /* | |
e01402b1 | 1593 | * Initialise interrupt handlers |
1da177e4 | 1594 | */ |
e01402b1 RB |
1595 | if (cpu_has_veic || cpu_has_vint) { |
1596 | int nvec = cpu_has_veic ? 64 : 8; | |
1597 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1598 | set_vi_handler(i, NULL); |
e01402b1 RB |
1599 | } |
1600 | else if (cpu_has_divec) | |
1601 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1602 | |
1603 | /* | |
1604 | * Some CPUs can enable/disable for cache parity detection, but does | |
1605 | * it different ways. | |
1606 | */ | |
1607 | parity_protection_init(); | |
1608 | ||
1609 | /* | |
1610 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1611 | * by external hardware. Therefore these two exceptions | |
1612 | * may have board specific handlers. | |
1613 | */ | |
1614 | if (board_be_init) | |
1615 | board_be_init(); | |
1616 | ||
e4ac58af | 1617 | set_except_vector(0, handle_int); |
1da177e4 LT |
1618 | set_except_vector(1, handle_tlbm); |
1619 | set_except_vector(2, handle_tlbl); | |
1620 | set_except_vector(3, handle_tlbs); | |
1621 | ||
1622 | set_except_vector(4, handle_adel); | |
1623 | set_except_vector(5, handle_ades); | |
1624 | ||
1625 | set_except_vector(6, handle_ibe); | |
1626 | set_except_vector(7, handle_dbe); | |
1627 | ||
1628 | set_except_vector(8, handle_sys); | |
1629 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1630 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1631 | (cpu_has_vtag_icache ? | |
1632 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1633 | set_except_vector(11, handle_cpu); |
1634 | set_except_vector(12, handle_ov); | |
1635 | set_except_vector(13, handle_tr); | |
1da177e4 | 1636 | |
10cc3529 RB |
1637 | if (current_cpu_type() == CPU_R6000 || |
1638 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1639 | /* |
1640 | * The R6000 is the only R-series CPU that features a machine | |
1641 | * check exception (similar to the R4000 cache error) and | |
1642 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1643 | * written yet. Well, anyway there is no R6000 machine on the | |
1644 | * current list of targets for Linux/MIPS. | |
1645 | * (Duh, crap, there is someone with a triple R6k machine) | |
1646 | */ | |
1647 | //set_except_vector(14, handle_mc); | |
1648 | //set_except_vector(15, handle_ndc); | |
1649 | } | |
1650 | ||
e01402b1 RB |
1651 | |
1652 | if (board_nmi_handler_setup) | |
1653 | board_nmi_handler_setup(); | |
1654 | ||
e50c0a8f RB |
1655 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1656 | set_except_vector(15, handle_fpe); | |
1657 | ||
1658 | set_except_vector(22, handle_mdmx); | |
1659 | ||
1660 | if (cpu_has_mcheck) | |
1661 | set_except_vector(24, handle_mcheck); | |
1662 | ||
340ee4b9 RB |
1663 | if (cpu_has_mipsmt) |
1664 | set_except_vector(25, handle_mt); | |
1665 | ||
acaec427 | 1666 | set_except_vector(26, handle_dsp); |
e50c0a8f RB |
1667 | |
1668 | if (cpu_has_vce) | |
1669 | /* Special exception: R4[04]00 uses also the divec space. */ | |
1670 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); | |
1671 | else if (cpu_has_4kex) | |
1672 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1673 | else | |
1674 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); | |
1675 | ||
1da177e4 LT |
1676 | signal_init(); |
1677 | #ifdef CONFIG_MIPS32_COMPAT | |
1678 | signal32_init(); | |
1679 | #endif | |
1680 | ||
e01402b1 | 1681 | flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1682 | flush_tlb_handlers(); |
1da177e4 | 1683 | } |