[net-next-2.6.git] / arch / mips / include / asm / system.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
 * Copyright (C) 1996 by Paul M. Antoine
 * Copyright (C) 1999 Silicon Graphics
 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.
 */
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H

#include <linux/types.h>
#include <linux/irqflags.h>

#include <asm/addrspace.h>
#include <asm/barrier.h>
#include <asm/cmpxchg.h>
#include <asm/cpu-features.h>
#include <asm/dsp.h>
#include <asm/watch.h>
#include <asm/war.h>


/*
 * switch_to(n) should switch tasks to task nr n, first
 * checking that n isn't the current task, in which case it does nothing.
 */
extern asmlinkage void *resume(void *last, void *next, void *next_ti);

struct task_struct;

#ifdef CONFIG_MIPS_MT_FPAFF

/*
 * Handle the scheduler resume end of FPU affinity management.  We do this
 * inline to try to keep the overhead down. If we have been forced to run on
 * a "CPU" with an FPU because of a previous high level of FP computation,
 * but did not actually use the FPU during the most recent time-slice (CU1
 * isn't set), we undo the restriction on cpus_allowed.
 *
 * We're not calling set_cpus_allowed() here, because we have no need to
 * force prompt migration - we're already switching the current CPU to a
 * different thread.
 */

#define __mips_mt_fpaff_switch_to(prev)					\
do {									\
	struct thread_info *__prev_ti = task_thread_info(prev);		\
									\
	if (cpu_has_fpu &&						\
	    test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&		\
	    (!(KSTK_STATUS(prev) & ST0_CU1))) {				\
		clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);		\
		prev->cpus_allowed = prev->thread.user_cpus_allowed;	\
	}								\
	next->thread.emulated_fp = 0;					\
} while(0)

#else
#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
#endif

#ifdef CONFIG_CPU_HAS_LLSC
#define __clear_software_ll_bit() do { } while (0)
#else
extern unsigned long ll_bit;

#define __clear_software_ll_bit()					\
do {									\
	ll_bit = 0;							\
} while (0)
#endif

#define switch_to(prev, next, last)					\
do {									\
	__mips_mt_fpaff_switch_to(prev);				\
	if (cpu_has_dsp)						\
		__save_dsp(prev);					\
	__clear_software_ll_bit();					\
	(last) = resume(prev, next, task_thread_info(next));		\
} while (0)

#define finish_arch_switch(prev)					\
do {									\
	if (cpu_has_dsp)						\
		__restore_dsp(current);					\
	if (cpu_has_userlocal)						\
		write_c0_userlocal(current_thread_info()->tp_value);	\
	__restore_watch();						\
} while (0)

static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
	__u32 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqz	%2, 2f					\n"
		"	.subsection 2					\n"
		"2:	b	1b					\n"
		"	.previous					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		raw_local_irq_save(flags);
		retval = *m;
		*m = val;
		raw_local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_llsc_mb();

	return retval;
}

#ifdef CONFIG_64BIT
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
{
	__u64 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqz	%2, 2f					\n"
		"	.subsection 2					\n"
		"2:	b	1b					\n"
		"	.previous					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		raw_local_irq_save(flags);
		retval = *m;
		*m = val;
		raw_local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_llsc_mb();

	return retval;
}
#else
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
#endif

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid xchg().  */
extern void __xchg_called_with_bad_pointer(void);

static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
	switch (size) {
	case 4:
		return __xchg_u32(ptr, x);
	case 8:
		return __xchg_u64(ptr, x);
	}
	__xchg_called_with_bad_pointer();
	return x;
}

#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))

extern void set_handler(unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);

typedef void (*vi_handler_t)(void);
extern void *set_vi_handler(int n, vi_handler_t addr);

extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);

/*
 * See include/asm-ia64/system.h; prevents deadlock on SMP
 * systems.
 */
#define __ARCH_WANT_UNLOCKED_CTXSW

extern unsigned long arch_align_stack(unsigned long sp);

#endif /* _ASM_SYSTEM_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
0004a9df	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
1da177e4 LT	7	* Copyright (C) 1996 by Paul M. Antoine
	8	* Copyright (C) 1999 Silicon Graphics
	9	* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	*/
	12	#ifndef _ASM_SYSTEM_H
	13	#define _ASM_SYSTEM_H
	14
1da177e4	15	#include <linux/types.h>
192ef366	16	#include <linux/irqflags.h>
1da177e4 LT	17
1da177e4 LT	18	#include <asm/addrspace.h>
0004a9df	19	#include <asm/barrier.h>
fef74705	20	#include <asm/cmpxchg.h>
1da177e4	21	#include <asm/cpu-features.h>
e50c0a8f	22	#include <asm/dsp.h>
2c708cba	23	#include <asm/watch.h>
1da177e4	24	#include <asm/war.h>
1da177e4	25
1da177e4	26
1da177e4 LT	27	/*
	28	* switch_to(n) should switch tasks to task nr n, first
	29	* checking that n isn't the current task, in which case it does nothing.
	30	*/
	31	extern asmlinkage void resume(void last, void next, void next_ti);
	32
	33	struct task_struct;
	34
f088fc84 RB	35	#ifdef CONFIG_MIPS_MT_FPAFF
	36
	37	/*
	38	* Handle the scheduler resume end of FPU affinity management. We do this
	39	* inline to try to keep the overhead down. If we have been forced to run on
	40	* a "CPU" with an FPU because of a previous high level of FP computation,
	41	* but did not actually use the FPU during the most recent time-slice (CU1
	42	* isn't set), we undo the restriction on cpus_allowed.
	43	*
	44	* We're not calling set_cpus_allowed() here, because we have no need to
	45	* force prompt migration - we're already switching the current CPU to a
	46	* different thread.
	47	*/
	48
d223a861	49	#define __mips_mt_fpaff_switch_to(prev) \
f088fc84	50	do { \
293c5bd1 RB	51	struct thread_info *__prev_ti = task_thread_info(prev); \
293c5bd1 RB	52	\
f088fc84	53	if (cpu_has_fpu && \
293c5bd1 RB	54	test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
	55	(!(KSTK_STATUS(prev) & ST0_CU1))) { \
	56	clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
f088fc84 RB	57	prev->cpus_allowed = prev->thread.user_cpus_allowed; \
f088fc84 RB	58	} \
f088fc84	59	next->thread.emulated_fp = 0; \
f088fc84 RB	60	} while(0)
	61
	62	#else
35c700c0	63	#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
d223a861 RB	64	#endif
d223a861 RB	65
f4c6b6bc RB	66	#ifdef CONFIG_CPU_HAS_LLSC
	67	#define __clear_software_ll_bit() do { } while (0)
	68	#else
	69	extern unsigned long ll_bit;
	70
	71	#define __clear_software_ll_bit() \
	72	do { \
	73	ll_bit = 0; \
	74	} while (0)
	75	#endif
	76
21a151d8	77	#define switch_to(prev, next, last) \
e50c0a8f	78	do { \
d223a861	79	__mips_mt_fpaff_switch_to(prev); \
e50c0a8f RB	80	if (cpu_has_dsp) \
e50c0a8f RB	81	__save_dsp(prev); \
f4c6b6bc	82	__clear_software_ll_bit(); \
40bc9c67	83	(last) = resume(prev, next, task_thread_info(next)); \
07500b0d RB	84	} while (0)
	85
	86	#define finish_arch_switch(prev) \
	87	do { \
e50c0a8f RB	88	if (cpu_has_dsp) \
e50c0a8f RB	89	__restore_dsp(current); \
a3692020	90	if (cpu_has_userlocal) \
07500b0d	91	write_c0_userlocal(current_thread_info()->tp_value); \
2c708cba	92	__restore_watch(); \
07500b0d	93	} while (0)
1da177e4	94
1da177e4 LT	95	static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
	96	{
	97	__u32 retval;
	98
	99	if (cpu_has_llsc && R10000_LLSC_WAR) {
	100	unsigned long dummy;
	101
	102	__asm__ __volatile__(
c4559f67	103	" .set mips3 \n"
1da177e4	104	"1: ll %0, %3 # xchg_u32 \n"
7222424e	105	" .set mips0 \n"
1da177e4	106	" move %2, %z4 \n"
7222424e	107	" .set mips3 \n"
1da177e4 LT	108	" sc %2, %1 \n"
1da177e4 LT	109	" beqzl %2, 1b \n"
aac8aa77	110	" .set mips0 \n"
1da177e4 LT	111	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	112	: "R" (*m), "Jr" (val)
	113	: "memory");
	114	} else if (cpu_has_llsc) {
	115	unsigned long dummy;
	116
	117	__asm__ __volatile__(
c4559f67	118	" .set mips3 \n"
1da177e4	119	"1: ll %0, %3 # xchg_u32 \n"
7222424e	120	" .set mips0 \n"
1da177e4	121	" move %2, %z4 \n"
7222424e	122	" .set mips3 \n"
1da177e4	123	" sc %2, %1 \n"
f65e4fa8 RB	124	" beqz %2, 2f \n"
	125	" .subsection 2 \n"
	126	"2: b 1b \n"
	127	" .previous \n"
aac8aa77	128	" .set mips0 \n"
1da177e4 LT	129	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	130	: "R" (*m), "Jr" (val)
	131	: "memory");
	132	} else {
	133	unsigned long flags;
	134
49edd098	135	raw_local_irq_save(flags);
1da177e4 LT	136	retval = *m;
1da177e4 LT	137	*m = val;
49edd098	138	raw_local_irq_restore(flags); /* implies memory barrier */
1da177e4 LT	139	}
1da177e4 LT	140
17099b11	141	smp_llsc_mb();
0004a9df	142
1da177e4 LT	143	return retval;
	144	}
	145
875d43e7	146	#ifdef CONFIG_64BIT
1da177e4 LT	147	static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
	148	{
	149	__u64 retval;
	150
	151	if (cpu_has_llsc && R10000_LLSC_WAR) {
	152	unsigned long dummy;
	153
	154	__asm__ __volatile__(
aac8aa77	155	" .set mips3 \n"
1da177e4 LT	156	"1: lld %0, %3 # xchg_u64 \n"
	157	" move %2, %z4 \n"
	158	" scd %2, %1 \n"
	159	" beqzl %2, 1b \n"
aac8aa77	160	" .set mips0 \n"
1da177e4 LT	161	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	162	: "R" (*m), "Jr" (val)
	163	: "memory");
	164	} else if (cpu_has_llsc) {
	165	unsigned long dummy;
	166
	167	__asm__ __volatile__(
aac8aa77	168	" .set mips3 \n"
1da177e4 LT	169	"1: lld %0, %3 # xchg_u64 \n"
	170	" move %2, %z4 \n"
	171	" scd %2, %1 \n"
f65e4fa8 RB	172	" beqz %2, 2f \n"
	173	" .subsection 2 \n"
	174	"2: b 1b \n"
	175	" .previous \n"
aac8aa77	176	" .set mips0 \n"
1da177e4 LT	177	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	178	: "R" (*m), "Jr" (val)
	179	: "memory");
	180	} else {
	181	unsigned long flags;
	182
49edd098	183	raw_local_irq_save(flags);
1da177e4 LT	184	retval = *m;
1da177e4 LT	185	*m = val;
49edd098	186	raw_local_irq_restore(flags); /* implies memory barrier */
1da177e4 LT	187	}
1da177e4 LT	188
17099b11	189	smp_llsc_mb();
0004a9df	190
1da177e4 LT	191	return retval;
	192	}
	193	#else
	194	extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
	195	#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
	196	#endif
	197
	198	/* This function doesn't exist, so you'll get a linker error
	199	if something tries to do an invalid xchg(). */
	200	extern void __xchg_called_with_bad_pointer(void);
	201
	202	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
	203	{
	204	switch (size) {
0cea043b RB	205	case 4:
	206	return __xchg_u32(ptr, x);
	207	case 8:
	208	return __xchg_u64(ptr, x);
1da177e4 LT	209	}
	210	__xchg_called_with_bad_pointer();
	211	return x;
	212	}
	213
21a151d8	214	#define xchg(ptr, x) ((__typeof__((ptr)))__xchg((unsigned long)(x), (ptr), sizeof((ptr))))
1da177e4	215
49a89efb RB	216	extern void set_handler(unsigned long offset, void *addr, unsigned long len);
49a89efb RB	217	extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
ef300e42 RB	218
ef300e42 RB	219	typedef void (*vi_handler_t)(void);
49a89efb	220	extern void *set_vi_handler(int n, vi_handler_t addr);
ef300e42	221
1da177e4	222	extern void set_except_vector(int n, void addr);
91b05e67	223	extern unsigned long ebase;
1da177e4 LT	224	extern void per_cpu_trap_init(void);
1da177e4 LT	225
1da177e4	226	/*
4866cde0	227	* See include/asm-ia64/system.h; prevents deadlock on SMP
1da177e4 LT	228	* systems.
1da177e4 LT	229	*/
4866cde0	230	#define __ARCH_WANT_UNLOCKED_CTXSW
1da177e4	231
94109102	232	extern unsigned long arch_align_stack(unsigned long sp);
1da177e4 LT	233
1da177e4 LT	234	#endif /* _ASM_SYSTEM_H */