[net-next-2.6.git] / arch / mips / include / asm / system.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
 * Copyright (C) 1996 by Paul M. Antoine
 * Copyright (C) 1999 Silicon Graphics
 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.
 */
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H

#include <linux/types.h>
#include <linux/irqflags.h>

#include <asm/addrspace.h>
#include <asm/barrier.h>
#include <asm/cmpxchg.h>
#include <asm/cpu-features.h>
#include <asm/dsp.h>
#include <asm/watch.h>
#include <asm/war.h>


/*
 * switch_to(n) should switch tasks to task nr n, first
 * checking that n isn't the current task, in which case it does nothing.
 */
extern asmlinkage void *resume(void *last, void *next, void *next_ti);

struct task_struct;

extern unsigned int ll_bit;
extern struct task_struct *ll_task;

#ifdef CONFIG_MIPS_MT_FPAFF

/*
 * Handle the scheduler resume end of FPU affinity management.  We do this
 * inline to try to keep the overhead down. If we have been forced to run on
 * a "CPU" with an FPU because of a previous high level of FP computation,
 * but did not actually use the FPU during the most recent time-slice (CU1
 * isn't set), we undo the restriction on cpus_allowed.
 *
 * We're not calling set_cpus_allowed() here, because we have no need to
 * force prompt migration - we're already switching the current CPU to a
 * different thread.
 */

#define __mips_mt_fpaff_switch_to(prev)					\
do {									\
	struct thread_info *__prev_ti = task_thread_info(prev);		\
									\
	if (cpu_has_fpu &&						\
	    test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&		\
	    (!(KSTK_STATUS(prev) & ST0_CU1))) {				\
		clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);		\
		prev->cpus_allowed = prev->thread.user_cpus_allowed;	\
	}								\
	next->thread.emulated_fp = 0;					\
} while(0)

#else
#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
#endif

#ifdef CONFIG_CPU_HAS_LLSC
#define __clear_software_ll_bit() do { } while (0)
#else
extern unsigned long ll_bit;

#define __clear_software_ll_bit()					\
do {									\
	ll_bit = 0;							\
} while (0)
#endif

#define switch_to(prev, next, last)					\
do {									\
	__mips_mt_fpaff_switch_to(prev);				\
	if (cpu_has_dsp)						\
		__save_dsp(prev);					\
	__clear_software_ll_bit();					\
	(last) = resume(prev, next, task_thread_info(next));		\
} while (0)

#define finish_arch_switch(prev)					\
do {									\
	if (cpu_has_dsp)						\
		__restore_dsp(current);					\
	if (cpu_has_userlocal)						\
		write_c0_userlocal(current_thread_info()->tp_value);	\
	__restore_watch();						\
} while (0)

static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
	__u32 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqz	%2, 2f					\n"
		"	.subsection 2					\n"
		"2:	b	1b					\n"
		"	.previous					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		raw_local_irq_save(flags);
		retval = *m;
		*m = val;
		raw_local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_llsc_mb();

	return retval;
}

#ifdef CONFIG_64BIT
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
{
	__u64 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqz	%2, 2f					\n"
		"	.subsection 2					\n"
		"2:	b	1b					\n"
		"	.previous					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		raw_local_irq_save(flags);
		retval = *m;
		*m = val;
		raw_local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_llsc_mb();

	return retval;
}
#else
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
#endif

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid xchg().  */
extern void __xchg_called_with_bad_pointer(void);

static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
	switch (size) {
	case 4:
		return __xchg_u32(ptr, x);
	case 8:
		return __xchg_u64(ptr, x);
	}
	__xchg_called_with_bad_pointer();
	return x;
}

#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))

extern void set_handler(unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);

typedef void (*vi_handler_t)(void);
extern void *set_vi_handler(int n, vi_handler_t addr);

extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);

/*
 * See include/asm-ia64/system.h; prevents deadlock on SMP
 * systems.
 */
#define __ARCH_WANT_UNLOCKED_CTXSW

extern unsigned long arch_align_stack(unsigned long sp);

#endif /* _ASM_SYSTEM_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
0004a9df	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
1da177e4 LT	7	* Copyright (C) 1996 by Paul M. Antoine
	8	* Copyright (C) 1999 Silicon Graphics
	9	* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	*/
	12	#ifndef _ASM_SYSTEM_H
	13	#define _ASM_SYSTEM_H
	14
1da177e4	15	#include <linux/types.h>
192ef366	16	#include <linux/irqflags.h>
1da177e4 LT	17
1da177e4 LT	18	#include <asm/addrspace.h>
0004a9df	19	#include <asm/barrier.h>
fef74705	20	#include <asm/cmpxchg.h>
1da177e4	21	#include <asm/cpu-features.h>
e50c0a8f	22	#include <asm/dsp.h>
2c708cba	23	#include <asm/watch.h>
1da177e4	24	#include <asm/war.h>
1da177e4	25
1da177e4	26
1da177e4 LT	27	/*
	28	* switch_to(n) should switch tasks to task nr n, first
	29	* checking that n isn't the current task, in which case it does nothing.
	30	*/
	31	extern asmlinkage void resume(void last, void next, void next_ti);
	32
	33	struct task_struct;
	34
f1e39a4a RB	35	extern unsigned int ll_bit;
	36	extern struct task_struct *ll_task;
	37
f088fc84 RB	38	#ifdef CONFIG_MIPS_MT_FPAFF
	39
	40	/*
	41	* Handle the scheduler resume end of FPU affinity management. We do this
	42	* inline to try to keep the overhead down. If we have been forced to run on
	43	* a "CPU" with an FPU because of a previous high level of FP computation,
	44	* but did not actually use the FPU during the most recent time-slice (CU1
	45	* isn't set), we undo the restriction on cpus_allowed.
	46	*
	47	* We're not calling set_cpus_allowed() here, because we have no need to
	48	* force prompt migration - we're already switching the current CPU to a
	49	* different thread.
	50	*/
	51
d223a861	52	#define __mips_mt_fpaff_switch_to(prev) \
f088fc84	53	do { \
293c5bd1 RB	54	struct thread_info *__prev_ti = task_thread_info(prev); \
293c5bd1 RB	55	\
f088fc84	56	if (cpu_has_fpu && \
293c5bd1 RB	57	test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
	58	(!(KSTK_STATUS(prev) & ST0_CU1))) { \
	59	clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
f088fc84 RB	60	prev->cpus_allowed = prev->thread.user_cpus_allowed; \
f088fc84 RB	61	} \
f088fc84	62	next->thread.emulated_fp = 0; \
f088fc84 RB	63	} while(0)
	64
	65	#else
35c700c0	66	#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
d223a861 RB	67	#endif
d223a861 RB	68
f4c6b6bc RB	69	#ifdef CONFIG_CPU_HAS_LLSC
	70	#define __clear_software_ll_bit() do { } while (0)
	71	#else
	72	extern unsigned long ll_bit;
	73
	74	#define __clear_software_ll_bit() \
	75	do { \
	76	ll_bit = 0; \
	77	} while (0)
	78	#endif
	79
21a151d8	80	#define switch_to(prev, next, last) \
e50c0a8f	81	do { \
d223a861	82	__mips_mt_fpaff_switch_to(prev); \
e50c0a8f RB	83	if (cpu_has_dsp) \
e50c0a8f RB	84	__save_dsp(prev); \
f4c6b6bc	85	__clear_software_ll_bit(); \
40bc9c67	86	(last) = resume(prev, next, task_thread_info(next)); \
07500b0d RB	87	} while (0)
	88
	89	#define finish_arch_switch(prev) \
	90	do { \
e50c0a8f RB	91	if (cpu_has_dsp) \
e50c0a8f RB	92	__restore_dsp(current); \
a3692020	93	if (cpu_has_userlocal) \
07500b0d	94	write_c0_userlocal(current_thread_info()->tp_value); \
2c708cba	95	__restore_watch(); \
07500b0d	96	} while (0)
1da177e4	97
1da177e4 LT	98	static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
	99	{
	100	__u32 retval;
	101
	102	if (cpu_has_llsc && R10000_LLSC_WAR) {
	103	unsigned long dummy;
	104
	105	__asm__ __volatile__(
c4559f67	106	" .set mips3 \n"
1da177e4	107	"1: ll %0, %3 # xchg_u32 \n"
7222424e	108	" .set mips0 \n"
1da177e4	109	" move %2, %z4 \n"
7222424e	110	" .set mips3 \n"
1da177e4 LT	111	" sc %2, %1 \n"
1da177e4 LT	112	" beqzl %2, 1b \n"
aac8aa77	113	" .set mips0 \n"
1da177e4 LT	114	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	115	: "R" (*m), "Jr" (val)
	116	: "memory");
	117	} else if (cpu_has_llsc) {
	118	unsigned long dummy;
	119
	120	__asm__ __volatile__(
c4559f67	121	" .set mips3 \n"
1da177e4	122	"1: ll %0, %3 # xchg_u32 \n"
7222424e	123	" .set mips0 \n"
1da177e4	124	" move %2, %z4 \n"
7222424e	125	" .set mips3 \n"
1da177e4	126	" sc %2, %1 \n"
f65e4fa8 RB	127	" beqz %2, 2f \n"
	128	" .subsection 2 \n"
	129	"2: b 1b \n"
	130	" .previous \n"
aac8aa77	131	" .set mips0 \n"
1da177e4 LT	132	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	133	: "R" (*m), "Jr" (val)
	134	: "memory");
	135	} else {
	136	unsigned long flags;
	137
49edd098	138	raw_local_irq_save(flags);
1da177e4 LT	139	retval = *m;
1da177e4 LT	140	*m = val;
49edd098	141	raw_local_irq_restore(flags); /* implies memory barrier */
1da177e4 LT	142	}
1da177e4 LT	143
17099b11	144	smp_llsc_mb();
0004a9df	145
1da177e4 LT	146	return retval;
	147	}
	148
875d43e7	149	#ifdef CONFIG_64BIT
1da177e4 LT	150	static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
	151	{
	152	__u64 retval;
	153
	154	if (cpu_has_llsc && R10000_LLSC_WAR) {
	155	unsigned long dummy;
	156
	157	__asm__ __volatile__(
aac8aa77	158	" .set mips3 \n"
1da177e4 LT	159	"1: lld %0, %3 # xchg_u64 \n"
	160	" move %2, %z4 \n"
	161	" scd %2, %1 \n"
	162	" beqzl %2, 1b \n"
aac8aa77	163	" .set mips0 \n"
1da177e4 LT	164	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	165	: "R" (*m), "Jr" (val)
	166	: "memory");
	167	} else if (cpu_has_llsc) {
	168	unsigned long dummy;
	169
	170	__asm__ __volatile__(
aac8aa77	171	" .set mips3 \n"
1da177e4 LT	172	"1: lld %0, %3 # xchg_u64 \n"
	173	" move %2, %z4 \n"
	174	" scd %2, %1 \n"
f65e4fa8 RB	175	" beqz %2, 2f \n"
	176	" .subsection 2 \n"
	177	"2: b 1b \n"
	178	" .previous \n"
aac8aa77	179	" .set mips0 \n"
1da177e4 LT	180	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	181	: "R" (*m), "Jr" (val)
	182	: "memory");
	183	} else {
	184	unsigned long flags;
	185
49edd098	186	raw_local_irq_save(flags);
1da177e4 LT	187	retval = *m;
1da177e4 LT	188	*m = val;
49edd098	189	raw_local_irq_restore(flags); /* implies memory barrier */
1da177e4 LT	190	}
1da177e4 LT	191
17099b11	192	smp_llsc_mb();
0004a9df	193
1da177e4 LT	194	return retval;
	195	}
	196	#else
	197	extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
	198	#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
	199	#endif
	200
	201	/* This function doesn't exist, so you'll get a linker error
	202	if something tries to do an invalid xchg(). */
	203	extern void __xchg_called_with_bad_pointer(void);
	204
	205	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
	206	{
	207	switch (size) {
0cea043b RB	208	case 4:
	209	return __xchg_u32(ptr, x);
	210	case 8:
	211	return __xchg_u64(ptr, x);
1da177e4 LT	212	}
	213	__xchg_called_with_bad_pointer();
	214	return x;
	215	}
	216
21a151d8	217	#define xchg(ptr, x) ((__typeof__((ptr)))__xchg((unsigned long)(x), (ptr), sizeof((ptr))))
1da177e4	218
49a89efb RB	219	extern void set_handler(unsigned long offset, void *addr, unsigned long len);
49a89efb RB	220	extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
ef300e42 RB	221
ef300e42 RB	222	typedef void (*vi_handler_t)(void);
49a89efb	223	extern void *set_vi_handler(int n, vi_handler_t addr);
ef300e42	224
1da177e4	225	extern void set_except_vector(int n, void addr);
91b05e67	226	extern unsigned long ebase;
1da177e4 LT	227	extern void per_cpu_trap_init(void);
1da177e4 LT	228
1da177e4	229	/*
4866cde0	230	* See include/asm-ia64/system.h; prevents deadlock on SMP
1da177e4 LT	231	* systems.
1da177e4 LT	232	*/
4866cde0	233	#define __ARCH_WANT_UNLOCKED_CTXSW
1da177e4	234
94109102	235	extern unsigned long arch_align_stack(unsigned long sp);
1da177e4 LT	236
1da177e4 LT	237	#endif /* _ASM_SYSTEM_H */