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5b3b1688 DD |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2004-2008 Cavium Networks | |
7 | */ | |
8 | #ifndef __ASM_OCTEON_OCTEON_H | |
9 | #define __ASM_OCTEON_OCTEON_H | |
10 | ||
11 | #include "cvmx.h" | |
12 | ||
13 | extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, | |
14 | uint64_t alignment, | |
15 | uint64_t min_addr, | |
16 | uint64_t max_addr, | |
17 | int do_locking); | |
18 | extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment, | |
19 | int do_locking); | |
20 | extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment, | |
21 | uint64_t min_addr, uint64_t max_addr, | |
22 | int do_locking); | |
23 | extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment, | |
24 | char *name); | |
25 | extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, | |
26 | uint64_t max_addr, uint64_t align, | |
27 | char *name); | |
28 | extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address, | |
29 | char *name); | |
30 | extern int octeon_bootmem_free_named(char *name); | |
31 | extern void octeon_bootmem_lock(void); | |
32 | extern void octeon_bootmem_unlock(void); | |
33 | ||
34 | extern int octeon_is_simulation(void); | |
35 | extern int octeon_is_pci_host(void); | |
36 | extern int octeon_usb_is_ref_clk(void); | |
37 | extern uint64_t octeon_get_clock_rate(void); | |
38 | extern const char *octeon_board_type_string(void); | |
39 | extern const char *octeon_get_pci_interrupts(void); | |
40 | extern int octeon_get_southbridge_interrupt(void); | |
41 | extern int octeon_get_boot_coremask(void); | |
42 | extern int octeon_get_boot_num_arguments(void); | |
43 | extern const char *octeon_get_boot_argument(int arg); | |
44 | extern void octeon_hal_setup_reserved32(void); | |
45 | extern void octeon_user_io_init(void); | |
46 | struct octeon_cop2_state; | |
47 | extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); | |
48 | extern void octeon_crypto_disable(struct octeon_cop2_state *state, | |
49 | unsigned long flags); | |
69f3a7de | 50 | extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); |
5b3b1688 DD |
51 | |
52 | extern void octeon_init_cvmcount(void); | |
ca148125 | 53 | extern void octeon_setup_delays(void); |
5b3b1688 DD |
54 | |
55 | #define OCTEON_ARGV_MAX_ARGS 64 | |
56 | #define OCTOEN_SERIAL_LEN 20 | |
57 | ||
58 | struct octeon_boot_descriptor { | |
59 | /* Start of block referenced by assembly code - do not change! */ | |
60 | uint32_t desc_version; | |
61 | uint32_t desc_size; | |
62 | uint64_t stack_top; | |
63 | uint64_t heap_base; | |
64 | uint64_t heap_end; | |
65 | /* Only used by bootloader */ | |
66 | uint64_t entry_point; | |
67 | uint64_t desc_vaddr; | |
68 | /* End of This block referenced by assembly code - do not change! */ | |
69 | uint32_t exception_base_addr; | |
70 | uint32_t stack_size; | |
71 | uint32_t heap_size; | |
72 | /* Argc count for application. */ | |
73 | uint32_t argc; | |
74 | uint32_t argv[OCTEON_ARGV_MAX_ARGS]; | |
75 | ||
76 | #define BOOT_FLAG_INIT_CORE (1 << 0) | |
77 | #define OCTEON_BL_FLAG_DEBUG (1 << 1) | |
78 | #define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) | |
79 | /* If set, use uart1 for console */ | |
80 | #define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) | |
81 | /* If set, use PCI console */ | |
82 | #define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) | |
83 | /* Call exit on break on serial port */ | |
84 | #define OCTEON_BL_FLAG_BREAK (1 << 5) | |
85 | ||
86 | uint32_t flags; | |
87 | uint32_t core_mask; | |
88 | /* DRAM size in megabyes. */ | |
89 | uint32_t dram_size; | |
90 | /* physical address of free memory descriptor block. */ | |
91 | uint32_t phy_mem_desc_addr; | |
92 | /* used to pass flags from app to debugger. */ | |
93 | uint32_t debugger_flags_base_addr; | |
94 | /* CPU clock speed, in hz. */ | |
95 | uint32_t eclock_hz; | |
96 | /* DRAM clock speed, in hz. */ | |
97 | uint32_t dclock_hz; | |
98 | /* SPI4 clock in hz. */ | |
99 | uint32_t spi_clock_hz; | |
100 | uint16_t board_type; | |
101 | uint8_t board_rev_major; | |
102 | uint8_t board_rev_minor; | |
103 | uint16_t chip_type; | |
104 | uint8_t chip_rev_major; | |
105 | uint8_t chip_rev_minor; | |
106 | char board_serial_number[OCTOEN_SERIAL_LEN]; | |
107 | uint8_t mac_addr_base[6]; | |
108 | uint8_t mac_addr_count; | |
109 | uint64_t cvmx_desc_vaddr; | |
110 | }; | |
111 | ||
112 | union octeon_cvmemctl { | |
113 | uint64_t u64; | |
114 | struct { | |
115 | /* RO 1 = BIST fail, 0 = BIST pass */ | |
116 | uint64_t tlbbist:1; | |
117 | /* RO 1 = BIST fail, 0 = BIST pass */ | |
118 | uint64_t l1cbist:1; | |
119 | /* RO 1 = BIST fail, 0 = BIST pass */ | |
120 | uint64_t l1dbist:1; | |
121 | /* RO 1 = BIST fail, 0 = BIST pass */ | |
122 | uint64_t dcmbist:1; | |
123 | /* RO 1 = BIST fail, 0 = BIST pass */ | |
124 | uint64_t ptgbist:1; | |
125 | /* RO 1 = BIST fail, 0 = BIST pass */ | |
126 | uint64_t wbfbist:1; | |
127 | /* Reserved */ | |
128 | uint64_t reserved:22; | |
129 | /* R/W If set, marked write-buffer entries time out | |
130 | * the same as as other entries; if clear, marked | |
131 | * write-buffer entries use the maximum timeout. */ | |
132 | uint64_t dismarkwblongto:1; | |
133 | /* R/W If set, a merged store does not clear the | |
134 | * write-buffer entry timeout state. */ | |
135 | uint64_t dismrgclrwbto:1; | |
136 | /* R/W Two bits that are the MSBs of the resultant | |
137 | * CVMSEG LM word location for an IOBDMA. The other 8 | |
138 | * bits come from the SCRADDR field of the IOBDMA. */ | |
139 | uint64_t iobdmascrmsb:2; | |
140 | /* R/W If set, SYNCWS and SYNCS only order marked | |
141 | * stores; if clear, SYNCWS and SYNCS only order | |
142 | * unmarked stores. SYNCWSMARKED has no effect when | |
143 | * DISSYNCWS is set. */ | |
144 | uint64_t syncwsmarked:1; | |
145 | /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as | |
146 | * SYNC. */ | |
147 | uint64_t dissyncws:1; | |
148 | /* R/W If set, no stall happens on write buffer | |
149 | * full. */ | |
150 | uint64_t diswbfst:1; | |
151 | /* R/W If set (and SX set), supervisor-level | |
152 | * loads/stores can use XKPHYS addresses with | |
153 | * VA<48>==0 */ | |
154 | uint64_t xkmemenas:1; | |
155 | /* R/W If set (and UX set), user-level loads/stores | |
156 | * can use XKPHYS addresses with VA<48>==0 */ | |
157 | uint64_t xkmemenau:1; | |
158 | /* R/W If set (and SX set), supervisor-level | |
159 | * loads/stores can use XKPHYS addresses with | |
160 | * VA<48>==1 */ | |
161 | uint64_t xkioenas:1; | |
162 | /* R/W If set (and UX set), user-level loads/stores | |
163 | * can use XKPHYS addresses with VA<48>==1 */ | |
164 | uint64_t xkioenau:1; | |
165 | /* R/W If set, all stores act as SYNCW (NOMERGE must | |
166 | * be set when this is set) RW, reset to 0. */ | |
167 | uint64_t allsyncw:1; | |
168 | /* R/W If set, no stores merge, and all stores reach | |
169 | * the coherent bus in order. */ | |
170 | uint64_t nomerge:1; | |
171 | /* R/W Selects the bit in the counter used for DID | |
172 | * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = | |
173 | * 214. Actual time-out is between 1x and 2x this | |
174 | * interval. For example, with DIDTTO=3, expiration | |
175 | * interval is between 16K and 32K. */ | |
176 | uint64_t didtto:2; | |
177 | /* R/W If set, the (mem) CSR clock never turns off. */ | |
178 | uint64_t csrckalwys:1; | |
179 | /* R/W If set, mclk never turns off. */ | |
180 | uint64_t mclkalwys:1; | |
181 | /* R/W Selects the bit in the counter used for write | |
182 | * buffer flush time-outs (WBFLT+11) is the bit | |
183 | * position in an internal counter used to determine | |
184 | * expiration. The write buffer expires between 1x and | |
185 | * 2x this interval. For example, with WBFLT = 0, a | |
186 | * write buffer expires between 2K and 4K cycles after | |
187 | * the write buffer entry is allocated. */ | |
188 | uint64_t wbfltime:3; | |
189 | /* R/W If set, do not put Istream in the L2 cache. */ | |
190 | uint64_t istrnol2:1; | |
191 | /* R/W The write buffer threshold. */ | |
192 | uint64_t wbthresh:4; | |
193 | /* Reserved */ | |
194 | uint64_t reserved2:2; | |
195 | /* R/W If set, CVMSEG is available for loads/stores in | |
196 | * kernel/debug mode. */ | |
197 | uint64_t cvmsegenak:1; | |
198 | /* R/W If set, CVMSEG is available for loads/stores in | |
199 | * supervisor mode. */ | |
200 | uint64_t cvmsegenas:1; | |
201 | /* R/W If set, CVMSEG is available for loads/stores in | |
202 | * user mode. */ | |
203 | uint64_t cvmsegenau:1; | |
204 | /* R/W Size of local memory in cache blocks, 54 (6912 | |
205 | * bytes) is max legal value. */ | |
206 | uint64_t lmemsz:6; | |
207 | } s; | |
208 | }; | |
209 | ||
210 | struct octeon_cf_data { | |
211 | unsigned long base_region_bias; | |
212 | unsigned int base_region; /* The chip select region used by CF */ | |
213 | int is16bit; /* 0 - 8bit, !0 - 16bit */ | |
214 | int dma_engine; /* -1 for no DMA */ | |
215 | }; | |
216 | ||
f41c3c1b DD |
217 | struct octeon_i2c_data { |
218 | unsigned int sys_freq; | |
219 | unsigned int i2c_freq; | |
220 | }; | |
221 | ||
5b3b1688 DD |
222 | extern void octeon_write_lcd(const char *s); |
223 | extern void octeon_check_cpu_bist(void); | |
224 | extern int octeon_get_boot_debug_flag(void); | |
225 | extern int octeon_get_boot_uart(void); | |
226 | ||
227 | struct uart_port; | |
228 | extern unsigned int octeon_serial_in(struct uart_port *, int); | |
229 | extern void octeon_serial_out(struct uart_port *, int, int); | |
230 | ||
231 | /** | |
232 | * Write a 32bit value to the Octeon NPI register space | |
233 | * | |
234 | * @address: Address to write to | |
235 | * @val: Value to write | |
236 | */ | |
237 | static inline void octeon_npi_write32(uint64_t address, uint32_t val) | |
238 | { | |
239 | cvmx_write64_uint32(address ^ 4, val); | |
240 | cvmx_read64_uint32(address ^ 4); | |
241 | } | |
242 | ||
243 | ||
244 | /** | |
245 | * Read a 32bit value from the Octeon NPI register space | |
246 | * | |
247 | * @address: Address to read | |
248 | * Returns The result | |
249 | */ | |
250 | static inline uint32_t octeon_npi_read32(uint64_t address) | |
251 | { | |
252 | return cvmx_read64_uint32(address ^ 4); | |
253 | } | |
254 | ||
e8635b48 DD |
255 | extern struct cvmx_bootinfo *octeon_bootinfo; |
256 | ||
babba4f1 DD |
257 | extern uint64_t octeon_bootloader_entry_addr; |
258 | ||
5b3b1688 | 259 | #endif /* __ASM_OCTEON_OCTEON_H */ |