[net-next-2.6.git] / arch / microblaze / kernel / head.S

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * MMU code derived from arch/ppc/kernel/head_4xx.S:
 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
 *      Initial PowerPC version.
 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
 *      Rewritten for PReP
 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
 *      Low-level exception handers, MMU support, and rewrite.
 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
 *      PowerPC 8xx modifications.
 *    Copyright (c) 1998-1999 TiVo, Inc.
 *      PowerPC 403GCX modifications.
 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
 *      PowerPC 403GCX/405GP modifications.
 *    Copyright 2000 MontaVista Software Inc.
 *	PPC405 modifications
 *      PowerPC 403GCX/405GP modifications.
 * 	Author: MontaVista Software, Inc.
 *         	frank_rowand@mvista.com or source@mvista.com
 * 	   	debbie_chu@mvista.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/page.h>
#include <linux/of_fdt.h>		/* for OF_DT_HEADER */

#ifdef CONFIG_MMU
#include <asm/setup.h> /* COMMAND_LINE_SIZE */
#include <asm/mmu.h>
#include <asm/processor.h>

.data
.global empty_zero_page
.align 12
empty_zero_page:
	.space	4096
.global swapper_pg_dir
swapper_pg_dir:
	.space	4096

#endif /* CONFIG_MMU */

	.text
ENTRY(_start)
#if CONFIG_KERNEL_BASE_ADDR == 0
	brai	TOPHYS(real_start)
	.org	0x100
real_start:
#endif

	mfs	r1, rmsr
	andi	r1, r1, ~2
	mts	rmsr, r1
/*
 * Here is checking mechanism which check if Microblaze has msr instructions
 * We load msr and compare it with previous r1 value - if is the same,
 * msr instructions works if not - cpu don't have them.
 */
	/* r8=0 - I have msr instr, 1 - I don't have them */
	rsubi	r0, r0, 1	/* set the carry bit */
	msrclr	r0, 0x4		/* try to clear it */
	/* read the carry bit, r8 will be '0' if msrclr exists */
	addik	r8, r0, 0

/* r7 may point to an FDT, or there may be one linked in.
   if it's in r7, we've got to save it away ASAP.
   We ensure r7 points to a valid FDT, just in case the bootloader
   is broken or non-existent */
	beqi	r7, no_fdt_arg			/* NULL pointer?  don't copy */
	lw	r11, r0, r7			/* Does r7 point to a */
	rsubi	r11, r11, OF_DT_HEADER		/* valid FDT? */
	beqi	r11, _prepare_copy_fdt
	or	r7, r0, r0		/* clear R7 when not valid DTB */
	bnei	r11, no_fdt_arg			/* No - get out of here */
_prepare_copy_fdt:
	or	r11, r0, r0 /* incremment */
	ori	r4, r0, TOPHYS(_fdt_start)
	ori	r3, r0, (0x4000 - 4)
_copy_fdt:
	lw	r12, r7, r11 /* r12 = r7 + r11 */
	sw	r12, r4, r11 /* addr[r4 + r11] = r12 */
	addik	r11, r11, 4 /* increment counting */
	bgtid	r3, _copy_fdt /* loop for all entries */
	addik	r3, r3, -4 /* descrement loop */
no_fdt_arg:

#ifdef CONFIG_MMU

#ifndef CONFIG_CMDLINE_BOOL
/*
 * handling command line
 * copy command line to __init_end. There is space for storing command line.
 */
	or	r6, r0, r0		/* incremment */
	ori	r4, r0, __init_end	/* load address of command line */
	tophys(r4,r4)			/* convert to phys address */
	ori	r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
_copy_command_line:
	lbu	r2, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */
	sb	r2, r4, r6		/* addr[r4+r6]= r7*/
	addik	r6, r6, 1		/* increment counting */
	bgtid	r3, _copy_command_line	/* loop for all entries       */
	addik	r3, r3, -1		/* descrement loop */
	addik	r5, r4, 0		/* add new space for command line */
	tovirt(r5,r5)
#endif /* CONFIG_CMDLINE_BOOL */

#ifdef NOT_COMPILE
/* save bram context */
	or	r6, r0, r0				/* incremment */
	ori	r4, r0, TOPHYS(_bram_load_start)	/* save bram context */
	ori	r3, r0, (LMB_SIZE - 4)
_copy_bram:
	lw	r7, r0, r6		/* r7 = r0 + r6 */
	sw	r7, r4, r6		/* addr[r4 + r6] = r7*/
	addik	r6, r6, 4		/* increment counting */
	bgtid	r3, _copy_bram		/* loop for all entries */
	addik	r3, r3, -4		/* descrement loop */
#endif
	/* We have to turn on the MMU right away. */

	/*
	 * Set up the initial MMU state so we can do the first level of
	 * kernel initialization.  This maps the first 16 MBytes of memory 1:1
	 * virtual to physical.
	 */
	nop
	addik	r3, r0, MICROBLAZE_TLB_SIZE -1	/* Invalidate all TLB entries */
_invalidate:
	mts	rtlbx, r3
	mts	rtlbhi, r0			/* flush: ensure V is clear   */
	bgtid	r3, _invalidate		/* loop for all entries       */
	addik	r3, r3, -1
	/* sync */

	/* Setup the kernel PID */
	mts	rpid,r0			/* Load the kernel PID */
	nop
	bri	4

	/*
	 * We should still be executing code at physical address area
	 * RAM_BASEADDR at this point. However, kernel code is at
	 * a virtual address. So, set up a TLB mapping to cover this once
	 * translation is enabled.
	 */

	addik	r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
	tophys(r4,r3)			/* Load the kernel physical address */

	/*
	 * Configure and load two entries into TLB slots 0 and 1.
	 * In case we are pinning TLBs, these are reserved in by the
	 * other TLB functions.  If not reserving, then it doesn't
	 * matter where they are loaded.
	 */
	andi	r4,r4,0xfffffc00	/* Mask off the real page number */
	ori	r4,r4,(TLB_WR | TLB_EX)	/* Set the write and execute bits */

	andi	r3,r3,0xfffffc00	/* Mask off the effective page number */
	ori	r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))

	mts     rtlbx,r0		/* TLB slow 0 */

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	addik	r4, r4, 0x01000000	/* Map next 16 M entries */
	addik	r3, r3, 0x01000000

	ori	r6,r0,1			/* TLB slot 1 */
	mts     rtlbx,r6

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	/*
	 * Load a TLB entry for LMB, since we need access to
	 * the exception vectors, using a 4k real==virtual mapping.
	 */
	ori	r6,r0,3			/* TLB slot 3 */
	mts     rtlbx,r6

	ori	r4,r0,(TLB_WR | TLB_EX)
	ori	r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	/*
	 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the
	 * caches ready to work.
	 */
turn_on_mmu:
	ori	r15,r0,start_here
	ori	r4,r0,MSR_KERNEL_VMS
	mts	rmsr,r4
	nop
	rted	r15,0			/* enables MMU */
	nop

start_here:
#endif /* CONFIG_MMU */

	/* Initialize small data anchors */
	la	r13, r0, _KERNEL_SDA_BASE_
	la	r2, r0, _KERNEL_SDA2_BASE_

	/* Initialize stack pointer */
	la	r1, r0, init_thread_union + THREAD_SIZE - 4

	/* Initialize r31 with current task address */
	la	r31, r0, init_task

	/*
	 * Call platform dependent initialize function.
	 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
	 * the function.
	 */
	la	r9, r0, machine_early_init
	brald	r15, r9
	nop

#ifndef CONFIG_MMU
	la	r15, r0, machine_halt
	braid	start_kernel
	nop
#else
	/*
	 * Initialize the MMU.
	 */
	bralid	r15, mmu_init
	nop

	/* Go back to running unmapped so we can load up new values
	 * and change to using our exception vectors.
	 * On the MicroBlaze, all we invalidate the used TLB entries to clear
	 * the old 16M byte TLB mappings.
	 */
	ori	r15,r0,TOPHYS(kernel_load_context)
	ori	r4,r0,MSR_KERNEL
	mts	rmsr,r4
	nop
	bri	4
	rted	r15,0
	nop

	/* Load up the kernel context */
kernel_load_context:
	# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
	ori	r5,r0,3
	mts     rtlbx,r5
	nop
	mts	rtlbhi,r0
	nop
	addi	r15, r0, machine_halt
	ori	r17, r0, start_kernel
	ori	r4, r0, MSR_KERNEL_VMS
	mts	rmsr, r4
	nop
	rted	r17, 0		/* enable MMU and jump to start_kernel */
	nop
#endif /* CONFIG_MMU */
Commit	Line	Data
6d5af1a3 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
5846cc60 MS	6	* MMU code derived from arch/ppc/kernel/head_4xx.S:
	7	* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
	8	* Initial PowerPC version.
	9	* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
	10	* Rewritten for PReP
	11	* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
	12	* Low-level exception handers, MMU support, and rewrite.
	13	* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
	14	* PowerPC 8xx modifications.
	15	* Copyright (c) 1998-1999 TiVo, Inc.
	16	* PowerPC 403GCX modifications.
	17	* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
	18	* PowerPC 403GCX/405GP modifications.
	19	* Copyright 2000 MontaVista Software Inc.
	20	* PPC405 modifications
	21	* PowerPC 403GCX/405GP modifications.
	22	* Author: MontaVista Software, Inc.
	23	* frank_rowand@mvista.com or source@mvista.com
	24	* debbie_chu@mvista.com
	25	*
6d5af1a3 MS	26	* This file is subject to the terms and conditions of the GNU General Public
	27	* License. See the file "COPYING" in the main directory of this archive
	28	* for more details.
	29	*/
	30
	31	#include <linux/linkage.h>
	32	#include <asm/thread_info.h>
	33	#include <asm/page.h>
d8678b58	34	#include <linux/of_fdt.h> /* for OF_DT_HEADER */
6d5af1a3	35
5846cc60 MS	36	#ifdef CONFIG_MMU
	37	#include <asm/setup.h> /* COMMAND_LINE_SIZE */
	38	#include <asm/mmu.h>
	39	#include <asm/processor.h>
	40
	41	.data
	42	.global empty_zero_page
	43	.align 12
	44	empty_zero_page:
	45	.space 4096
	46	.global swapper_pg_dir
	47	swapper_pg_dir:
	48	.space 4096
	49
	50	#endif /* CONFIG_MMU */
	51
6d5af1a3 MS	52	.text
6d5af1a3 MS	53	ENTRY(_start)
ee68f174 MS	54	#if CONFIG_KERNEL_BASE_ADDR == 0
	55	brai TOPHYS(real_start)
	56	.org 0x100
	57	real_start:
	58	#endif
	59
6d5af1a3 MS	60	mfs r1, rmsr
	61	andi r1, r1, ~2
	62	mts rmsr, r1
2622434e MS	63	/*
	64	* Here is checking mechanism which check if Microblaze has msr instructions
	65	* We load msr and compare it with previous r1 value - if is the same,
	66	* msr instructions works if not - cpu don't have them.
	67	*/
9002062f MS	68	/* r8=0 - I have msr instr, 1 - I don't have them */
	69	rsubi r0, r0, 1 /* set the carry bit */
	70	msrclr r0, 0x4 /* try to clear it */
	71	/* read the carry bit, r8 will be '0' if msrclr exists */
	72	addik r8, r0, 0
2622434e	73
909964ec JW	74	/* r7 may point to an FDT, or there may be one linked in.
	75	if it's in r7, we've got to save it away ASAP.
	76	We ensure r7 points to a valid FDT, just in case the bootloader
	77	is broken or non-existent */
	78	beqi r7, no_fdt_arg /* NULL pointer? don't copy */
	79	lw r11, r0, r7 /* Does r7 point to a */
	80	rsubi r11, r11, OF_DT_HEADER /* valid FDT? */
ea3fd146 MS	81	beqi r11, _prepare_copy_fdt
ea3fd146 MS	82	or r7, r0, r0 /* clear R7 when not valid DTB */
909964ec	83	bnei r11, no_fdt_arg /* No - get out of here */
ea3fd146	84	_prepare_copy_fdt:
6d5af1a3	85	or r11, r0, r0 /* incremment */
909964ec	86	ori r4, r0, TOPHYS(_fdt_start)
6d5af1a3 MS	87	ori r3, r0, (0x4000 - 4)
	88	_copy_fdt:
	89	lw r12, r7, r11 /* r12 = r7 + r11 */
	90	sw r12, r4, r11 /* addr[r4 + r11] = r12 */
	91	addik r11, r11, 4 /* increment counting */
	92	bgtid r3, _copy_fdt /* loop for all entries */
	93	addik r3, r3, -4 /* descrement loop */
	94	no_fdt_arg:
	95
5846cc60 MS	96	#ifdef CONFIG_MMU
	97
	98	#ifndef CONFIG_CMDLINE_BOOL
	99	/*
	100	* handling command line
	101	* copy command line to __init_end. There is space for storing command line.
	102	*/
	103	or r6, r0, r0 /* incremment */
	104	ori r4, r0, __init_end /* load address of command line */
	105	tophys(r4,r4) /* convert to phys address */
	106	ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
	107	_copy_command_line:
137d0795 MS	108	lbu r2, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */
137d0795 MS	109	sb r2, r4, r6 /* addr[r4+r6]= r7*/
5846cc60 MS	110	addik r6, r6, 1 /* increment counting */
	111	bgtid r3, _copy_command_line /* loop for all entries */
	112	addik r3, r3, -1 /* descrement loop */
	113	addik r5, r4, 0 /* add new space for command line */
	114	tovirt(r5,r5)
	115	#endif /* CONFIG_CMDLINE_BOOL */
	116
	117	#ifdef NOT_COMPILE
	118	/* save bram context */
	119	or r6, r0, r0 /* incremment */
	120	ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */
	121	ori r3, r0, (LMB_SIZE - 4)
	122	_copy_bram:
	123	lw r7, r0, r6 /* r7 = r0 + r6 */
	124	sw r7, r4, r6 /* addr[r4 + r6] = r7*/
	125	addik r6, r6, 4 /* increment counting */
	126	bgtid r3, _copy_bram /* loop for all entries */
	127	addik r3, r3, -4 /* descrement loop */
	128	#endif
	129	/* We have to turn on the MMU right away. */
	130
	131	/*
	132	* Set up the initial MMU state so we can do the first level of
	133	* kernel initialization. This maps the first 16 MBytes of memory 1:1
	134	* virtual to physical.
	135	*/
	136	nop
0691c97d	137	addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */
5846cc60 MS	138	_invalidate:
	139	mts rtlbx, r3
	140	mts rtlbhi, r0 /* flush: ensure V is clear */
	141	bgtid r3, _invalidate /* loop for all entries */
	142	addik r3, r3, -1
	143	/* sync */
	144
137d0795 MS	145	/* Setup the kernel PID */
	146	mts rpid,r0 /* Load the kernel PID */
	147	nop
	148	bri 4
	149
5846cc60 MS	150	/*
	151	* We should still be executing code at physical address area
	152	* RAM_BASEADDR at this point. However, kernel code is at
	153	* a virtual address. So, set up a TLB mapping to cover this once
	154	* translation is enabled.
	155	*/
	156
	157	addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
	158	tophys(r4,r3) /* Load the kernel physical address */
	159
5846cc60 MS	160	/*
	161	* Configure and load two entries into TLB slots 0 and 1.
	162	* In case we are pinning TLBs, these are reserved in by the
	163	* other TLB functions. If not reserving, then it doesn't
	164	* matter where they are loaded.
	165	*/
	166	andi r4,r4,0xfffffc00 /* Mask off the real page number */
	167	ori r4,r4,(TLB_WR \| TLB_EX) /* Set the write and execute bits */
	168
	169	andi r3,r3,0xfffffc00 /* Mask off the effective page number */
	170	ori r3,r3,(TLB_VALID \| TLB_PAGESZ(PAGESZ_16M))
	171
	172	mts rtlbx,r0 /* TLB slow 0 */
	173
	174	mts rtlblo,r4 /* Load the data portion of the entry */
	175	mts rtlbhi,r3 /* Load the tag portion of the entry */
	176
	177	addik r4, r4, 0x01000000 /* Map next 16 M entries */
	178	addik r3, r3, 0x01000000
	179
	180	ori r6,r0,1 /* TLB slot 1 */
	181	mts rtlbx,r6
	182
	183	mts rtlblo,r4 /* Load the data portion of the entry */
	184	mts rtlbhi,r3 /* Load the tag portion of the entry */
	185
	186	/*
	187	* Load a TLB entry for LMB, since we need access to
	188	* the exception vectors, using a 4k real==virtual mapping.
	189	*/
	190	ori r6,r0,3 /* TLB slot 3 */
	191	mts rtlbx,r6
	192
	193	ori r4,r0,(TLB_WR \| TLB_EX)
	194	ori r3,r0,(TLB_VALID \| TLB_PAGESZ(PAGESZ_4K))
	195
	196	mts rtlblo,r4 /* Load the data portion of the entry */
	197	mts rtlbhi,r3 /* Load the tag portion of the entry */
	198
	199	/*
	200	* We now have the lower 16 Meg of RAM mapped into TLB entries, and the
	201	* caches ready to work.
	202	*/
	203	turn_on_mmu:
	204	ori r15,r0,start_here
	205	ori r4,r0,MSR_KERNEL_VMS
	206	mts rmsr,r4
	207	nop
	208	rted r15,0 /* enables MMU */
	209	nop
	210
	211	start_here:
	212	#endif /* CONFIG_MMU */
	213
6d5af1a3 MS	214	/* Initialize small data anchors */
	215	la r13, r0, _KERNEL_SDA_BASE_
	216	la r2, r0, _KERNEL_SDA2_BASE_
	217
	218	/* Initialize stack pointer */
	219	la r1, r0, init_thread_union + THREAD_SIZE - 4
	220
	221	/* Initialize r31 with current task address */
	222	la r31, r0, init_task
	223
	224	/*
	225	* Call platform dependent initialize function.
	226	* Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
	227	* the function.
	228	*/
2622434e MS	229	la r9, r0, machine_early_init
2622434e MS	230	brald r15, r9
6d5af1a3 MS	231	nop
6d5af1a3 MS	232
5846cc60	233	#ifndef CONFIG_MMU
6d5af1a3 MS	234	la r15, r0, machine_halt
	235	braid start_kernel
	236	nop
5846cc60 MS	237	#else
	238	/*
	239	* Initialize the MMU.
	240	*/
	241	bralid r15, mmu_init
	242	nop
	243
	244	/* Go back to running unmapped so we can load up new values
	245	* and change to using our exception vectors.
	246	* On the MicroBlaze, all we invalidate the used TLB entries to clear
	247	* the old 16M byte TLB mappings.
	248	*/
	249	ori r15,r0,TOPHYS(kernel_load_context)
	250	ori r4,r0,MSR_KERNEL
	251	mts rmsr,r4
	252	nop
	253	bri 4
	254	rted r15,0
	255	nop
	256
	257	/* Load up the kernel context */
	258	kernel_load_context:
	259	# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
	260	ori r5,r0,3
	261	mts rtlbx,r5
	262	nop
	263	mts rtlbhi,r0
	264	nop
	265	addi r15, r0, machine_halt
	266	ori r17, r0, start_kernel
	267	ori r4, r0, MSR_KERNEL_VMS
	268	mts rmsr, r4
	269	nop
	270	rted r17, 0 /* enable MMU and jump to start_kernel */
	271	nop
	272	#endif /* CONFIG_MMU */