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1da177e4 LT |
1 | /* |
2 | * linux/arch/m68knommu/mm/memory.c | |
3 | * | |
4 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, | |
5 | * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) | |
6 | * | |
7 | * Based on: | |
8 | * | |
9 | * linux/arch/m68k/mm/memory.c | |
10 | * | |
11 | * Copyright (C) 1995 Hamish Macdonald | |
12 | */ | |
13 | ||
14 | #include <linux/config.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/slab.h> | |
20 | ||
21 | #include <asm/setup.h> | |
22 | #include <asm/segment.h> | |
23 | #include <asm/page.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/system.h> | |
26 | #include <asm/traps.h> | |
27 | #include <asm/io.h> | |
28 | ||
29 | /* | |
30 | * cache_clear() semantics: Clear any cache entries for the area in question, | |
31 | * without writing back dirty entries first. This is useful if the data will | |
32 | * be overwritten anyway, e.g. by DMA to memory. The range is defined by a | |
33 | * _physical_ address. | |
34 | */ | |
35 | ||
36 | void cache_clear (unsigned long paddr, int len) | |
37 | { | |
38 | } | |
39 | ||
40 | ||
41 | /* | |
42 | * Define cache invalidate functions. The ColdFire 5407 is really | |
43 | * the only processor that needs to do some work here. Anything | |
44 | * that has separate data and instruction caches will be a problem. | |
45 | */ | |
46 | #ifdef CONFIG_M5407 | |
47 | ||
48 | static __inline__ void cache_invalidate_lines(unsigned long paddr, int len) | |
49 | { | |
50 | unsigned long sset, eset; | |
51 | ||
52 | sset = (paddr & 0x00000ff0); | |
53 | eset = ((paddr + len) & 0x0000ff0) + 0x10; | |
54 | ||
55 | __asm__ __volatile__ ( | |
56 | "nop\n\t" | |
57 | "clrl %%d0\n\t" | |
58 | "1:\n\t" | |
59 | "movel %0,%%a0\n\t" | |
60 | "addl %%d0,%%a0\n\t" | |
61 | "2:\n\t" | |
62 | ".word 0xf4e8\n\t" | |
63 | "addl #0x10,%%a0\n\t" | |
64 | "cmpl %1,%%a0\n\t" | |
65 | "blt 2b\n\t" | |
66 | "addql #1,%%d0\n\t" | |
67 | "cmpil #4,%%d0\n\t" | |
68 | "bne 1b" | |
69 | : : "a" (sset), "a" (eset) : "d0", "a0" ); | |
70 | } | |
71 | ||
72 | #else | |
73 | #define cache_invalidate_lines(a,b) | |
74 | #endif | |
75 | ||
76 | ||
77 | /* | |
78 | * cache_push() semantics: Write back any dirty cache data in the given area, | |
79 | * and invalidate the range in the instruction cache. It needs not (but may) | |
80 | * invalidate those entries also in the data cache. The range is defined by a | |
81 | * _physical_ address. | |
82 | */ | |
83 | ||
84 | void cache_push (unsigned long paddr, int len) | |
85 | { | |
86 | cache_invalidate_lines(paddr, len); | |
87 | } | |
88 | ||
89 | ||
90 | /* | |
91 | * cache_push_v() semantics: Write back any dirty cache data in the given | |
92 | * area, and invalidate those entries at least in the instruction cache. This | |
93 | * is intended to be used after data has been written that can be executed as | |
94 | * code later. The range is defined by a _user_mode_ _virtual_ address (or, | |
95 | * more exactly, the space is defined by the %sfc/%dfc register.) | |
96 | */ | |
97 | ||
98 | void cache_push_v (unsigned long vaddr, int len) | |
99 | { | |
100 | cache_invalidate_lines(vaddr, len); | |
101 | } | |
102 | ||
103 | /* Map some physical address range into the kernel address space. The | |
104 | * code is copied and adapted from map_chunk(). | |
105 | */ | |
106 | ||
107 | unsigned long kernel_map(unsigned long paddr, unsigned long size, | |
108 | int nocacheflag, unsigned long *memavailp ) | |
109 | { | |
110 | return paddr; | |
111 | } | |
112 | ||
113 | ||
114 | int is_in_rom(unsigned long addr) | |
115 | { | |
116 | extern unsigned long _ramstart, _ramend; | |
117 | ||
118 | /* | |
119 | * What we are really trying to do is determine if addr is | |
120 | * in an allocated kernel memory region. If not then assume | |
121 | * we cannot free it or otherwise de-allocate it. Ideally | |
122 | * we could restrict this to really being in a ROM or flash, | |
123 | * but that would need to be done on a board by board basis, | |
124 | * not globally. | |
125 | */ | |
126 | if ((addr < _ramstart) || (addr >= _ramend)) | |
127 | return(1); | |
128 | ||
129 | /* Default case, not in ROM */ | |
130 | return(0); | |
131 | } | |
132 |