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1da177e4 LT |
1 | /* |
2 | * I/O SAPIC support. | |
3 | * | |
4 | * Copyright (C) 1999 Intel Corp. | |
5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
8 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
9 | * Copyright (C) 1999 VA Linux Systems | |
10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
11 | * | |
12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code. | |
13 | * In particular, we now have separate handlers for edge | |
14 | * and level triggered interrupts. | |
15 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation | |
16 | * PCI to vector mapping, shared PCI interrupts. | |
17 | * 00/10/27 D. Mosberger Document things a bit more to make them more understandable. | |
18 | * Clean up much of the old IOSAPIC cruft. | |
19 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for | |
20 | * ACPI S5(SoftOff) support. | |
21 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT | |
22 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in | |
23 | * iosapic_set_affinity(), initializations for | |
24 | * /proc/irq/#/smp_affinity | |
25 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. | |
26 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
27 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping | |
28 | * error | |
29 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically | |
30 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.) | |
31 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code. | |
32 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. | |
33 | * Remove iosapic_address & gsi_base from external interfaces. | |
34 | * Rationalize __init/__devinit attributes. | |
35 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 | |
36 | * Updated to work with irq migration necessary for CPU Hotplug | |
37 | */ | |
38 | /* | |
39 | * Here is what the interrupt logic between a PCI device and the kernel looks like: | |
40 | * | |
41 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The | |
42 | * device is uniquely identified by its bus--, and slot-number (the function | |
43 | * number does not matter here because all functions share the same interrupt | |
44 | * lines). | |
45 | * | |
46 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller. | |
47 | * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level | |
48 | * triggered and use the same polarity). Each interrupt line has a unique Global | |
49 | * System Interrupt (GSI) number which can be calculated as the sum of the controller's | |
50 | * base GSI number and the IOSAPIC pin number to which the line connects. | |
51 | * | |
52 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin | |
53 | * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU. | |
54 | * | |
55 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as | |
56 | * architecture-independent interrupt handling mechanism in Linux. As an | |
57 | * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number | |
58 | * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and | |
59 | * IRQ. A platform can implement platform_irq_to_vector(irq) and | |
60 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. | |
61 | * Please see also include/asm-ia64/hw_irq.h for those APIs. | |
62 | * | |
63 | * To sum up, there are three levels of mappings involved: | |
64 | * | |
65 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
66 | * | |
67 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts. | |
68 | * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this | |
69 | * source code. | |
70 | */ | |
71 | #include <linux/config.h> | |
72 | ||
73 | #include <linux/acpi.h> | |
74 | #include <linux/init.h> | |
75 | #include <linux/irq.h> | |
76 | #include <linux/kernel.h> | |
77 | #include <linux/list.h> | |
78 | #include <linux/pci.h> | |
79 | #include <linux/smp.h> | |
80 | #include <linux/smp_lock.h> | |
81 | #include <linux/string.h> | |
24eeb568 | 82 | #include <linux/bootmem.h> |
1da177e4 LT |
83 | |
84 | #include <asm/delay.h> | |
85 | #include <asm/hw_irq.h> | |
86 | #include <asm/io.h> | |
87 | #include <asm/iosapic.h> | |
88 | #include <asm/machvec.h> | |
89 | #include <asm/processor.h> | |
90 | #include <asm/ptrace.h> | |
91 | #include <asm/system.h> | |
92 | ||
93 | ||
94 | #undef DEBUG_INTERRUPT_ROUTING | |
95 | ||
96 | #ifdef DEBUG_INTERRUPT_ROUTING | |
97 | #define DBG(fmt...) printk(fmt) | |
98 | #else | |
99 | #define DBG(fmt...) | |
100 | #endif | |
101 | ||
24eeb568 KK |
102 | #define NR_PREALLOCATE_RTE_ENTRIES (PAGE_SIZE / sizeof(struct iosapic_rte_info)) |
103 | #define RTE_PREALLOCATED (1) | |
104 | ||
1da177e4 LT |
105 | static DEFINE_SPINLOCK(iosapic_lock); |
106 | ||
107 | /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */ | |
108 | ||
24eeb568 KK |
109 | struct iosapic_rte_info { |
110 | struct list_head rte_list; /* node in list of RTEs sharing the same vector */ | |
1da177e4 | 111 | char __iomem *addr; /* base address of IOSAPIC */ |
1da177e4 | 112 | unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */ |
24eeb568 KK |
113 | char rte_index; /* IOSAPIC RTE index */ |
114 | int refcnt; /* reference counter */ | |
115 | unsigned int flags; /* flags */ | |
116 | } ____cacheline_aligned; | |
117 | ||
118 | static struct iosapic_intr_info { | |
119 | struct list_head rtes; /* RTEs using this vector (empty => not an IOSAPIC interrupt) */ | |
120 | int count; /* # of RTEs that shares this vector */ | |
121 | u32 low32; /* current value of low word of Redirection table entry */ | |
122 | unsigned int dest; /* destination CPU physical ID */ | |
1da177e4 LT |
123 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
124 | unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */ | |
125 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ | |
1da177e4 LT |
126 | } iosapic_intr_info[IA64_NUM_VECTORS]; |
127 | ||
128 | static struct iosapic { | |
129 | char __iomem *addr; /* base address of IOSAPIC */ | |
130 | unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */ | |
131 | unsigned short num_rte; /* number of RTE in this IOSAPIC */ | |
0e888adc | 132 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ |
1da177e4 LT |
133 | #ifdef CONFIG_NUMA |
134 | unsigned short node; /* numa node association via pxm */ | |
135 | #endif | |
136 | } iosapic_lists[NR_IOSAPICS]; | |
137 | ||
0e888adc | 138 | static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */ |
1da177e4 | 139 | |
24eeb568 KK |
140 | static int iosapic_kmalloc_ok; |
141 | static LIST_HEAD(free_rte_list); | |
1da177e4 LT |
142 | |
143 | /* | |
144 | * Find an IOSAPIC associated with a GSI | |
145 | */ | |
146 | static inline int | |
147 | find_iosapic (unsigned int gsi) | |
148 | { | |
149 | int i; | |
150 | ||
0e888adc | 151 | for (i = 0; i < NR_IOSAPICS; i++) { |
1da177e4 LT |
152 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte) |
153 | return i; | |
154 | } | |
155 | ||
156 | return -1; | |
157 | } | |
158 | ||
159 | static inline int | |
160 | _gsi_to_vector (unsigned int gsi) | |
161 | { | |
162 | struct iosapic_intr_info *info; | |
24eeb568 | 163 | struct iosapic_rte_info *rte; |
1da177e4 LT |
164 | |
165 | for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info) | |
24eeb568 KK |
166 | list_for_each_entry(rte, &info->rtes, rte_list) |
167 | if (rte->gsi_base + rte->rte_index == gsi) | |
168 | return info - iosapic_intr_info; | |
1da177e4 LT |
169 | return -1; |
170 | } | |
171 | ||
172 | /* | |
173 | * Translate GSI number to the corresponding IA-64 interrupt vector. If no | |
174 | * entry exists, return -1. | |
175 | */ | |
176 | inline int | |
177 | gsi_to_vector (unsigned int gsi) | |
178 | { | |
179 | return _gsi_to_vector(gsi); | |
180 | } | |
181 | ||
182 | int | |
183 | gsi_to_irq (unsigned int gsi) | |
184 | { | |
24eeb568 KK |
185 | unsigned long flags; |
186 | int irq; | |
1da177e4 LT |
187 | /* |
188 | * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq | |
189 | * numbers... | |
190 | */ | |
24eeb568 KK |
191 | spin_lock_irqsave(&iosapic_lock, flags); |
192 | { | |
193 | irq = _gsi_to_vector(gsi); | |
194 | } | |
195 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
196 | ||
197 | return irq; | |
198 | } | |
199 | ||
200 | static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi, unsigned int vec) | |
201 | { | |
202 | struct iosapic_rte_info *rte; | |
203 | ||
204 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) | |
205 | if (rte->gsi_base + rte->rte_index == gsi) | |
206 | return rte; | |
207 | return NULL; | |
1da177e4 LT |
208 | } |
209 | ||
210 | static void | |
24eeb568 | 211 | set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask) |
1da177e4 LT |
212 | { |
213 | unsigned long pol, trigger, dmode; | |
214 | u32 low32, high32; | |
215 | char __iomem *addr; | |
216 | int rte_index; | |
217 | char redir; | |
24eeb568 | 218 | struct iosapic_rte_info *rte; |
1da177e4 LT |
219 | |
220 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
221 | ||
24eeb568 KK |
222 | rte = gsi_vector_to_rte(gsi, vector); |
223 | if (!rte) | |
1da177e4 LT |
224 | return; /* not an IOSAPIC interrupt */ |
225 | ||
24eeb568 KK |
226 | rte_index = rte->rte_index; |
227 | addr = rte->addr; | |
1da177e4 LT |
228 | pol = iosapic_intr_info[vector].polarity; |
229 | trigger = iosapic_intr_info[vector].trigger; | |
230 | dmode = iosapic_intr_info[vector].dmode; | |
1da177e4 LT |
231 | |
232 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
233 | ||
234 | #ifdef CONFIG_SMP | |
235 | { | |
236 | unsigned int irq; | |
237 | ||
238 | for (irq = 0; irq < NR_IRQS; ++irq) | |
239 | if (irq_to_vector(irq) == vector) { | |
240 | set_irq_affinity_info(irq, (int)(dest & 0xffff), redir); | |
241 | break; | |
242 | } | |
243 | } | |
244 | #endif | |
245 | ||
246 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
247 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
248 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
249 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
250 | vector); | |
251 | ||
252 | /* dest contains both id and eid */ | |
253 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
254 | ||
255 | iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); | |
256 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); | |
257 | iosapic_intr_info[vector].low32 = low32; | |
24eeb568 | 258 | iosapic_intr_info[vector].dest = dest; |
1da177e4 LT |
259 | } |
260 | ||
261 | static void | |
262 | nop (unsigned int vector) | |
263 | { | |
264 | /* do nothing... */ | |
265 | } | |
266 | ||
267 | static void | |
268 | mask_irq (unsigned int irq) | |
269 | { | |
270 | unsigned long flags; | |
271 | char __iomem *addr; | |
272 | u32 low32; | |
273 | int rte_index; | |
274 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 275 | struct iosapic_rte_info *rte; |
1da177e4 | 276 | |
24eeb568 | 277 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
278 | return; /* not an IOSAPIC interrupt! */ |
279 | ||
280 | spin_lock_irqsave(&iosapic_lock, flags); | |
281 | { | |
282 | /* set only the mask bit */ | |
283 | low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK; | |
24eeb568 KK |
284 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { |
285 | addr = rte->addr; | |
286 | rte_index = rte->rte_index; | |
287 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); | |
288 | } | |
1da177e4 LT |
289 | } |
290 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
291 | } | |
292 | ||
293 | static void | |
294 | unmask_irq (unsigned int irq) | |
295 | { | |
296 | unsigned long flags; | |
297 | char __iomem *addr; | |
298 | u32 low32; | |
299 | int rte_index; | |
300 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 301 | struct iosapic_rte_info *rte; |
1da177e4 | 302 | |
24eeb568 | 303 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
304 | return; /* not an IOSAPIC interrupt! */ |
305 | ||
306 | spin_lock_irqsave(&iosapic_lock, flags); | |
307 | { | |
308 | low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK; | |
24eeb568 KK |
309 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { |
310 | addr = rte->addr; | |
311 | rte_index = rte->rte_index; | |
312 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); | |
313 | } | |
1da177e4 LT |
314 | } |
315 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
316 | } | |
317 | ||
318 | ||
319 | static void | |
320 | iosapic_set_affinity (unsigned int irq, cpumask_t mask) | |
321 | { | |
322 | #ifdef CONFIG_SMP | |
323 | unsigned long flags; | |
324 | u32 high32, low32; | |
325 | int dest, rte_index; | |
326 | char __iomem *addr; | |
327 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; | |
328 | ia64_vector vec; | |
24eeb568 | 329 | struct iosapic_rte_info *rte; |
1da177e4 LT |
330 | |
331 | irq &= (~IA64_IRQ_REDIRECTED); | |
332 | vec = irq_to_vector(irq); | |
333 | ||
334 | if (cpus_empty(mask)) | |
335 | return; | |
336 | ||
337 | dest = cpu_physical_id(first_cpu(mask)); | |
338 | ||
24eeb568 | 339 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
340 | return; /* not an IOSAPIC interrupt */ |
341 | ||
342 | set_irq_affinity_info(irq, dest, redir); | |
343 | ||
344 | /* dest contains both id and eid */ | |
345 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
346 | ||
347 | spin_lock_irqsave(&iosapic_lock, flags); | |
348 | { | |
349 | low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); | |
350 | ||
351 | if (redir) | |
352 | /* change delivery mode to lowest priority */ | |
353 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
354 | else | |
355 | /* change delivery mode to fixed */ | |
356 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
357 | ||
358 | iosapic_intr_info[vec].low32 = low32; | |
24eeb568 KK |
359 | iosapic_intr_info[vec].dest = dest; |
360 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { | |
361 | addr = rte->addr; | |
362 | rte_index = rte->rte_index; | |
363 | iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); | |
364 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); | |
365 | } | |
1da177e4 LT |
366 | } |
367 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
368 | #endif | |
369 | } | |
370 | ||
371 | /* | |
372 | * Handlers for level-triggered interrupts. | |
373 | */ | |
374 | ||
375 | static unsigned int | |
376 | iosapic_startup_level_irq (unsigned int irq) | |
377 | { | |
378 | unmask_irq(irq); | |
379 | return 0; | |
380 | } | |
381 | ||
382 | static void | |
383 | iosapic_end_level_irq (unsigned int irq) | |
384 | { | |
385 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 386 | struct iosapic_rte_info *rte; |
1da177e4 LT |
387 | |
388 | move_irq(irq); | |
24eeb568 KK |
389 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) |
390 | iosapic_eoi(rte->addr, vec); | |
1da177e4 LT |
391 | } |
392 | ||
393 | #define iosapic_shutdown_level_irq mask_irq | |
394 | #define iosapic_enable_level_irq unmask_irq | |
395 | #define iosapic_disable_level_irq mask_irq | |
396 | #define iosapic_ack_level_irq nop | |
397 | ||
398 | struct hw_interrupt_type irq_type_iosapic_level = { | |
399 | .typename = "IO-SAPIC-level", | |
400 | .startup = iosapic_startup_level_irq, | |
401 | .shutdown = iosapic_shutdown_level_irq, | |
402 | .enable = iosapic_enable_level_irq, | |
403 | .disable = iosapic_disable_level_irq, | |
404 | .ack = iosapic_ack_level_irq, | |
405 | .end = iosapic_end_level_irq, | |
406 | .set_affinity = iosapic_set_affinity | |
407 | }; | |
408 | ||
409 | /* | |
410 | * Handlers for edge-triggered interrupts. | |
411 | */ | |
412 | ||
413 | static unsigned int | |
414 | iosapic_startup_edge_irq (unsigned int irq) | |
415 | { | |
416 | unmask_irq(irq); | |
417 | /* | |
418 | * IOSAPIC simply drops interrupts pended while the | |
419 | * corresponding pin was masked, so we can't know if an | |
420 | * interrupt is pending already. Let's hope not... | |
421 | */ | |
422 | return 0; | |
423 | } | |
424 | ||
425 | static void | |
426 | iosapic_ack_edge_irq (unsigned int irq) | |
427 | { | |
428 | irq_desc_t *idesc = irq_descp(irq); | |
429 | ||
430 | move_irq(irq); | |
431 | /* | |
432 | * Once we have recorded IRQ_PENDING already, we can mask the | |
433 | * interrupt for real. This prevents IRQ storms from unhandled | |
434 | * devices. | |
435 | */ | |
436 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED)) | |
437 | mask_irq(irq); | |
438 | } | |
439 | ||
440 | #define iosapic_enable_edge_irq unmask_irq | |
441 | #define iosapic_disable_edge_irq nop | |
442 | #define iosapic_end_edge_irq nop | |
443 | ||
444 | struct hw_interrupt_type irq_type_iosapic_edge = { | |
445 | .typename = "IO-SAPIC-edge", | |
446 | .startup = iosapic_startup_edge_irq, | |
447 | .shutdown = iosapic_disable_edge_irq, | |
448 | .enable = iosapic_enable_edge_irq, | |
449 | .disable = iosapic_disable_edge_irq, | |
450 | .ack = iosapic_ack_edge_irq, | |
451 | .end = iosapic_end_edge_irq, | |
452 | .set_affinity = iosapic_set_affinity | |
453 | }; | |
454 | ||
455 | unsigned int | |
456 | iosapic_version (char __iomem *addr) | |
457 | { | |
458 | /* | |
459 | * IOSAPIC Version Register return 32 bit structure like: | |
460 | * { | |
461 | * unsigned int version : 8; | |
462 | * unsigned int reserved1 : 8; | |
463 | * unsigned int max_redir : 8; | |
464 | * unsigned int reserved2 : 8; | |
465 | * } | |
466 | */ | |
467 | return iosapic_read(addr, IOSAPIC_VERSION); | |
468 | } | |
469 | ||
24eeb568 KK |
470 | static int iosapic_find_sharable_vector (unsigned long trigger, unsigned long pol) |
471 | { | |
472 | int i, vector = -1, min_count = -1; | |
473 | struct iosapic_intr_info *info; | |
474 | ||
475 | /* | |
476 | * shared vectors for edge-triggered interrupts are not | |
477 | * supported yet | |
478 | */ | |
479 | if (trigger == IOSAPIC_EDGE) | |
480 | return -1; | |
481 | ||
482 | for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) { | |
483 | info = &iosapic_intr_info[i]; | |
484 | if (info->trigger == trigger && info->polarity == pol && | |
485 | (info->dmode == IOSAPIC_FIXED || info->dmode == IOSAPIC_LOWEST_PRIORITY)) { | |
486 | if (min_count == -1 || info->count < min_count) { | |
487 | vector = i; | |
488 | min_count = info->count; | |
489 | } | |
490 | } | |
491 | } | |
24eeb568 KK |
492 | |
493 | return vector; | |
494 | } | |
495 | ||
1da177e4 LT |
496 | /* |
497 | * if the given vector is already owned by other, | |
498 | * assign a new vector for the other and make the vector available | |
499 | */ | |
500 | static void __init | |
501 | iosapic_reassign_vector (int vector) | |
502 | { | |
503 | int new_vector; | |
504 | ||
24eeb568 | 505 | if (!list_empty(&iosapic_intr_info[vector].rtes)) { |
1da177e4 | 506 | new_vector = assign_irq_vector(AUTO_ASSIGN); |
3b5cc090 KK |
507 | if (new_vector < 0) |
508 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); | |
1da177e4 LT |
509 | printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector); |
510 | memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector], | |
511 | sizeof(struct iosapic_intr_info)); | |
24eeb568 KK |
512 | INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes); |
513 | list_move(iosapic_intr_info[vector].rtes.next, &iosapic_intr_info[new_vector].rtes); | |
1da177e4 | 514 | memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info)); |
24eeb568 KK |
515 | iosapic_intr_info[vector].low32 = IOSAPIC_MASK; |
516 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
1da177e4 LT |
517 | } |
518 | } | |
519 | ||
24eeb568 KK |
520 | static struct iosapic_rte_info *iosapic_alloc_rte (void) |
521 | { | |
522 | int i; | |
523 | struct iosapic_rte_info *rte; | |
524 | int preallocated = 0; | |
525 | ||
526 | if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) { | |
527 | rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * NR_PREALLOCATE_RTE_ENTRIES); | |
528 | if (!rte) | |
529 | return NULL; | |
530 | for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++) | |
531 | list_add(&rte->rte_list, &free_rte_list); | |
532 | } | |
533 | ||
534 | if (!list_empty(&free_rte_list)) { | |
535 | rte = list_entry(free_rte_list.next, struct iosapic_rte_info, rte_list); | |
536 | list_del(&rte->rte_list); | |
537 | preallocated++; | |
538 | } else { | |
539 | rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC); | |
540 | if (!rte) | |
541 | return NULL; | |
542 | } | |
543 | ||
544 | memset(rte, 0, sizeof(struct iosapic_rte_info)); | |
545 | if (preallocated) | |
546 | rte->flags |= RTE_PREALLOCATED; | |
547 | ||
548 | return rte; | |
549 | } | |
550 | ||
551 | static void iosapic_free_rte (struct iosapic_rte_info *rte) | |
552 | { | |
553 | if (rte->flags & RTE_PREALLOCATED) | |
554 | list_add_tail(&rte->rte_list, &free_rte_list); | |
555 | else | |
556 | kfree(rte); | |
557 | } | |
558 | ||
559 | static inline int vector_is_shared (int vector) | |
560 | { | |
561 | return (iosapic_intr_info[vector].count > 1); | |
562 | } | |
563 | ||
14454a1b | 564 | static int |
1da177e4 LT |
565 | register_intr (unsigned int gsi, int vector, unsigned char delivery, |
566 | unsigned long polarity, unsigned long trigger) | |
567 | { | |
568 | irq_desc_t *idesc; | |
569 | struct hw_interrupt_type *irq_type; | |
570 | int rte_index; | |
571 | int index; | |
572 | unsigned long gsi_base; | |
573 | void __iomem *iosapic_address; | |
24eeb568 | 574 | struct iosapic_rte_info *rte; |
1da177e4 LT |
575 | |
576 | index = find_iosapic(gsi); | |
577 | if (index < 0) { | |
578 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", __FUNCTION__, gsi); | |
14454a1b | 579 | return -ENODEV; |
1da177e4 LT |
580 | } |
581 | ||
582 | iosapic_address = iosapic_lists[index].addr; | |
583 | gsi_base = iosapic_lists[index].gsi_base; | |
584 | ||
24eeb568 KK |
585 | rte = gsi_vector_to_rte(gsi, vector); |
586 | if (!rte) { | |
587 | rte = iosapic_alloc_rte(); | |
588 | if (!rte) { | |
589 | printk(KERN_WARNING "%s: cannot allocate memory\n", __FUNCTION__); | |
14454a1b | 590 | return -ENOMEM; |
24eeb568 KK |
591 | } |
592 | ||
593 | rte_index = gsi - gsi_base; | |
594 | rte->rte_index = rte_index; | |
595 | rte->addr = iosapic_address; | |
596 | rte->gsi_base = gsi_base; | |
597 | rte->refcnt++; | |
598 | list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes); | |
599 | iosapic_intr_info[vector].count++; | |
0e888adc | 600 | iosapic_lists[index].rtes_inuse++; |
24eeb568 KK |
601 | } |
602 | else if (vector_is_shared(vector)) { | |
603 | struct iosapic_intr_info *info = &iosapic_intr_info[vector]; | |
604 | if (info->trigger != trigger || info->polarity != polarity) { | |
605 | printk (KERN_WARNING "%s: cannot override the interrupt\n", __FUNCTION__); | |
14454a1b | 606 | return -EINVAL; |
24eeb568 KK |
607 | } |
608 | } | |
609 | ||
1da177e4 LT |
610 | iosapic_intr_info[vector].polarity = polarity; |
611 | iosapic_intr_info[vector].dmode = delivery; | |
1da177e4 | 612 | iosapic_intr_info[vector].trigger = trigger; |
1da177e4 LT |
613 | |
614 | if (trigger == IOSAPIC_EDGE) | |
615 | irq_type = &irq_type_iosapic_edge; | |
616 | else | |
617 | irq_type = &irq_type_iosapic_level; | |
618 | ||
619 | idesc = irq_descp(vector); | |
620 | if (idesc->handler != irq_type) { | |
621 | if (idesc->handler != &no_irq_type) | |
622 | printk(KERN_WARNING "%s: changing vector %d from %s to %s\n", | |
623 | __FUNCTION__, vector, idesc->handler->typename, irq_type->typename); | |
624 | idesc->handler = irq_type; | |
625 | } | |
14454a1b | 626 | return 0; |
1da177e4 LT |
627 | } |
628 | ||
629 | static unsigned int | |
630 | get_target_cpu (unsigned int gsi, int vector) | |
631 | { | |
632 | #ifdef CONFIG_SMP | |
633 | static int cpu = -1; | |
ff741906 | 634 | extern int cpe_vector; |
1da177e4 | 635 | |
24eeb568 KK |
636 | /* |
637 | * In case of vector shared by multiple RTEs, all RTEs that | |
638 | * share the vector need to use the same destination CPU. | |
639 | */ | |
640 | if (!list_empty(&iosapic_intr_info[vector].rtes)) | |
641 | return iosapic_intr_info[vector].dest; | |
642 | ||
1da177e4 LT |
643 | /* |
644 | * If the platform supports redirection via XTP, let it | |
645 | * distribute interrupts. | |
646 | */ | |
647 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
648 | return cpu_physical_id(smp_processor_id()); | |
649 | ||
650 | /* | |
651 | * Some interrupts (ACPI SCI, for instance) are registered | |
652 | * before the BSP is marked as online. | |
653 | */ | |
654 | if (!cpu_online(smp_processor_id())) | |
655 | return cpu_physical_id(smp_processor_id()); | |
656 | ||
ff741906 | 657 | #ifdef CONFIG_ACPI |
b88e9265 AR |
658 | if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR) |
659 | return get_cpei_target_cpu(); | |
ff741906 AR |
660 | #endif |
661 | ||
1da177e4 LT |
662 | #ifdef CONFIG_NUMA |
663 | { | |
664 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
665 | cpumask_t cpu_mask; | |
666 | ||
667 | iosapic_index = find_iosapic(gsi); | |
668 | if (iosapic_index < 0 || | |
669 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
670 | goto skip_numa_setup; | |
671 | ||
672 | cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node); | |
673 | ||
674 | for_each_cpu_mask(numa_cpu, cpu_mask) { | |
675 | if (!cpu_online(numa_cpu)) | |
676 | cpu_clear(numa_cpu, cpu_mask); | |
677 | } | |
678 | ||
679 | num_cpus = cpus_weight(cpu_mask); | |
680 | ||
681 | if (!num_cpus) | |
682 | goto skip_numa_setup; | |
683 | ||
684 | /* Use vector assigment to distribute across cpus in node */ | |
685 | cpu_index = vector % num_cpus; | |
686 | ||
687 | for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++) | |
688 | numa_cpu = next_cpu(numa_cpu, cpu_mask); | |
689 | ||
690 | if (numa_cpu != NR_CPUS) | |
691 | return cpu_physical_id(numa_cpu); | |
692 | } | |
693 | skip_numa_setup: | |
694 | #endif | |
695 | /* | |
696 | * Otherwise, round-robin interrupt vectors across all the | |
697 | * processors. (It'd be nice if we could be smarter in the | |
698 | * case of NUMA.) | |
699 | */ | |
700 | do { | |
701 | if (++cpu >= NR_CPUS) | |
702 | cpu = 0; | |
703 | } while (!cpu_online(cpu)); | |
704 | ||
705 | return cpu_physical_id(cpu); | |
706 | #else | |
707 | return cpu_physical_id(smp_processor_id()); | |
708 | #endif | |
709 | } | |
710 | ||
711 | /* | |
712 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
713 | * methods. This provides an interface to register those interrupts and | |
714 | * program the IOSAPIC RTE. | |
715 | */ | |
716 | int | |
717 | iosapic_register_intr (unsigned int gsi, | |
718 | unsigned long polarity, unsigned long trigger) | |
719 | { | |
14454a1b | 720 | int vector, mask = 1, err; |
1da177e4 LT |
721 | unsigned int dest; |
722 | unsigned long flags; | |
24eeb568 KK |
723 | struct iosapic_rte_info *rte; |
724 | u32 low32; | |
725 | again: | |
1da177e4 LT |
726 | /* |
727 | * If this GSI has already been registered (i.e., it's a | |
728 | * shared interrupt, or we lost a race to register it), | |
729 | * don't touch the RTE. | |
730 | */ | |
731 | spin_lock_irqsave(&iosapic_lock, flags); | |
732 | { | |
733 | vector = gsi_to_vector(gsi); | |
734 | if (vector > 0) { | |
24eeb568 KK |
735 | rte = gsi_vector_to_rte(gsi, vector); |
736 | rte->refcnt++; | |
1da177e4 LT |
737 | spin_unlock_irqrestore(&iosapic_lock, flags); |
738 | return vector; | |
739 | } | |
24eeb568 KK |
740 | } |
741 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
742 | ||
743 | /* If vector is running out, we try to find a sharable vector */ | |
3b5cc090 KK |
744 | vector = assign_irq_vector(AUTO_ASSIGN); |
745 | if (vector < 0) { | |
24eeb568 | 746 | vector = iosapic_find_sharable_vector(trigger, polarity); |
14454a1b | 747 | if (vector < 0) |
702c7e76 | 748 | return -ENOSPC; |
3b5cc090 | 749 | } |
24eeb568 KK |
750 | |
751 | spin_lock_irqsave(&irq_descp(vector)->lock, flags); | |
752 | spin_lock(&iosapic_lock); | |
753 | { | |
754 | if (gsi_to_vector(gsi) > 0) { | |
755 | if (list_empty(&iosapic_intr_info[vector].rtes)) | |
756 | free_irq_vector(vector); | |
757 | spin_unlock(&iosapic_lock); | |
758 | spin_unlock_irqrestore(&irq_descp(vector)->lock, flags); | |
759 | goto again; | |
760 | } | |
1da177e4 | 761 | |
1da177e4 | 762 | dest = get_target_cpu(gsi, vector); |
14454a1b | 763 | err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, |
24eeb568 | 764 | polarity, trigger); |
14454a1b KK |
765 | if (err < 0) { |
766 | spin_unlock(&iosapic_lock); | |
767 | spin_unlock_irqrestore(&irq_descp(vector)->lock, flags); | |
768 | return err; | |
769 | } | |
1da177e4 | 770 | |
24eeb568 KK |
771 | /* |
772 | * If the vector is shared and already unmasked for | |
773 | * other interrupt sources, don't mask it. | |
774 | */ | |
775 | low32 = iosapic_intr_info[vector].low32; | |
776 | if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK)) | |
777 | mask = 0; | |
778 | set_rte(gsi, vector, dest, mask); | |
1da177e4 | 779 | } |
b9e41d7f | 780 | spin_unlock(&iosapic_lock); |
24eeb568 | 781 | spin_unlock_irqrestore(&irq_descp(vector)->lock, flags); |
1da177e4 LT |
782 | |
783 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
784 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
785 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
786 | cpu_logical_id(dest), dest, vector); | |
787 | ||
788 | return vector; | |
789 | } | |
790 | ||
1da177e4 LT |
791 | void |
792 | iosapic_unregister_intr (unsigned int gsi) | |
793 | { | |
794 | unsigned long flags; | |
0e888adc | 795 | int irq, vector, index; |
1da177e4 | 796 | irq_desc_t *idesc; |
24eeb568 | 797 | u32 low32; |
1da177e4 | 798 | unsigned long trigger, polarity; |
24eeb568 KK |
799 | unsigned int dest; |
800 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
801 | |
802 | /* | |
803 | * If the irq associated with the gsi is not found, | |
804 | * iosapic_unregister_intr() is unbalanced. We need to check | |
805 | * this again after getting locks. | |
806 | */ | |
807 | irq = gsi_to_irq(gsi); | |
808 | if (irq < 0) { | |
809 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi); | |
810 | WARN_ON(1); | |
811 | return; | |
812 | } | |
813 | vector = irq_to_vector(irq); | |
814 | ||
815 | idesc = irq_descp(irq); | |
816 | spin_lock_irqsave(&idesc->lock, flags); | |
817 | spin_lock(&iosapic_lock); | |
818 | { | |
24eeb568 | 819 | if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) { |
1da177e4 LT |
820 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi); |
821 | WARN_ON(1); | |
24eeb568 | 822 | goto out; |
1da177e4 LT |
823 | } |
824 | ||
24eeb568 KK |
825 | if (--rte->refcnt > 0) |
826 | goto out; | |
1da177e4 | 827 | |
24eeb568 KK |
828 | /* Mask the interrupt */ |
829 | low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK; | |
830 | iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32); | |
1da177e4 | 831 | |
24eeb568 KK |
832 | /* Remove the rte entry from the list */ |
833 | list_del(&rte->rte_list); | |
834 | iosapic_intr_info[vector].count--; | |
835 | iosapic_free_rte(rte); | |
0e888adc KK |
836 | index = find_iosapic(gsi); |
837 | iosapic_lists[index].rtes_inuse--; | |
838 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
1da177e4 | 839 | |
24eeb568 | 840 | trigger = iosapic_intr_info[vector].trigger; |
1da177e4 | 841 | polarity = iosapic_intr_info[vector].polarity; |
24eeb568 KK |
842 | dest = iosapic_intr_info[vector].dest; |
843 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n", | |
844 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
845 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
846 | cpu_logical_id(dest), dest, vector); | |
847 | ||
848 | if (list_empty(&iosapic_intr_info[vector].rtes)) { | |
849 | /* Sanity check */ | |
850 | BUG_ON(iosapic_intr_info[vector].count); | |
851 | ||
852 | /* Clear the interrupt controller descriptor */ | |
853 | idesc->handler = &no_irq_type; | |
854 | ||
855 | /* Clear the interrupt information */ | |
856 | memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info)); | |
857 | iosapic_intr_info[vector].low32 |= IOSAPIC_MASK; | |
858 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
859 | ||
860 | if (idesc->action) { | |
861 | printk(KERN_ERR "interrupt handlers still exist on IRQ %u\n", irq); | |
862 | WARN_ON(1); | |
863 | } | |
1da177e4 | 864 | |
24eeb568 KK |
865 | /* Free the interrupt vector */ |
866 | free_irq_vector(vector); | |
867 | } | |
1da177e4 | 868 | } |
24eeb568 | 869 | out: |
1da177e4 LT |
870 | spin_unlock(&iosapic_lock); |
871 | spin_unlock_irqrestore(&idesc->lock, flags); | |
1da177e4 | 872 | } |
1da177e4 LT |
873 | |
874 | /* | |
875 | * ACPI calls this when it finds an entry for a platform interrupt. | |
876 | * Note that the irq_base and IOSAPIC address must be set in iosapic_init(). | |
877 | */ | |
878 | int __init | |
879 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
880 | int iosapic_vector, u16 eid, u16 id, | |
881 | unsigned long polarity, unsigned long trigger) | |
882 | { | |
883 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
884 | unsigned char delivery; | |
885 | int vector, mask = 0; | |
886 | unsigned int dest = ((id << 8) | eid) & 0xffff; | |
887 | ||
888 | switch (int_type) { | |
889 | case ACPI_INTERRUPT_PMI: | |
890 | vector = iosapic_vector; | |
891 | /* | |
892 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
893 | * we need to make sure the vector is available | |
894 | */ | |
895 | iosapic_reassign_vector(vector); | |
896 | delivery = IOSAPIC_PMI; | |
897 | break; | |
898 | case ACPI_INTERRUPT_INIT: | |
899 | vector = assign_irq_vector(AUTO_ASSIGN); | |
3b5cc090 KK |
900 | if (vector < 0) |
901 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); | |
1da177e4 LT |
902 | delivery = IOSAPIC_INIT; |
903 | break; | |
904 | case ACPI_INTERRUPT_CPEI: | |
905 | vector = IA64_CPE_VECTOR; | |
906 | delivery = IOSAPIC_LOWEST_PRIORITY; | |
907 | mask = 1; | |
908 | break; | |
909 | default: | |
910 | printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type); | |
911 | return -1; | |
912 | } | |
913 | ||
914 | register_intr(gsi, vector, delivery, polarity, trigger); | |
915 | ||
916 | printk(KERN_INFO "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
917 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", | |
918 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
919 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
920 | cpu_logical_id(dest), dest, vector); | |
921 | ||
24eeb568 | 922 | set_rte(gsi, vector, dest, mask); |
1da177e4 LT |
923 | return vector; |
924 | } | |
925 | ||
926 | ||
927 | /* | |
928 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
929 | * Note that the gsi_base and IOSAPIC address must be set in iosapic_init(). | |
930 | */ | |
931 | void __init | |
932 | iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, | |
933 | unsigned long polarity, | |
934 | unsigned long trigger) | |
935 | { | |
936 | int vector; | |
937 | unsigned int dest = cpu_physical_id(smp_processor_id()); | |
938 | ||
939 | vector = isa_irq_to_vector(isa_irq); | |
940 | ||
941 | register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger); | |
942 | ||
943 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
944 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
945 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
946 | cpu_logical_id(dest), dest, vector); | |
947 | ||
24eeb568 | 948 | set_rte(gsi, vector, dest, 1); |
1da177e4 LT |
949 | } |
950 | ||
951 | void __init | |
952 | iosapic_system_init (int system_pcat_compat) | |
953 | { | |
954 | int vector; | |
955 | ||
24eeb568 KK |
956 | for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) { |
957 | iosapic_intr_info[vector].low32 = IOSAPIC_MASK; | |
958 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); /* mark as unused */ | |
959 | } | |
1da177e4 LT |
960 | |
961 | pcat_compat = system_pcat_compat; | |
962 | if (pcat_compat) { | |
963 | /* | |
964 | * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support | |
965 | * enabled. | |
966 | */ | |
967 | printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__); | |
968 | outb(0xff, 0xA1); | |
969 | outb(0xff, 0x21); | |
970 | } | |
971 | } | |
972 | ||
0e888adc KK |
973 | static inline int |
974 | iosapic_alloc (void) | |
975 | { | |
976 | int index; | |
977 | ||
978 | for (index = 0; index < NR_IOSAPICS; index++) | |
979 | if (!iosapic_lists[index].addr) | |
980 | return index; | |
981 | ||
982 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__); | |
983 | return -1; | |
984 | } | |
985 | ||
986 | static inline void | |
987 | iosapic_free (int index) | |
988 | { | |
989 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
990 | } | |
991 | ||
992 | static inline int | |
993 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
994 | { | |
995 | int index; | |
996 | unsigned int gsi_end, base, end; | |
997 | ||
998 | /* check gsi range */ | |
999 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
1000 | for (index = 0; index < NR_IOSAPICS; index++) { | |
1001 | if (!iosapic_lists[index].addr) | |
1002 | continue; | |
1003 | ||
1004 | base = iosapic_lists[index].gsi_base; | |
1005 | end = base + iosapic_lists[index].num_rte - 1; | |
1006 | ||
1007 | if (gsi_base < base && gsi_end < base) | |
1008 | continue;/* OK */ | |
1009 | ||
1010 | if (gsi_base > end && gsi_end > end) | |
1011 | continue; /* OK */ | |
1012 | ||
1013 | return -EBUSY; | |
1014 | } | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | int __devinit | |
1da177e4 LT |
1019 | iosapic_init (unsigned long phys_addr, unsigned int gsi_base) |
1020 | { | |
0e888adc | 1021 | int num_rte, err, index; |
1da177e4 LT |
1022 | unsigned int isa_irq, ver; |
1023 | char __iomem *addr; | |
0e888adc KK |
1024 | unsigned long flags; |
1025 | ||
1026 | spin_lock_irqsave(&iosapic_lock, flags); | |
1027 | { | |
1028 | addr = ioremap(phys_addr, 0); | |
1029 | ver = iosapic_version(addr); | |
1da177e4 | 1030 | |
0e888adc KK |
1031 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1032 | iounmap(addr); | |
1033 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1034 | return err; | |
1035 | } | |
1da177e4 | 1036 | |
0e888adc KK |
1037 | /* |
1038 | * The MAX_REDIR register holds the highest input pin | |
1039 | * number (starting from 0). | |
1040 | * We add 1 so that we can use it for number of pins (= RTEs) | |
1041 | */ | |
1042 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1043 | |
0e888adc KK |
1044 | index = iosapic_alloc(); |
1045 | iosapic_lists[index].addr = addr; | |
1046 | iosapic_lists[index].gsi_base = gsi_base; | |
1047 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1048 | #ifdef CONFIG_NUMA |
0e888adc | 1049 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1050 | #endif |
0e888adc KK |
1051 | } |
1052 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1da177e4 LT |
1053 | |
1054 | if ((gsi_base == 0) && pcat_compat) { | |
1055 | /* | |
1056 | * Map the legacy ISA devices into the IOSAPIC data. Some of these may | |
1057 | * get reprogrammed later on with data from the ACPI Interrupt Source | |
1058 | * Override table. | |
1059 | */ | |
1060 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
1061 | iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE); | |
1062 | } | |
0e888adc KK |
1063 | return 0; |
1064 | } | |
1065 | ||
1066 | #ifdef CONFIG_HOTPLUG | |
1067 | int | |
1068 | iosapic_remove (unsigned int gsi_base) | |
1069 | { | |
1070 | int index, err = 0; | |
1071 | unsigned long flags; | |
1072 | ||
1073 | spin_lock_irqsave(&iosapic_lock, flags); | |
1074 | { | |
1075 | index = find_iosapic(gsi_base); | |
1076 | if (index < 0) { | |
1077 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
1078 | __FUNCTION__, gsi_base); | |
1079 | goto out; | |
1080 | } | |
1081 | ||
1082 | if (iosapic_lists[index].rtes_inuse) { | |
1083 | err = -EBUSY; | |
1084 | printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n", | |
1085 | __FUNCTION__, gsi_base); | |
1086 | goto out; | |
1087 | } | |
1088 | ||
1089 | iounmap(iosapic_lists[index].addr); | |
1090 | iosapic_free(index); | |
1091 | } | |
1092 | out: | |
1093 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1094 | return err; | |
1da177e4 | 1095 | } |
0e888adc | 1096 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 LT |
1097 | |
1098 | #ifdef CONFIG_NUMA | |
0e888adc | 1099 | void __devinit |
1da177e4 LT |
1100 | map_iosapic_to_node(unsigned int gsi_base, int node) |
1101 | { | |
1102 | int index; | |
1103 | ||
1104 | index = find_iosapic(gsi_base); | |
1105 | if (index < 0) { | |
1106 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
1107 | __FUNCTION__, gsi_base); | |
1108 | return; | |
1109 | } | |
1110 | iosapic_lists[index].node = node; | |
1111 | return; | |
1112 | } | |
1113 | #endif | |
24eeb568 KK |
1114 | |
1115 | static int __init iosapic_enable_kmalloc (void) | |
1116 | { | |
1117 | iosapic_kmalloc_ok = 1; | |
1118 | return 0; | |
1119 | } | |
1120 | core_initcall (iosapic_enable_kmalloc); |