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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * I/O SAPIC support. | |
3 | * | |
4 | * Copyright (C) 1999 Intel Corp. | |
5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
8 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
9 | * Copyright (C) 1999 VA Linux Systems | |
10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
11 | * | |
46cba3dc ST |
12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O |
13 | * APIC code. In particular, we now have separate | |
14 | * handlers for edge and level triggered | |
15 | * interrupts. | |
16 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector | |
17 | * allocation PCI to vector mapping, shared PCI | |
18 | * interrupts. | |
19 | * 00/10/27 D. Mosberger Document things a bit more to make them more | |
20 | * understandable. Clean up much of the old | |
21 | * IOSAPIC cruft. | |
22 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts | |
23 | * and fixes for ACPI S5(SoftOff) support. | |
1da177e4 | 24 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
46cba3dc ST |
25 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt |
26 | * vectors in iosapic_set_affinity(), | |
27 | * initializations for /proc/irq/#/smp_affinity | |
1da177e4 LT |
28 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
29 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
46cba3dc ST |
30 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to |
31 | * IOSAPIC mapping error | |
1da177e4 | 32 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
46cba3dc ST |
33 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system |
34 | * interrupt, vector, etc.) | |
35 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's | |
36 | * pci_irq code. | |
1da177e4 | 37 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
46cba3dc ST |
38 | * Remove iosapic_address & gsi_base from |
39 | * external interfaces. Rationalize | |
40 | * __init/__devinit attributes. | |
1da177e4 | 41 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
46cba3dc ST |
42 | * Updated to work with irq migration necessary |
43 | * for CPU Hotplug | |
1da177e4 LT |
44 | */ |
45 | /* | |
46cba3dc ST |
46 | * Here is what the interrupt logic between a PCI device and the kernel looks |
47 | * like: | |
1da177e4 | 48 | * |
46cba3dc ST |
49 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, |
50 | * INTD). The device is uniquely identified by its bus-, and slot-number | |
51 | * (the function number does not matter here because all functions share | |
52 | * the same interrupt lines). | |
1da177e4 | 53 | * |
46cba3dc ST |
54 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC |
55 | * controller. Multiple interrupt lines may have to share the same | |
56 | * IOSAPIC pin (if they're level triggered and use the same polarity). | |
57 | * Each interrupt line has a unique Global System Interrupt (GSI) number | |
58 | * which can be calculated as the sum of the controller's base GSI number | |
59 | * and the IOSAPIC pin number to which the line connects. | |
1da177e4 | 60 | * |
46cba3dc ST |
61 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the |
62 | * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then | |
63 | * sent to the CPU. | |
1da177e4 | 64 | * |
46cba3dc ST |
65 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is |
66 | * used as architecture-independent interrupt handling mechanism in Linux. | |
67 | * As an IRQ is a number, we have to have | |
68 | * IA-64 interrupt vector number <-> IRQ number mapping. On smaller | |
69 | * systems, we use one-to-one mapping between IA-64 vector and IRQ. A | |
70 | * platform can implement platform_irq_to_vector(irq) and | |
1da177e4 LT |
71 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
72 | * Please see also include/asm-ia64/hw_irq.h for those APIs. | |
73 | * | |
74 | * To sum up, there are three levels of mappings involved: | |
75 | * | |
76 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
77 | * | |
46cba3dc ST |
78 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to |
79 | * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ | |
80 | * (isa_irq) is the only exception in this source code. | |
1da177e4 | 81 | */ |
1da177e4 LT |
82 | |
83 | #include <linux/acpi.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/irq.h> | |
86 | #include <linux/kernel.h> | |
87 | #include <linux/list.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/smp.h> | |
1da177e4 | 90 | #include <linux/string.h> |
24eeb568 | 91 | #include <linux/bootmem.h> |
1da177e4 LT |
92 | |
93 | #include <asm/delay.h> | |
94 | #include <asm/hw_irq.h> | |
95 | #include <asm/io.h> | |
96 | #include <asm/iosapic.h> | |
97 | #include <asm/machvec.h> | |
98 | #include <asm/processor.h> | |
99 | #include <asm/ptrace.h> | |
100 | #include <asm/system.h> | |
101 | ||
1da177e4 LT |
102 | #undef DEBUG_INTERRUPT_ROUTING |
103 | ||
104 | #ifdef DEBUG_INTERRUPT_ROUTING | |
105 | #define DBG(fmt...) printk(fmt) | |
106 | #else | |
107 | #define DBG(fmt...) | |
108 | #endif | |
109 | ||
46cba3dc ST |
110 | #define NR_PREALLOCATE_RTE_ENTRIES \ |
111 | (PAGE_SIZE / sizeof(struct iosapic_rte_info)) | |
24eeb568 KK |
112 | #define RTE_PREALLOCATED (1) |
113 | ||
1da177e4 LT |
114 | static DEFINE_SPINLOCK(iosapic_lock); |
115 | ||
46cba3dc ST |
116 | /* |
117 | * These tables map IA-64 vectors to the IOSAPIC pin that generates this | |
118 | * vector. | |
119 | */ | |
e1b30a39 YI |
120 | |
121 | #define NO_REF_RTE 0 | |
122 | ||
c5e3f9e5 YI |
123 | static struct iosapic { |
124 | char __iomem *addr; /* base address of IOSAPIC */ | |
125 | unsigned int gsi_base; /* GSI base */ | |
126 | unsigned short num_rte; /* # of RTEs on this IOSAPIC */ | |
127 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ | |
128 | #ifdef CONFIG_NUMA | |
129 | unsigned short node; /* numa node association via pxm */ | |
130 | #endif | |
c1726d6f | 131 | spinlock_t lock; /* lock for indirect reg access */ |
c5e3f9e5 | 132 | } iosapic_lists[NR_IOSAPICS]; |
1da177e4 | 133 | |
24eeb568 | 134 | struct iosapic_rte_info { |
c5e3f9e5 | 135 | struct list_head rte_list; /* RTEs sharing the same vector */ |
24eeb568 KK |
136 | char rte_index; /* IOSAPIC RTE index */ |
137 | int refcnt; /* reference counter */ | |
138 | unsigned int flags; /* flags */ | |
c5e3f9e5 | 139 | struct iosapic *iosapic; |
24eeb568 KK |
140 | } ____cacheline_aligned; |
141 | ||
142 | static struct iosapic_intr_info { | |
46cba3dc ST |
143 | struct list_head rtes; /* RTEs using this vector (empty => |
144 | * not an IOSAPIC interrupt) */ | |
c4c376f7 | 145 | int count; /* # of registered RTEs */ |
46cba3dc ST |
146 | u32 low32; /* current value of low word of |
147 | * Redirection table entry */ | |
24eeb568 | 148 | unsigned int dest; /* destination CPU physical ID */ |
1da177e4 | 149 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
46cba3dc ST |
150 | unsigned char polarity: 1; /* interrupt polarity |
151 | * (see iosapic.h) */ | |
1da177e4 | 152 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
4bbdec7a | 153 | } iosapic_intr_info[NR_IRQS]; |
1da177e4 | 154 | |
0e888adc | 155 | static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */ |
1da177e4 | 156 | |
24eeb568 KK |
157 | static int iosapic_kmalloc_ok; |
158 | static LIST_HEAD(free_rte_list); | |
1da177e4 | 159 | |
c1726d6f YI |
160 | static inline void |
161 | iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) | |
162 | { | |
163 | unsigned long flags; | |
164 | ||
165 | spin_lock_irqsave(&iosapic->lock, flags); | |
166 | __iosapic_write(iosapic->addr, reg, val); | |
167 | spin_unlock_irqrestore(&iosapic->lock, flags); | |
168 | } | |
169 | ||
1da177e4 LT |
170 | /* |
171 | * Find an IOSAPIC associated with a GSI | |
172 | */ | |
173 | static inline int | |
174 | find_iosapic (unsigned int gsi) | |
175 | { | |
176 | int i; | |
177 | ||
0e888adc | 178 | for (i = 0; i < NR_IOSAPICS; i++) { |
46cba3dc ST |
179 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < |
180 | iosapic_lists[i].num_rte) | |
1da177e4 LT |
181 | return i; |
182 | } | |
183 | ||
184 | return -1; | |
185 | } | |
186 | ||
4bbdec7a | 187 | static inline int __gsi_to_irq(unsigned int gsi) |
1da177e4 | 188 | { |
4bbdec7a | 189 | int irq; |
1da177e4 | 190 | struct iosapic_intr_info *info; |
24eeb568 | 191 | struct iosapic_rte_info *rte; |
1da177e4 | 192 | |
4bbdec7a YI |
193 | for (irq = 0; irq < NR_IRQS; irq++) { |
194 | info = &iosapic_intr_info[irq]; | |
24eeb568 | 195 | list_for_each_entry(rte, &info->rtes, rte_list) |
c5e3f9e5 | 196 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
4bbdec7a YI |
197 | return irq; |
198 | } | |
1da177e4 LT |
199 | return -1; |
200 | } | |
201 | ||
1da177e4 LT |
202 | int |
203 | gsi_to_irq (unsigned int gsi) | |
204 | { | |
24eeb568 KK |
205 | unsigned long flags; |
206 | int irq; | |
4bbdec7a | 207 | |
24eeb568 | 208 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 209 | irq = __gsi_to_irq(gsi); |
24eeb568 | 210 | spin_unlock_irqrestore(&iosapic_lock, flags); |
24eeb568 KK |
211 | return irq; |
212 | } | |
213 | ||
4bbdec7a | 214 | static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi) |
24eeb568 KK |
215 | { |
216 | struct iosapic_rte_info *rte; | |
217 | ||
4bbdec7a | 218 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 219 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
24eeb568 KK |
220 | return rte; |
221 | return NULL; | |
1da177e4 LT |
222 | } |
223 | ||
224 | static void | |
4bbdec7a | 225 | set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) |
1da177e4 LT |
226 | { |
227 | unsigned long pol, trigger, dmode; | |
228 | u32 low32, high32; | |
1da177e4 LT |
229 | int rte_index; |
230 | char redir; | |
24eeb568 | 231 | struct iosapic_rte_info *rte; |
4bbdec7a | 232 | ia64_vector vector = irq_to_vector(irq); |
1da177e4 LT |
233 | |
234 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
235 | ||
4bbdec7a | 236 | rte = find_rte(irq, gsi); |
24eeb568 | 237 | if (!rte) |
1da177e4 LT |
238 | return; /* not an IOSAPIC interrupt */ |
239 | ||
24eeb568 | 240 | rte_index = rte->rte_index; |
4bbdec7a YI |
241 | pol = iosapic_intr_info[irq].polarity; |
242 | trigger = iosapic_intr_info[irq].trigger; | |
243 | dmode = iosapic_intr_info[irq].dmode; | |
1da177e4 LT |
244 | |
245 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
246 | ||
247 | #ifdef CONFIG_SMP | |
4bbdec7a | 248 | set_irq_affinity_info(irq, (int)(dest & 0xffff), redir); |
1da177e4 LT |
249 | #endif |
250 | ||
251 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
252 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
253 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
254 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
255 | vector); | |
256 | ||
257 | /* dest contains both id and eid */ | |
258 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
259 | ||
c1726d6f YI |
260 | iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
261 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
4bbdec7a YI |
262 | iosapic_intr_info[irq].low32 = low32; |
263 | iosapic_intr_info[irq].dest = dest; | |
1da177e4 LT |
264 | } |
265 | ||
266 | static void | |
46cba3dc | 267 | nop (unsigned int irq) |
1da177e4 LT |
268 | { |
269 | /* do nothing... */ | |
270 | } | |
271 | ||
a7956113 ZN |
272 | |
273 | #ifdef CONFIG_KEXEC | |
274 | void | |
275 | kexec_disable_iosapic(void) | |
276 | { | |
277 | struct iosapic_intr_info *info; | |
278 | struct iosapic_rte_info *rte; | |
4bbdec7a YI |
279 | ia64_vector vec; |
280 | int irq; | |
281 | ||
282 | for (irq = 0; irq < NR_IRQS; irq++) { | |
283 | info = &iosapic_intr_info[irq]; | |
284 | vec = irq_to_vector(irq); | |
a7956113 ZN |
285 | list_for_each_entry(rte, &info->rtes, |
286 | rte_list) { | |
c1726d6f | 287 | iosapic_write(rte->iosapic, |
a7956113 ZN |
288 | IOSAPIC_RTE_LOW(rte->rte_index), |
289 | IOSAPIC_MASK|vec); | |
c5e3f9e5 | 290 | iosapic_eoi(rte->iosapic->addr, vec); |
a7956113 ZN |
291 | } |
292 | } | |
293 | } | |
294 | #endif | |
295 | ||
1da177e4 LT |
296 | static void |
297 | mask_irq (unsigned int irq) | |
298 | { | |
1da177e4 LT |
299 | u32 low32; |
300 | int rte_index; | |
24eeb568 | 301 | struct iosapic_rte_info *rte; |
1da177e4 | 302 | |
c4c376f7 | 303 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
304 | return; /* not an IOSAPIC interrupt! */ |
305 | ||
e3a8f7b8 | 306 | /* set only the mask bit */ |
4bbdec7a YI |
307 | low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
308 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 309 | rte_index = rte->rte_index; |
c1726d6f | 310 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 311 | } |
1da177e4 LT |
312 | } |
313 | ||
314 | static void | |
315 | unmask_irq (unsigned int irq) | |
316 | { | |
1da177e4 LT |
317 | u32 low32; |
318 | int rte_index; | |
24eeb568 | 319 | struct iosapic_rte_info *rte; |
1da177e4 | 320 | |
c4c376f7 | 321 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
322 | return; /* not an IOSAPIC interrupt! */ |
323 | ||
4bbdec7a YI |
324 | low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK; |
325 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 326 | rte_index = rte->rte_index; |
c1726d6f | 327 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 328 | } |
1da177e4 LT |
329 | } |
330 | ||
331 | ||
332 | static void | |
333 | iosapic_set_affinity (unsigned int irq, cpumask_t mask) | |
334 | { | |
335 | #ifdef CONFIG_SMP | |
1da177e4 LT |
336 | u32 high32, low32; |
337 | int dest, rte_index; | |
1da177e4 | 338 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
24eeb568 | 339 | struct iosapic_rte_info *rte; |
c1726d6f | 340 | struct iosapic *iosapic; |
1da177e4 LT |
341 | |
342 | irq &= (~IA64_IRQ_REDIRECTED); | |
1da177e4 | 343 | |
cd378f18 | 344 | cpus_and(mask, mask, cpu_online_map); |
1da177e4 LT |
345 | if (cpus_empty(mask)) |
346 | return; | |
347 | ||
cd378f18 YI |
348 | if (reassign_irq_vector(irq, first_cpu(mask))) |
349 | return; | |
350 | ||
1da177e4 LT |
351 | dest = cpu_physical_id(first_cpu(mask)); |
352 | ||
c4c376f7 | 353 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
354 | return; /* not an IOSAPIC interrupt */ |
355 | ||
356 | set_irq_affinity_info(irq, dest, redir); | |
357 | ||
358 | /* dest contains both id and eid */ | |
359 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
360 | ||
4bbdec7a | 361 | low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); |
e3a8f7b8 YI |
362 | if (redir) |
363 | /* change delivery mode to lowest priority */ | |
364 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
365 | else | |
366 | /* change delivery mode to fixed */ | |
367 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
cd378f18 YI |
368 | low32 &= IOSAPIC_VECTOR_MASK; |
369 | low32 |= irq_to_vector(irq); | |
e3a8f7b8 | 370 | |
4bbdec7a YI |
371 | iosapic_intr_info[irq].low32 = low32; |
372 | iosapic_intr_info[irq].dest = dest; | |
373 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
c1726d6f | 374 | iosapic = rte->iosapic; |
e3a8f7b8 | 375 | rte_index = rte->rte_index; |
c1726d6f YI |
376 | iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
377 | iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
1da177e4 | 378 | } |
1da177e4 LT |
379 | #endif |
380 | } | |
381 | ||
382 | /* | |
383 | * Handlers for level-triggered interrupts. | |
384 | */ | |
385 | ||
386 | static unsigned int | |
387 | iosapic_startup_level_irq (unsigned int irq) | |
388 | { | |
389 | unmask_irq(irq); | |
390 | return 0; | |
391 | } | |
392 | ||
393 | static void | |
394 | iosapic_end_level_irq (unsigned int irq) | |
395 | { | |
396 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 397 | struct iosapic_rte_info *rte; |
cd378f18 YI |
398 | int do_unmask_irq = 0; |
399 | ||
400 | if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { | |
401 | do_unmask_irq = 1; | |
402 | mask_irq(irq); | |
403 | } | |
1da177e4 | 404 | |
4bbdec7a | 405 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 406 | iosapic_eoi(rte->iosapic->addr, vec); |
cd378f18 YI |
407 | |
408 | if (unlikely(do_unmask_irq)) { | |
409 | move_masked_irq(irq); | |
410 | unmask_irq(irq); | |
411 | } | |
1da177e4 LT |
412 | } |
413 | ||
414 | #define iosapic_shutdown_level_irq mask_irq | |
415 | #define iosapic_enable_level_irq unmask_irq | |
416 | #define iosapic_disable_level_irq mask_irq | |
417 | #define iosapic_ack_level_irq nop | |
418 | ||
9e004ebd | 419 | static struct irq_chip irq_type_iosapic_level = { |
06344db3 | 420 | .name = "IO-SAPIC-level", |
1da177e4 LT |
421 | .startup = iosapic_startup_level_irq, |
422 | .shutdown = iosapic_shutdown_level_irq, | |
423 | .enable = iosapic_enable_level_irq, | |
424 | .disable = iosapic_disable_level_irq, | |
425 | .ack = iosapic_ack_level_irq, | |
426 | .end = iosapic_end_level_irq, | |
e253eb0c KH |
427 | .mask = mask_irq, |
428 | .unmask = unmask_irq, | |
1da177e4 LT |
429 | .set_affinity = iosapic_set_affinity |
430 | }; | |
431 | ||
432 | /* | |
433 | * Handlers for edge-triggered interrupts. | |
434 | */ | |
435 | ||
436 | static unsigned int | |
437 | iosapic_startup_edge_irq (unsigned int irq) | |
438 | { | |
439 | unmask_irq(irq); | |
440 | /* | |
441 | * IOSAPIC simply drops interrupts pended while the | |
442 | * corresponding pin was masked, so we can't know if an | |
443 | * interrupt is pending already. Let's hope not... | |
444 | */ | |
445 | return 0; | |
446 | } | |
447 | ||
448 | static void | |
449 | iosapic_ack_edge_irq (unsigned int irq) | |
450 | { | |
a8553acd | 451 | irq_desc_t *idesc = irq_desc + irq; |
1da177e4 | 452 | |
41503def | 453 | move_native_irq(irq); |
1da177e4 LT |
454 | /* |
455 | * Once we have recorded IRQ_PENDING already, we can mask the | |
456 | * interrupt for real. This prevents IRQ storms from unhandled | |
457 | * devices. | |
458 | */ | |
46cba3dc ST |
459 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == |
460 | (IRQ_PENDING|IRQ_DISABLED)) | |
1da177e4 LT |
461 | mask_irq(irq); |
462 | } | |
463 | ||
464 | #define iosapic_enable_edge_irq unmask_irq | |
465 | #define iosapic_disable_edge_irq nop | |
466 | #define iosapic_end_edge_irq nop | |
467 | ||
9e004ebd | 468 | static struct irq_chip irq_type_iosapic_edge = { |
06344db3 | 469 | .name = "IO-SAPIC-edge", |
1da177e4 LT |
470 | .startup = iosapic_startup_edge_irq, |
471 | .shutdown = iosapic_disable_edge_irq, | |
472 | .enable = iosapic_enable_edge_irq, | |
473 | .disable = iosapic_disable_edge_irq, | |
474 | .ack = iosapic_ack_edge_irq, | |
475 | .end = iosapic_end_edge_irq, | |
e253eb0c KH |
476 | .mask = mask_irq, |
477 | .unmask = unmask_irq, | |
1da177e4 LT |
478 | .set_affinity = iosapic_set_affinity |
479 | }; | |
480 | ||
9e004ebd | 481 | static unsigned int |
1da177e4 LT |
482 | iosapic_version (char __iomem *addr) |
483 | { | |
484 | /* | |
485 | * IOSAPIC Version Register return 32 bit structure like: | |
486 | * { | |
487 | * unsigned int version : 8; | |
488 | * unsigned int reserved1 : 8; | |
489 | * unsigned int max_redir : 8; | |
490 | * unsigned int reserved2 : 8; | |
491 | * } | |
492 | */ | |
c1726d6f | 493 | return __iosapic_read(addr, IOSAPIC_VERSION); |
1da177e4 LT |
494 | } |
495 | ||
4bbdec7a | 496 | static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol) |
24eeb568 | 497 | { |
4bbdec7a | 498 | int i, irq = -ENOSPC, min_count = -1; |
24eeb568 KK |
499 | struct iosapic_intr_info *info; |
500 | ||
501 | /* | |
502 | * shared vectors for edge-triggered interrupts are not | |
503 | * supported yet | |
504 | */ | |
505 | if (trigger == IOSAPIC_EDGE) | |
40598cbe | 506 | return -EINVAL; |
24eeb568 | 507 | |
4bbdec7a | 508 | for (i = 0; i <= NR_IRQS; i++) { |
24eeb568 KK |
509 | info = &iosapic_intr_info[i]; |
510 | if (info->trigger == trigger && info->polarity == pol && | |
f8c087f3 YI |
511 | (info->dmode == IOSAPIC_FIXED || |
512 | info->dmode == IOSAPIC_LOWEST_PRIORITY) && | |
513 | can_request_irq(i, IRQF_SHARED)) { | |
24eeb568 | 514 | if (min_count == -1 || info->count < min_count) { |
4bbdec7a | 515 | irq = i; |
24eeb568 KK |
516 | min_count = info->count; |
517 | } | |
518 | } | |
519 | } | |
4bbdec7a | 520 | return irq; |
24eeb568 KK |
521 | } |
522 | ||
1da177e4 LT |
523 | /* |
524 | * if the given vector is already owned by other, | |
525 | * assign a new vector for the other and make the vector available | |
526 | */ | |
527 | static void __init | |
4bbdec7a | 528 | iosapic_reassign_vector (int irq) |
1da177e4 | 529 | { |
4bbdec7a | 530 | int new_irq; |
1da177e4 | 531 | |
c4c376f7 | 532 | if (iosapic_intr_info[irq].count) { |
4bbdec7a YI |
533 | new_irq = create_irq(); |
534 | if (new_irq < 0) | |
3b5cc090 | 535 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); |
46cba3dc | 536 | printk(KERN_INFO "Reassigning vector %d to %d\n", |
4bbdec7a YI |
537 | irq_to_vector(irq), irq_to_vector(new_irq)); |
538 | memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq], | |
1da177e4 | 539 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
540 | INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes); |
541 | list_move(iosapic_intr_info[irq].rtes.next, | |
542 | &iosapic_intr_info[new_irq].rtes); | |
543 | memset(&iosapic_intr_info[irq], 0, | |
46cba3dc | 544 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
545 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; |
546 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); | |
1da177e4 LT |
547 | } |
548 | } | |
549 | ||
056e6d89 | 550 | static struct iosapic_rte_info * __init_refok iosapic_alloc_rte (void) |
24eeb568 KK |
551 | { |
552 | int i; | |
553 | struct iosapic_rte_info *rte; | |
554 | int preallocated = 0; | |
555 | ||
556 | if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) { | |
46cba3dc ST |
557 | rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * |
558 | NR_PREALLOCATE_RTE_ENTRIES); | |
24eeb568 KK |
559 | if (!rte) |
560 | return NULL; | |
561 | for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++) | |
562 | list_add(&rte->rte_list, &free_rte_list); | |
563 | } | |
564 | ||
565 | if (!list_empty(&free_rte_list)) { | |
46cba3dc ST |
566 | rte = list_entry(free_rte_list.next, struct iosapic_rte_info, |
567 | rte_list); | |
24eeb568 KK |
568 | list_del(&rte->rte_list); |
569 | preallocated++; | |
570 | } else { | |
571 | rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC); | |
572 | if (!rte) | |
573 | return NULL; | |
574 | } | |
575 | ||
576 | memset(rte, 0, sizeof(struct iosapic_rte_info)); | |
577 | if (preallocated) | |
578 | rte->flags |= RTE_PREALLOCATED; | |
579 | ||
580 | return rte; | |
581 | } | |
582 | ||
4bbdec7a | 583 | static inline int irq_is_shared (int irq) |
24eeb568 | 584 | { |
4bbdec7a | 585 | return (iosapic_intr_info[irq].count > 1); |
24eeb568 KK |
586 | } |
587 | ||
14454a1b | 588 | static int |
4bbdec7a | 589 | register_intr (unsigned int gsi, int irq, unsigned char delivery, |
1da177e4 LT |
590 | unsigned long polarity, unsigned long trigger) |
591 | { | |
592 | irq_desc_t *idesc; | |
593 | struct hw_interrupt_type *irq_type; | |
1da177e4 | 594 | int index; |
24eeb568 | 595 | struct iosapic_rte_info *rte; |
1da177e4 LT |
596 | |
597 | index = find_iosapic(gsi); | |
598 | if (index < 0) { | |
46cba3dc ST |
599 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
600 | __FUNCTION__, gsi); | |
14454a1b | 601 | return -ENODEV; |
1da177e4 LT |
602 | } |
603 | ||
4bbdec7a | 604 | rte = find_rte(irq, gsi); |
24eeb568 KK |
605 | if (!rte) { |
606 | rte = iosapic_alloc_rte(); | |
607 | if (!rte) { | |
46cba3dc ST |
608 | printk(KERN_WARNING "%s: cannot allocate memory\n", |
609 | __FUNCTION__); | |
14454a1b | 610 | return -ENOMEM; |
24eeb568 KK |
611 | } |
612 | ||
c5e3f9e5 YI |
613 | rte->iosapic = &iosapic_lists[index]; |
614 | rte->rte_index = gsi - rte->iosapic->gsi_base; | |
24eeb568 | 615 | rte->refcnt++; |
4bbdec7a YI |
616 | list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes); |
617 | iosapic_intr_info[irq].count++; | |
0e888adc | 618 | iosapic_lists[index].rtes_inuse++; |
24eeb568 | 619 | } |
e1b30a39 | 620 | else if (rte->refcnt == NO_REF_RTE) { |
4bbdec7a | 621 | struct iosapic_intr_info *info = &iosapic_intr_info[irq]; |
e1b30a39 YI |
622 | if (info->count > 0 && |
623 | (info->trigger != trigger || info->polarity != polarity)){ | |
46cba3dc ST |
624 | printk (KERN_WARNING |
625 | "%s: cannot override the interrupt\n", | |
626 | __FUNCTION__); | |
14454a1b | 627 | return -EINVAL; |
24eeb568 | 628 | } |
e1b30a39 YI |
629 | rte->refcnt++; |
630 | iosapic_intr_info[irq].count++; | |
631 | iosapic_lists[index].rtes_inuse++; | |
24eeb568 KK |
632 | } |
633 | ||
4bbdec7a YI |
634 | iosapic_intr_info[irq].polarity = polarity; |
635 | iosapic_intr_info[irq].dmode = delivery; | |
636 | iosapic_intr_info[irq].trigger = trigger; | |
1da177e4 LT |
637 | |
638 | if (trigger == IOSAPIC_EDGE) | |
639 | irq_type = &irq_type_iosapic_edge; | |
640 | else | |
641 | irq_type = &irq_type_iosapic_level; | |
642 | ||
4bbdec7a | 643 | idesc = irq_desc + irq; |
d1bef4ed IM |
644 | if (idesc->chip != irq_type) { |
645 | if (idesc->chip != &no_irq_type) | |
46cba3dc ST |
646 | printk(KERN_WARNING |
647 | "%s: changing vector %d from %s to %s\n", | |
4bbdec7a | 648 | __FUNCTION__, irq_to_vector(irq), |
351a5839 | 649 | idesc->chip->name, irq_type->name); |
d1bef4ed | 650 | idesc->chip = irq_type; |
1da177e4 | 651 | } |
14454a1b | 652 | return 0; |
1da177e4 LT |
653 | } |
654 | ||
655 | static unsigned int | |
4bbdec7a | 656 | get_target_cpu (unsigned int gsi, int irq) |
1da177e4 LT |
657 | { |
658 | #ifdef CONFIG_SMP | |
659 | static int cpu = -1; | |
ff741906 | 660 | extern int cpe_vector; |
4994be1b | 661 | cpumask_t domain = irq_to_domain(irq); |
1da177e4 | 662 | |
24eeb568 KK |
663 | /* |
664 | * In case of vector shared by multiple RTEs, all RTEs that | |
665 | * share the vector need to use the same destination CPU. | |
666 | */ | |
c4c376f7 | 667 | if (iosapic_intr_info[irq].count) |
4bbdec7a | 668 | return iosapic_intr_info[irq].dest; |
24eeb568 | 669 | |
1da177e4 LT |
670 | /* |
671 | * If the platform supports redirection via XTP, let it | |
672 | * distribute interrupts. | |
673 | */ | |
674 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
675 | return cpu_physical_id(smp_processor_id()); | |
676 | ||
677 | /* | |
678 | * Some interrupts (ACPI SCI, for instance) are registered | |
679 | * before the BSP is marked as online. | |
680 | */ | |
681 | if (!cpu_online(smp_processor_id())) | |
682 | return cpu_physical_id(smp_processor_id()); | |
683 | ||
ff741906 | 684 | #ifdef CONFIG_ACPI |
4bbdec7a | 685 | if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR) |
b88e9265 | 686 | return get_cpei_target_cpu(); |
ff741906 AR |
687 | #endif |
688 | ||
1da177e4 LT |
689 | #ifdef CONFIG_NUMA |
690 | { | |
691 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
692 | cpumask_t cpu_mask; | |
693 | ||
694 | iosapic_index = find_iosapic(gsi); | |
695 | if (iosapic_index < 0 || | |
696 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
697 | goto skip_numa_setup; | |
698 | ||
699 | cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node); | |
4994be1b | 700 | cpus_and(cpu_mask, cpu_mask, domain); |
1da177e4 LT |
701 | for_each_cpu_mask(numa_cpu, cpu_mask) { |
702 | if (!cpu_online(numa_cpu)) | |
703 | cpu_clear(numa_cpu, cpu_mask); | |
704 | } | |
705 | ||
706 | num_cpus = cpus_weight(cpu_mask); | |
707 | ||
708 | if (!num_cpus) | |
709 | goto skip_numa_setup; | |
710 | ||
4bbdec7a YI |
711 | /* Use irq assignment to distribute across cpus in node */ |
712 | cpu_index = irq % num_cpus; | |
1da177e4 LT |
713 | |
714 | for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++) | |
715 | numa_cpu = next_cpu(numa_cpu, cpu_mask); | |
716 | ||
717 | if (numa_cpu != NR_CPUS) | |
718 | return cpu_physical_id(numa_cpu); | |
719 | } | |
720 | skip_numa_setup: | |
721 | #endif | |
722 | /* | |
723 | * Otherwise, round-robin interrupt vectors across all the | |
724 | * processors. (It'd be nice if we could be smarter in the | |
725 | * case of NUMA.) | |
726 | */ | |
727 | do { | |
728 | if (++cpu >= NR_CPUS) | |
729 | cpu = 0; | |
4994be1b | 730 | } while (!cpu_online(cpu) || !cpu_isset(cpu, domain)); |
1da177e4 LT |
731 | |
732 | return cpu_physical_id(cpu); | |
46cba3dc | 733 | #else /* CONFIG_SMP */ |
1da177e4 LT |
734 | return cpu_physical_id(smp_processor_id()); |
735 | #endif | |
736 | } | |
737 | ||
c9d059de KK |
738 | static inline unsigned char choose_dmode(void) |
739 | { | |
740 | #ifdef CONFIG_SMP | |
741 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
742 | return IOSAPIC_LOWEST_PRIORITY; | |
743 | #endif | |
744 | return IOSAPIC_FIXED; | |
745 | } | |
746 | ||
1da177e4 LT |
747 | /* |
748 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
749 | * methods. This provides an interface to register those interrupts and | |
750 | * program the IOSAPIC RTE. | |
751 | */ | |
752 | int | |
753 | iosapic_register_intr (unsigned int gsi, | |
754 | unsigned long polarity, unsigned long trigger) | |
755 | { | |
4bbdec7a | 756 | int irq, mask = 1, err; |
1da177e4 LT |
757 | unsigned int dest; |
758 | unsigned long flags; | |
24eeb568 KK |
759 | struct iosapic_rte_info *rte; |
760 | u32 low32; | |
c9d059de | 761 | unsigned char dmode; |
40598cbe | 762 | |
1da177e4 LT |
763 | /* |
764 | * If this GSI has already been registered (i.e., it's a | |
765 | * shared interrupt, or we lost a race to register it), | |
766 | * don't touch the RTE. | |
767 | */ | |
768 | spin_lock_irqsave(&iosapic_lock, flags); | |
4bbdec7a YI |
769 | irq = __gsi_to_irq(gsi); |
770 | if (irq > 0) { | |
771 | rte = find_rte(irq, gsi); | |
e1b30a39 YI |
772 | if(iosapic_intr_info[irq].count == 0) { |
773 | assign_irq_vector(irq); | |
774 | dynamic_irq_init(irq); | |
775 | } else if (rte->refcnt != NO_REF_RTE) { | |
776 | rte->refcnt++; | |
777 | goto unlock_iosapic_lock; | |
778 | } | |
779 | } else | |
780 | irq = create_irq(); | |
24eeb568 KK |
781 | |
782 | /* If vector is running out, we try to find a sharable vector */ | |
eb21ab24 | 783 | if (irq < 0) { |
4bbdec7a YI |
784 | irq = iosapic_find_sharable_irq(trigger, polarity); |
785 | if (irq < 0) | |
40598cbe | 786 | goto unlock_iosapic_lock; |
4bbdec7a | 787 | } |
1da177e4 | 788 | |
4bbdec7a YI |
789 | spin_lock(&irq_desc[irq].lock); |
790 | dest = get_target_cpu(gsi, irq); | |
c9d059de KK |
791 | dmode = choose_dmode(); |
792 | err = register_intr(gsi, irq, dmode, polarity, trigger); | |
e3a8f7b8 | 793 | if (err < 0) { |
224685c0 | 794 | spin_unlock(&irq_desc[irq].lock); |
4bbdec7a | 795 | irq = err; |
224685c0 | 796 | goto unlock_iosapic_lock; |
1da177e4 | 797 | } |
e3a8f7b8 YI |
798 | |
799 | /* | |
800 | * If the vector is shared and already unmasked for other | |
801 | * interrupt sources, don't mask it. | |
802 | */ | |
4bbdec7a YI |
803 | low32 = iosapic_intr_info[irq].low32; |
804 | if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK)) | |
e3a8f7b8 | 805 | mask = 0; |
4bbdec7a | 806 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
807 | |
808 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
809 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
810 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 811 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
224685c0 | 812 | |
4bbdec7a | 813 | spin_unlock(&irq_desc[irq].lock); |
40598cbe YI |
814 | unlock_iosapic_lock: |
815 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
4bbdec7a | 816 | return irq; |
1da177e4 LT |
817 | } |
818 | ||
1da177e4 LT |
819 | void |
820 | iosapic_unregister_intr (unsigned int gsi) | |
821 | { | |
822 | unsigned long flags; | |
4bbdec7a | 823 | int irq, index; |
1da177e4 | 824 | irq_desc_t *idesc; |
24eeb568 | 825 | u32 low32; |
1da177e4 | 826 | unsigned long trigger, polarity; |
24eeb568 KK |
827 | unsigned int dest; |
828 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
829 | |
830 | /* | |
831 | * If the irq associated with the gsi is not found, | |
832 | * iosapic_unregister_intr() is unbalanced. We need to check | |
833 | * this again after getting locks. | |
834 | */ | |
835 | irq = gsi_to_irq(gsi); | |
836 | if (irq < 0) { | |
46cba3dc ST |
837 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
838 | gsi); | |
1da177e4 LT |
839 | WARN_ON(1); |
840 | return; | |
841 | } | |
1da177e4 | 842 | |
40598cbe | 843 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 844 | if ((rte = find_rte(irq, gsi)) == NULL) { |
e3a8f7b8 YI |
845 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
846 | gsi); | |
847 | WARN_ON(1); | |
848 | goto out; | |
849 | } | |
1da177e4 | 850 | |
e3a8f7b8 YI |
851 | if (--rte->refcnt > 0) |
852 | goto out; | |
1da177e4 | 853 | |
40598cbe | 854 | idesc = irq_desc + irq; |
e1b30a39 | 855 | rte->refcnt = NO_REF_RTE; |
40598cbe | 856 | |
e3a8f7b8 | 857 | /* Mask the interrupt */ |
4bbdec7a | 858 | low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK; |
c1726d6f | 859 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32); |
1da177e4 | 860 | |
4bbdec7a | 861 | iosapic_intr_info[irq].count--; |
e3a8f7b8 YI |
862 | index = find_iosapic(gsi); |
863 | iosapic_lists[index].rtes_inuse--; | |
864 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
24eeb568 | 865 | |
4bbdec7a YI |
866 | trigger = iosapic_intr_info[irq].trigger; |
867 | polarity = iosapic_intr_info[irq].polarity; | |
868 | dest = iosapic_intr_info[irq].dest; | |
e3a8f7b8 YI |
869 | printk(KERN_INFO |
870 | "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n", | |
871 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
872 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 873 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
24eeb568 | 874 | |
e1b30a39 | 875 | if (iosapic_intr_info[irq].count == 0) { |
451fe00c | 876 | #ifdef CONFIG_SMP |
e3a8f7b8 YI |
877 | /* Clear affinity */ |
878 | cpus_setall(idesc->affinity); | |
451fe00c | 879 | #endif |
e3a8f7b8 | 880 | /* Clear the interrupt information */ |
e1b30a39 YI |
881 | iosapic_intr_info[irq].dest = 0; |
882 | iosapic_intr_info[irq].dmode = 0; | |
883 | iosapic_intr_info[irq].polarity = 0; | |
884 | iosapic_intr_info[irq].trigger = 0; | |
4bbdec7a | 885 | iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
1da177e4 | 886 | |
e1b30a39 YI |
887 | /* Destroy and reserve IRQ */ |
888 | destroy_and_reserve_irq(irq); | |
1da177e4 | 889 | } |
24eeb568 | 890 | out: |
40598cbe | 891 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 | 892 | } |
1da177e4 LT |
893 | |
894 | /* | |
895 | * ACPI calls this when it finds an entry for a platform interrupt. | |
1da177e4 LT |
896 | */ |
897 | int __init | |
898 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
899 | int iosapic_vector, u16 eid, u16 id, | |
900 | unsigned long polarity, unsigned long trigger) | |
901 | { | |
902 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
903 | unsigned char delivery; | |
eb21ab24 | 904 | int irq, vector, mask = 0; |
1da177e4 LT |
905 | unsigned int dest = ((id << 8) | eid) & 0xffff; |
906 | ||
907 | switch (int_type) { | |
908 | case ACPI_INTERRUPT_PMI: | |
e1b30a39 | 909 | irq = vector = iosapic_vector; |
4994be1b | 910 | bind_irq_vector(irq, vector, CPU_MASK_ALL); |
1da177e4 LT |
911 | /* |
912 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
913 | * we need to make sure the vector is available | |
914 | */ | |
4bbdec7a | 915 | iosapic_reassign_vector(irq); |
1da177e4 LT |
916 | delivery = IOSAPIC_PMI; |
917 | break; | |
918 | case ACPI_INTERRUPT_INIT: | |
eb21ab24 YI |
919 | irq = create_irq(); |
920 | if (irq < 0) | |
3b5cc090 | 921 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); |
eb21ab24 | 922 | vector = irq_to_vector(irq); |
1da177e4 LT |
923 | delivery = IOSAPIC_INIT; |
924 | break; | |
925 | case ACPI_INTERRUPT_CPEI: | |
e1b30a39 | 926 | irq = vector = IA64_CPE_VECTOR; |
4994be1b | 927 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
1da177e4 LT |
928 | delivery = IOSAPIC_LOWEST_PRIORITY; |
929 | mask = 1; | |
930 | break; | |
931 | default: | |
46cba3dc ST |
932 | printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__, |
933 | int_type); | |
1da177e4 LT |
934 | return -1; |
935 | } | |
936 | ||
4bbdec7a | 937 | register_intr(gsi, irq, delivery, polarity, trigger); |
1da177e4 | 938 | |
46cba3dc ST |
939 | printk(KERN_INFO |
940 | "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
941 | " vector %d\n", | |
1da177e4 LT |
942 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
943 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
944 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
945 | cpu_logical_id(dest), dest, vector); | |
946 | ||
4bbdec7a | 947 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
948 | return vector; |
949 | } | |
950 | ||
1da177e4 LT |
951 | /* |
952 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
1da177e4 | 953 | */ |
0f7ac29e | 954 | void __devinit |
1da177e4 LT |
955 | iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, |
956 | unsigned long polarity, | |
957 | unsigned long trigger) | |
958 | { | |
4bbdec7a | 959 | int vector, irq; |
1da177e4 | 960 | unsigned int dest = cpu_physical_id(smp_processor_id()); |
c9d059de | 961 | unsigned char dmode; |
1da177e4 | 962 | |
e1b30a39 | 963 | irq = vector = isa_irq_to_vector(isa_irq); |
4994be1b | 964 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
c9d059de KK |
965 | dmode = choose_dmode(); |
966 | register_intr(gsi, irq, dmode, polarity, trigger); | |
1da177e4 LT |
967 | |
968 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
969 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
970 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
971 | cpu_logical_id(dest), dest, vector); | |
972 | ||
4bbdec7a | 973 | set_rte(gsi, irq, dest, 1); |
1da177e4 LT |
974 | } |
975 | ||
976 | void __init | |
977 | iosapic_system_init (int system_pcat_compat) | |
978 | { | |
4bbdec7a | 979 | int irq; |
1da177e4 | 980 | |
4bbdec7a YI |
981 | for (irq = 0; irq < NR_IRQS; ++irq) { |
982 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; | |
46cba3dc | 983 | /* mark as unused */ |
4bbdec7a | 984 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); |
e1b30a39 YI |
985 | |
986 | iosapic_intr_info[irq].count = 0; | |
24eeb568 | 987 | } |
1da177e4 LT |
988 | |
989 | pcat_compat = system_pcat_compat; | |
990 | if (pcat_compat) { | |
991 | /* | |
46cba3dc ST |
992 | * Disable the compatibility mode interrupts (8259 style), |
993 | * needs IN/OUT support enabled. | |
1da177e4 | 994 | */ |
46cba3dc ST |
995 | printk(KERN_INFO |
996 | "%s: Disabling PC-AT compatible 8259 interrupts\n", | |
997 | __FUNCTION__); | |
1da177e4 LT |
998 | outb(0xff, 0xA1); |
999 | outb(0xff, 0x21); | |
1000 | } | |
1001 | } | |
1002 | ||
0e888adc KK |
1003 | static inline int |
1004 | iosapic_alloc (void) | |
1005 | { | |
1006 | int index; | |
1007 | ||
1008 | for (index = 0; index < NR_IOSAPICS; index++) | |
1009 | if (!iosapic_lists[index].addr) | |
1010 | return index; | |
1011 | ||
1012 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__); | |
1013 | return -1; | |
1014 | } | |
1015 | ||
1016 | static inline void | |
1017 | iosapic_free (int index) | |
1018 | { | |
1019 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
1020 | } | |
1021 | ||
1022 | static inline int | |
1023 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
1024 | { | |
1025 | int index; | |
1026 | unsigned int gsi_end, base, end; | |
1027 | ||
1028 | /* check gsi range */ | |
1029 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
1030 | for (index = 0; index < NR_IOSAPICS; index++) { | |
1031 | if (!iosapic_lists[index].addr) | |
1032 | continue; | |
1033 | ||
1034 | base = iosapic_lists[index].gsi_base; | |
1035 | end = base + iosapic_lists[index].num_rte - 1; | |
1036 | ||
e6d1ba5c | 1037 | if (gsi_end < base || end < gsi_base) |
0e888adc KK |
1038 | continue; /* OK */ |
1039 | ||
1040 | return -EBUSY; | |
1041 | } | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | int __devinit | |
1da177e4 LT |
1046 | iosapic_init (unsigned long phys_addr, unsigned int gsi_base) |
1047 | { | |
0e888adc | 1048 | int num_rte, err, index; |
1da177e4 LT |
1049 | unsigned int isa_irq, ver; |
1050 | char __iomem *addr; | |
0e888adc KK |
1051 | unsigned long flags; |
1052 | ||
1053 | spin_lock_irqsave(&iosapic_lock, flags); | |
c1726d6f YI |
1054 | index = find_iosapic(gsi_base); |
1055 | if (index >= 0) { | |
1056 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1057 | return -EBUSY; | |
1058 | } | |
1059 | ||
e3a8f7b8 YI |
1060 | addr = ioremap(phys_addr, 0); |
1061 | ver = iosapic_version(addr); | |
e3a8f7b8 YI |
1062 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1063 | iounmap(addr); | |
1064 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1065 | return err; | |
1066 | } | |
1da177e4 | 1067 | |
e3a8f7b8 YI |
1068 | /* |
1069 | * The MAX_REDIR register holds the highest input pin number | |
1070 | * (starting from 0). We add 1 so that we can use it for | |
1071 | * number of pins (= RTEs) | |
1072 | */ | |
1073 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1074 | |
e3a8f7b8 YI |
1075 | index = iosapic_alloc(); |
1076 | iosapic_lists[index].addr = addr; | |
1077 | iosapic_lists[index].gsi_base = gsi_base; | |
1078 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1079 | #ifdef CONFIG_NUMA |
e3a8f7b8 | 1080 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1081 | #endif |
c1726d6f | 1082 | spin_lock_init(&iosapic_lists[index].lock); |
0e888adc | 1083 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 LT |
1084 | |
1085 | if ((gsi_base == 0) && pcat_compat) { | |
1086 | /* | |
46cba3dc ST |
1087 | * Map the legacy ISA devices into the IOSAPIC data. Some of |
1088 | * these may get reprogrammed later on with data from the ACPI | |
1089 | * Interrupt Source Override table. | |
1da177e4 LT |
1090 | */ |
1091 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
46cba3dc ST |
1092 | iosapic_override_isa_irq(isa_irq, isa_irq, |
1093 | IOSAPIC_POL_HIGH, | |
1094 | IOSAPIC_EDGE); | |
1da177e4 | 1095 | } |
0e888adc KK |
1096 | return 0; |
1097 | } | |
1098 | ||
1099 | #ifdef CONFIG_HOTPLUG | |
1100 | int | |
1101 | iosapic_remove (unsigned int gsi_base) | |
1102 | { | |
1103 | int index, err = 0; | |
1104 | unsigned long flags; | |
1105 | ||
1106 | spin_lock_irqsave(&iosapic_lock, flags); | |
e3a8f7b8 YI |
1107 | index = find_iosapic(gsi_base); |
1108 | if (index < 0) { | |
1109 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
1110 | __FUNCTION__, gsi_base); | |
1111 | goto out; | |
1112 | } | |
0e888adc | 1113 | |
e3a8f7b8 YI |
1114 | if (iosapic_lists[index].rtes_inuse) { |
1115 | err = -EBUSY; | |
1116 | printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n", | |
1117 | __FUNCTION__, gsi_base); | |
1118 | goto out; | |
0e888adc | 1119 | } |
e3a8f7b8 YI |
1120 | |
1121 | iounmap(iosapic_lists[index].addr); | |
1122 | iosapic_free(index); | |
0e888adc KK |
1123 | out: |
1124 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1125 | return err; | |
1da177e4 | 1126 | } |
0e888adc | 1127 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 LT |
1128 | |
1129 | #ifdef CONFIG_NUMA | |
0e888adc | 1130 | void __devinit |
1da177e4 LT |
1131 | map_iosapic_to_node(unsigned int gsi_base, int node) |
1132 | { | |
1133 | int index; | |
1134 | ||
1135 | index = find_iosapic(gsi_base); | |
1136 | if (index < 0) { | |
1137 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
1138 | __FUNCTION__, gsi_base); | |
1139 | return; | |
1140 | } | |
1141 | iosapic_lists[index].node = node; | |
1142 | return; | |
1143 | } | |
1144 | #endif | |
24eeb568 KK |
1145 | |
1146 | static int __init iosapic_enable_kmalloc (void) | |
1147 | { | |
1148 | iosapic_kmalloc_ok = 1; | |
1149 | return 0; | |
1150 | } | |
1151 | core_initcall (iosapic_enable_kmalloc); |