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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/config.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/kernel.h> | |
40 | ||
41 | #include <linux/mm.h> | |
42 | #include <linux/sched.h> | |
43 | #include <linux/kernel_stat.h> | |
44 | #include <linux/smp_lock.h> | |
1da177e4 | 45 | #include <linux/bootmem.h> |
f3705136 ZM |
46 | #include <linux/notifier.h> |
47 | #include <linux/cpu.h> | |
48 | #include <linux/percpu.h> | |
1da177e4 LT |
49 | |
50 | #include <linux/delay.h> | |
51 | #include <linux/mc146818rtc.h> | |
52 | #include <asm/tlbflush.h> | |
53 | #include <asm/desc.h> | |
54 | #include <asm/arch_hooks.h> | |
55 | ||
56 | #include <mach_apic.h> | |
57 | #include <mach_wakecpu.h> | |
58 | #include <smpboot_hooks.h> | |
59 | ||
60 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 61 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
129f6946 AD |
65 | #ifdef CONFIG_X86_HT |
66 | EXPORT_SYMBOL(smp_num_siblings); | |
67 | #endif | |
d720803a LS |
68 | |
69 | /* Package ID of each logical CPU */ | |
6c036527 | 70 | int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID}; |
d720803a LS |
71 | |
72 | /* Core ID of each logical CPU */ | |
6c036527 | 73 | int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID}; |
1da177e4 | 74 | |
6c036527 | 75 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
76 | EXPORT_SYMBOL(cpu_sibling_map); |
77 | ||
6c036527 | 78 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
79 | EXPORT_SYMBOL(cpu_core_map); |
80 | ||
1da177e4 | 81 | /* bitmap of online cpus */ |
6c036527 | 82 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 83 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
84 | |
85 | cpumask_t cpu_callin_map; | |
86 | cpumask_t cpu_callout_map; | |
129f6946 | 87 | EXPORT_SYMBOL(cpu_callout_map); |
9f40a72a NP |
88 | #ifdef CONFIG_HOTPLUG_CPU |
89 | cpumask_t cpu_possible_map = CPU_MASK_ALL; | |
90 | #else | |
4ad8d383 | 91 | cpumask_t cpu_possible_map; |
9f40a72a | 92 | #endif |
4ad8d383 | 93 | EXPORT_SYMBOL(cpu_possible_map); |
1da177e4 LT |
94 | static cpumask_t smp_commenced_mask; |
95 | ||
e1367daf LS |
96 | /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there |
97 | * is no way to resync one AP against BP. TBD: for prescott and above, we | |
98 | * should use IA64's algorithm | |
99 | */ | |
100 | static int __devinitdata tsc_sync_disabled; | |
101 | ||
1da177e4 LT |
102 | /* Per CPU bogomips and other parameters */ |
103 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 104 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 105 | |
6c036527 | 106 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
107 | { [0 ... NR_CPUS-1] = 0xff }; |
108 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
109 | ||
110 | /* | |
111 | * Trampoline 80x86 program as an array. | |
112 | */ | |
113 | ||
114 | extern unsigned char trampoline_data []; | |
115 | extern unsigned char trampoline_end []; | |
116 | static unsigned char *trampoline_base; | |
117 | static int trampoline_exec; | |
118 | ||
119 | static void map_cpu_to_logical_apicid(void); | |
120 | ||
f3705136 ZM |
121 | /* State of each CPU. */ |
122 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
123 | ||
1da177e4 LT |
124 | /* |
125 | * Currently trivial. Write the real->protected mode | |
126 | * bootstrap into the page concerned. The caller | |
127 | * has made sure it's suitably aligned. | |
128 | */ | |
129 | ||
0bb3184d | 130 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
131 | { |
132 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
133 | return virt_to_phys(trampoline_base); | |
134 | } | |
135 | ||
136 | /* | |
137 | * We are called very early to get the low memory for the | |
138 | * SMP bootup trampoline page. | |
139 | */ | |
140 | void __init smp_alloc_memory(void) | |
141 | { | |
142 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
143 | /* | |
144 | * Has to be in very low memory so we can execute | |
145 | * real-mode AP code. | |
146 | */ | |
147 | if (__pa(trampoline_base) >= 0x9F000) | |
148 | BUG(); | |
149 | /* | |
150 | * Make the SMP trampoline executable: | |
151 | */ | |
152 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
153 | } | |
154 | ||
155 | /* | |
156 | * The bootstrap kernel entry code has set these up. Save them for | |
157 | * a given CPU | |
158 | */ | |
159 | ||
0bb3184d | 160 | static void __devinit smp_store_cpu_info(int id) |
1da177e4 LT |
161 | { |
162 | struct cpuinfo_x86 *c = cpu_data + id; | |
163 | ||
164 | *c = boot_cpu_data; | |
165 | if (id!=0) | |
166 | identify_cpu(c); | |
167 | /* | |
168 | * Mask B, Pentium, but not Pentium MMX | |
169 | */ | |
170 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
171 | c->x86 == 5 && | |
172 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
173 | c->x86_model <= 3) | |
174 | /* | |
175 | * Remember we have B step Pentia with bugs | |
176 | */ | |
177 | smp_b_stepping = 1; | |
178 | ||
179 | /* | |
180 | * Certain Athlons might work (for various values of 'work') in SMP | |
181 | * but they are not certified as MP capable. | |
182 | */ | |
183 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
184 | ||
185 | /* Athlon 660/661 is valid. */ | |
186 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
187 | goto valid_k7; | |
188 | ||
189 | /* Duron 670 is valid */ | |
190 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
191 | goto valid_k7; | |
192 | ||
193 | /* | |
194 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
195 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
196 | * have the MP bit set. | |
197 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
198 | */ | |
199 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
200 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
201 | (c->x86_model> 7)) | |
202 | if (cpu_has_mp) | |
203 | goto valid_k7; | |
204 | ||
205 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 206 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
207 | } |
208 | ||
209 | valid_k7: | |
210 | ; | |
211 | } | |
212 | ||
213 | /* | |
214 | * TSC synchronization. | |
215 | * | |
216 | * We first check whether all CPUs have their TSC's synchronized, | |
217 | * then we print a warning if not, and always resync. | |
218 | */ | |
219 | ||
220 | static atomic_t tsc_start_flag = ATOMIC_INIT(0); | |
221 | static atomic_t tsc_count_start = ATOMIC_INIT(0); | |
222 | static atomic_t tsc_count_stop = ATOMIC_INIT(0); | |
223 | static unsigned long long tsc_values[NR_CPUS]; | |
224 | ||
225 | #define NR_LOOPS 5 | |
226 | ||
227 | static void __init synchronize_tsc_bp (void) | |
228 | { | |
229 | int i; | |
230 | unsigned long long t0; | |
231 | unsigned long long sum, avg; | |
232 | long long delta; | |
a3a255e7 | 233 | unsigned int one_usec; |
1da177e4 LT |
234 | int buggy = 0; |
235 | ||
236 | printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus()); | |
237 | ||
238 | /* convert from kcyc/sec to cyc/usec */ | |
239 | one_usec = cpu_khz / 1000; | |
240 | ||
241 | atomic_set(&tsc_start_flag, 1); | |
242 | wmb(); | |
243 | ||
244 | /* | |
245 | * We loop a few times to get a primed instruction cache, | |
246 | * then the last pass is more or less synchronized and | |
247 | * the BP and APs set their cycle counters to zero all at | |
248 | * once. This reduces the chance of having random offsets | |
249 | * between the processors, and guarantees that the maximum | |
250 | * delay between the cycle counters is never bigger than | |
251 | * the latency of information-passing (cachelines) between | |
252 | * two CPUs. | |
253 | */ | |
254 | for (i = 0; i < NR_LOOPS; i++) { | |
255 | /* | |
256 | * all APs synchronize but they loop on '== num_cpus' | |
257 | */ | |
258 | while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) | |
259 | mb(); | |
260 | atomic_set(&tsc_count_stop, 0); | |
261 | wmb(); | |
262 | /* | |
263 | * this lets the APs save their current TSC: | |
264 | */ | |
265 | atomic_inc(&tsc_count_start); | |
266 | ||
267 | rdtscll(tsc_values[smp_processor_id()]); | |
268 | /* | |
269 | * We clear the TSC in the last loop: | |
270 | */ | |
271 | if (i == NR_LOOPS-1) | |
272 | write_tsc(0, 0); | |
273 | ||
274 | /* | |
275 | * Wait for all APs to leave the synchronization point: | |
276 | */ | |
277 | while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) | |
278 | mb(); | |
279 | atomic_set(&tsc_count_start, 0); | |
280 | wmb(); | |
281 | atomic_inc(&tsc_count_stop); | |
282 | } | |
283 | ||
284 | sum = 0; | |
285 | for (i = 0; i < NR_CPUS; i++) { | |
286 | if (cpu_isset(i, cpu_callout_map)) { | |
287 | t0 = tsc_values[i]; | |
288 | sum += t0; | |
289 | } | |
290 | } | |
291 | avg = sum; | |
292 | do_div(avg, num_booting_cpus()); | |
293 | ||
294 | sum = 0; | |
295 | for (i = 0; i < NR_CPUS; i++) { | |
296 | if (!cpu_isset(i, cpu_callout_map)) | |
297 | continue; | |
298 | delta = tsc_values[i] - avg; | |
299 | if (delta < 0) | |
300 | delta = -delta; | |
301 | /* | |
302 | * We report bigger than 2 microseconds clock differences. | |
303 | */ | |
304 | if (delta > 2*one_usec) { | |
305 | long realdelta; | |
306 | if (!buggy) { | |
307 | buggy = 1; | |
308 | printk("\n"); | |
309 | } | |
310 | realdelta = delta; | |
311 | do_div(realdelta, one_usec); | |
312 | if (tsc_values[i] < avg) | |
313 | realdelta = -realdelta; | |
314 | ||
315 | printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta); | |
316 | } | |
317 | ||
318 | sum += delta; | |
319 | } | |
320 | if (!buggy) | |
321 | printk("passed.\n"); | |
322 | } | |
323 | ||
324 | static void __init synchronize_tsc_ap (void) | |
325 | { | |
326 | int i; | |
327 | ||
328 | /* | |
329 | * Not every cpu is online at the time | |
330 | * this gets called, so we first wait for the BP to | |
331 | * finish SMP initialization: | |
332 | */ | |
333 | while (!atomic_read(&tsc_start_flag)) mb(); | |
334 | ||
335 | for (i = 0; i < NR_LOOPS; i++) { | |
336 | atomic_inc(&tsc_count_start); | |
337 | while (atomic_read(&tsc_count_start) != num_booting_cpus()) | |
338 | mb(); | |
339 | ||
340 | rdtscll(tsc_values[smp_processor_id()]); | |
341 | if (i == NR_LOOPS-1) | |
342 | write_tsc(0, 0); | |
343 | ||
344 | atomic_inc(&tsc_count_stop); | |
345 | while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb(); | |
346 | } | |
347 | } | |
348 | #undef NR_LOOPS | |
349 | ||
350 | extern void calibrate_delay(void); | |
351 | ||
352 | static atomic_t init_deasserted; | |
353 | ||
0bb3184d | 354 | static void __devinit smp_callin(void) |
1da177e4 LT |
355 | { |
356 | int cpuid, phys_id; | |
357 | unsigned long timeout; | |
358 | ||
359 | /* | |
360 | * If waken up by an INIT in an 82489DX configuration | |
361 | * we may get here before an INIT-deassert IPI reaches | |
362 | * our local APIC. We have to wait for the IPI or we'll | |
363 | * lock up on an APIC access. | |
364 | */ | |
365 | wait_for_init_deassert(&init_deasserted); | |
366 | ||
367 | /* | |
368 | * (This works even if the APIC is not enabled.) | |
369 | */ | |
370 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
371 | cpuid = smp_processor_id(); | |
372 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
373 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
374 | phys_id, cpuid); | |
375 | BUG(); | |
376 | } | |
377 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
378 | ||
379 | /* | |
380 | * STARTUP IPIs are fragile beasts as they might sometimes | |
381 | * trigger some glue motherboard logic. Complete APIC bus | |
382 | * silence for 1 second, this overestimates the time the | |
383 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
384 | * by a factor of two. This should be enough. | |
385 | */ | |
386 | ||
387 | /* | |
388 | * Waiting 2s total for startup (udelay is not yet working) | |
389 | */ | |
390 | timeout = jiffies + 2*HZ; | |
391 | while (time_before(jiffies, timeout)) { | |
392 | /* | |
393 | * Has the boot CPU finished it's STARTUP sequence? | |
394 | */ | |
395 | if (cpu_isset(cpuid, cpu_callout_map)) | |
396 | break; | |
397 | rep_nop(); | |
398 | } | |
399 | ||
400 | if (!time_before(jiffies, timeout)) { | |
401 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
402 | cpuid); | |
403 | BUG(); | |
404 | } | |
405 | ||
406 | /* | |
407 | * the boot CPU has finished the init stage and is spinning | |
408 | * on callin_map until we finish. We are free to set up this | |
409 | * CPU, first the APIC. (this is probably redundant on most | |
410 | * boards) | |
411 | */ | |
412 | ||
413 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
414 | smp_callin_clear_local_apic(); | |
415 | setup_local_APIC(); | |
416 | map_cpu_to_logical_apicid(); | |
417 | ||
418 | /* | |
419 | * Get our bogomips. | |
420 | */ | |
421 | calibrate_delay(); | |
422 | Dprintk("Stack at about %p\n",&cpuid); | |
423 | ||
424 | /* | |
425 | * Save our processor parameters | |
426 | */ | |
427 | smp_store_cpu_info(cpuid); | |
428 | ||
429 | disable_APIC_timer(); | |
430 | ||
431 | /* | |
432 | * Allow the master to continue. | |
433 | */ | |
434 | cpu_set(cpuid, cpu_callin_map); | |
435 | ||
436 | /* | |
437 | * Synchronize the TSC with the BP | |
438 | */ | |
e1367daf | 439 | if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) |
1da177e4 LT |
440 | synchronize_tsc_ap(); |
441 | } | |
442 | ||
443 | static int cpucount; | |
444 | ||
d720803a LS |
445 | static inline void |
446 | set_cpu_sibling_map(int cpu) | |
447 | { | |
448 | int i; | |
449 | ||
450 | if (smp_num_siblings > 1) { | |
451 | for (i = 0; i < NR_CPUS; i++) { | |
452 | if (!cpu_isset(i, cpu_callout_map)) | |
453 | continue; | |
454 | if (cpu_core_id[cpu] == cpu_core_id[i]) { | |
455 | cpu_set(i, cpu_sibling_map[cpu]); | |
456 | cpu_set(cpu, cpu_sibling_map[i]); | |
457 | } | |
458 | } | |
459 | } else { | |
460 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
461 | } | |
462 | ||
463 | if (current_cpu_data.x86_num_cores > 1) { | |
464 | for (i = 0; i < NR_CPUS; i++) { | |
465 | if (!cpu_isset(i, cpu_callout_map)) | |
466 | continue; | |
467 | if (phys_proc_id[cpu] == phys_proc_id[i]) { | |
468 | cpu_set(i, cpu_core_map[cpu]); | |
469 | cpu_set(cpu, cpu_core_map[i]); | |
470 | } | |
471 | } | |
472 | } else { | |
473 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; | |
474 | } | |
475 | } | |
476 | ||
1da177e4 LT |
477 | /* |
478 | * Activate a secondary processor. | |
479 | */ | |
0bb3184d | 480 | static void __devinit start_secondary(void *unused) |
1da177e4 LT |
481 | { |
482 | /* | |
483 | * Dont put anything before smp_callin(), SMP | |
484 | * booting is too fragile that we want to limit the | |
485 | * things done here to the most necessary things. | |
486 | */ | |
487 | cpu_init(); | |
5bfb5d69 | 488 | preempt_disable(); |
1da177e4 LT |
489 | smp_callin(); |
490 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
491 | rep_nop(); | |
492 | setup_secondary_APIC_clock(); | |
493 | if (nmi_watchdog == NMI_IO_APIC) { | |
494 | disable_8259A_irq(0); | |
495 | enable_NMI_through_LVT0(NULL); | |
496 | enable_8259A_irq(0); | |
497 | } | |
498 | enable_APIC_timer(); | |
499 | /* | |
500 | * low-memory mappings have been cleared, flush them from | |
501 | * the local TLBs too. | |
502 | */ | |
503 | local_flush_tlb(); | |
6fe940d6 | 504 | |
d720803a LS |
505 | /* This must be done before setting cpu_online_map */ |
506 | set_cpu_sibling_map(raw_smp_processor_id()); | |
507 | wmb(); | |
508 | ||
6fe940d6 LS |
509 | /* |
510 | * We need to hold call_lock, so there is no inconsistency | |
511 | * between the time smp_call_function() determines number of | |
512 | * IPI receipients, and the time when the determination is made | |
513 | * for which cpus receive the IPI. Holding this | |
514 | * lock helps us to not include this cpu in a currently in progress | |
515 | * smp_call_function(). | |
516 | */ | |
517 | lock_ipi_call_lock(); | |
1da177e4 | 518 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 519 | unlock_ipi_call_lock(); |
e1367daf | 520 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
521 | |
522 | /* We can take interrupts now: we're officially "up". */ | |
523 | local_irq_enable(); | |
524 | ||
525 | wmb(); | |
526 | cpu_idle(); | |
527 | } | |
528 | ||
529 | /* | |
530 | * Everything has been set up for the secondary | |
531 | * CPUs - they just need to reload everything | |
532 | * from the task structure | |
533 | * This function must not return. | |
534 | */ | |
0bb3184d | 535 | void __devinit initialize_secondary(void) |
1da177e4 LT |
536 | { |
537 | /* | |
538 | * We don't actually need to load the full TSS, | |
539 | * basically just the stack pointer and the eip. | |
540 | */ | |
541 | ||
542 | asm volatile( | |
543 | "movl %0,%%esp\n\t" | |
544 | "jmp *%1" | |
545 | : | |
546 | :"r" (current->thread.esp),"r" (current->thread.eip)); | |
547 | } | |
548 | ||
549 | extern struct { | |
550 | void * esp; | |
551 | unsigned short ss; | |
552 | } stack_start; | |
553 | ||
554 | #ifdef CONFIG_NUMA | |
555 | ||
556 | /* which logical CPUs are on which nodes */ | |
6c036527 | 557 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 LT |
558 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
559 | /* which node each logical CPU is on */ | |
6c036527 | 560 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
561 | EXPORT_SYMBOL(cpu_2_node); |
562 | ||
563 | /* set up a mapping between cpu and node. */ | |
564 | static inline void map_cpu_to_node(int cpu, int node) | |
565 | { | |
566 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
567 | cpu_set(cpu, node_2_cpu_mask[node]); | |
568 | cpu_2_node[cpu] = node; | |
569 | } | |
570 | ||
571 | /* undo a mapping between cpu and node. */ | |
572 | static inline void unmap_cpu_to_node(int cpu) | |
573 | { | |
574 | int node; | |
575 | ||
576 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
577 | for (node = 0; node < MAX_NUMNODES; node ++) | |
578 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
579 | cpu_2_node[cpu] = 0; | |
580 | } | |
581 | #else /* !CONFIG_NUMA */ | |
582 | ||
583 | #define map_cpu_to_node(cpu, node) ({}) | |
584 | #define unmap_cpu_to_node(cpu) ({}) | |
585 | ||
586 | #endif /* CONFIG_NUMA */ | |
587 | ||
6c036527 | 588 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
589 | |
590 | static void map_cpu_to_logical_apicid(void) | |
591 | { | |
592 | int cpu = smp_processor_id(); | |
593 | int apicid = logical_smp_processor_id(); | |
594 | ||
595 | cpu_2_logical_apicid[cpu] = apicid; | |
596 | map_cpu_to_node(cpu, apicid_to_node(apicid)); | |
597 | } | |
598 | ||
599 | static void unmap_cpu_to_logical_apicid(int cpu) | |
600 | { | |
601 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
602 | unmap_cpu_to_node(cpu); | |
603 | } | |
604 | ||
605 | #if APIC_DEBUG | |
606 | static inline void __inquire_remote_apic(int apicid) | |
607 | { | |
608 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
609 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
610 | int timeout, status; | |
611 | ||
612 | printk("Inquiring remote APIC #%d...\n", apicid); | |
613 | ||
38e548ee | 614 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
615 | printk("... APIC #%d %s: ", apicid, names[i]); |
616 | ||
617 | /* | |
618 | * Wait for idle. | |
619 | */ | |
620 | apic_wait_icr_idle(); | |
621 | ||
622 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
623 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
624 | ||
625 | timeout = 0; | |
626 | do { | |
627 | udelay(100); | |
628 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
629 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
630 | ||
631 | switch (status) { | |
632 | case APIC_ICR_RR_VALID: | |
633 | status = apic_read(APIC_RRR); | |
634 | printk("%08x\n", status); | |
635 | break; | |
636 | default: | |
637 | printk("failed\n"); | |
638 | } | |
639 | } | |
640 | } | |
641 | #endif | |
642 | ||
643 | #ifdef WAKE_SECONDARY_VIA_NMI | |
644 | /* | |
645 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
646 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
647 | * won't ... remember to clear down the APIC, etc later. | |
648 | */ | |
0bb3184d | 649 | static int __devinit |
1da177e4 LT |
650 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
651 | { | |
652 | unsigned long send_status = 0, accept_status = 0; | |
653 | int timeout, maxlvt; | |
654 | ||
655 | /* Target chip */ | |
656 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
657 | ||
658 | /* Boot on the stack */ | |
659 | /* Kick the second */ | |
660 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
661 | ||
662 | Dprintk("Waiting for send to finish...\n"); | |
663 | timeout = 0; | |
664 | do { | |
665 | Dprintk("+"); | |
666 | udelay(100); | |
667 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
668 | } while (send_status && (timeout++ < 1000)); | |
669 | ||
670 | /* | |
671 | * Give the other CPU some time to accept the IPI. | |
672 | */ | |
673 | udelay(200); | |
674 | /* | |
675 | * Due to the Pentium erratum 3AP. | |
676 | */ | |
677 | maxlvt = get_maxlvt(); | |
678 | if (maxlvt > 3) { | |
679 | apic_read_around(APIC_SPIV); | |
680 | apic_write(APIC_ESR, 0); | |
681 | } | |
682 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
683 | Dprintk("NMI sent.\n"); | |
684 | ||
685 | if (send_status) | |
686 | printk("APIC never delivered???\n"); | |
687 | if (accept_status) | |
688 | printk("APIC delivery error (%lx).\n", accept_status); | |
689 | ||
690 | return (send_status | accept_status); | |
691 | } | |
692 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
693 | ||
694 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 695 | static int __devinit |
1da177e4 LT |
696 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
697 | { | |
698 | unsigned long send_status = 0, accept_status = 0; | |
699 | int maxlvt, timeout, num_starts, j; | |
700 | ||
701 | /* | |
702 | * Be paranoid about clearing APIC errors. | |
703 | */ | |
704 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
705 | apic_read_around(APIC_SPIV); | |
706 | apic_write(APIC_ESR, 0); | |
707 | apic_read(APIC_ESR); | |
708 | } | |
709 | ||
710 | Dprintk("Asserting INIT.\n"); | |
711 | ||
712 | /* | |
713 | * Turn INIT on target chip | |
714 | */ | |
715 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
716 | ||
717 | /* | |
718 | * Send IPI | |
719 | */ | |
720 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
721 | | APIC_DM_INIT); | |
722 | ||
723 | Dprintk("Waiting for send to finish...\n"); | |
724 | timeout = 0; | |
725 | do { | |
726 | Dprintk("+"); | |
727 | udelay(100); | |
728 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
729 | } while (send_status && (timeout++ < 1000)); | |
730 | ||
731 | mdelay(10); | |
732 | ||
733 | Dprintk("Deasserting INIT.\n"); | |
734 | ||
735 | /* Target chip */ | |
736 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
737 | ||
738 | /* Send IPI */ | |
739 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
740 | ||
741 | Dprintk("Waiting for send to finish...\n"); | |
742 | timeout = 0; | |
743 | do { | |
744 | Dprintk("+"); | |
745 | udelay(100); | |
746 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
747 | } while (send_status && (timeout++ < 1000)); | |
748 | ||
749 | atomic_set(&init_deasserted, 1); | |
750 | ||
751 | /* | |
752 | * Should we send STARTUP IPIs ? | |
753 | * | |
754 | * Determine this based on the APIC version. | |
755 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
756 | */ | |
757 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
758 | num_starts = 2; | |
759 | else | |
760 | num_starts = 0; | |
761 | ||
762 | /* | |
763 | * Run STARTUP IPI loop. | |
764 | */ | |
765 | Dprintk("#startup loops: %d.\n", num_starts); | |
766 | ||
767 | maxlvt = get_maxlvt(); | |
768 | ||
769 | for (j = 1; j <= num_starts; j++) { | |
770 | Dprintk("Sending STARTUP #%d.\n",j); | |
771 | apic_read_around(APIC_SPIV); | |
772 | apic_write(APIC_ESR, 0); | |
773 | apic_read(APIC_ESR); | |
774 | Dprintk("After apic_write.\n"); | |
775 | ||
776 | /* | |
777 | * STARTUP IPI | |
778 | */ | |
779 | ||
780 | /* Target chip */ | |
781 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
782 | ||
783 | /* Boot on the stack */ | |
784 | /* Kick the second */ | |
785 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
786 | | (start_eip >> 12)); | |
787 | ||
788 | /* | |
789 | * Give the other CPU some time to accept the IPI. | |
790 | */ | |
791 | udelay(300); | |
792 | ||
793 | Dprintk("Startup point 1.\n"); | |
794 | ||
795 | Dprintk("Waiting for send to finish...\n"); | |
796 | timeout = 0; | |
797 | do { | |
798 | Dprintk("+"); | |
799 | udelay(100); | |
800 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
801 | } while (send_status && (timeout++ < 1000)); | |
802 | ||
803 | /* | |
804 | * Give the other CPU some time to accept the IPI. | |
805 | */ | |
806 | udelay(200); | |
807 | /* | |
808 | * Due to the Pentium erratum 3AP. | |
809 | */ | |
810 | if (maxlvt > 3) { | |
811 | apic_read_around(APIC_SPIV); | |
812 | apic_write(APIC_ESR, 0); | |
813 | } | |
814 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
815 | if (send_status || accept_status) | |
816 | break; | |
817 | } | |
818 | Dprintk("After Startup.\n"); | |
819 | ||
820 | if (send_status) | |
821 | printk("APIC never delivered???\n"); | |
822 | if (accept_status) | |
823 | printk("APIC delivery error (%lx).\n", accept_status); | |
824 | ||
825 | return (send_status | accept_status); | |
826 | } | |
827 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
828 | ||
829 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
830 | static inline int alloc_cpu_id(void) |
831 | { | |
832 | cpumask_t tmp_map; | |
833 | int cpu; | |
834 | cpus_complement(tmp_map, cpu_present_map); | |
835 | cpu = first_cpu(tmp_map); | |
836 | if (cpu >= NR_CPUS) | |
837 | return -ENODEV; | |
838 | return cpu; | |
839 | } | |
840 | ||
841 | #ifdef CONFIG_HOTPLUG_CPU | |
842 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
843 | static inline struct task_struct * alloc_idle_task(int cpu) | |
844 | { | |
845 | struct task_struct *idle; | |
846 | ||
847 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
848 | /* initialize thread_struct. we really want to avoid destroy | |
849 | * idle tread | |
850 | */ | |
851 | idle->thread.esp = (unsigned long)(((struct pt_regs *) | |
852 | (THREAD_SIZE + (unsigned long) idle->thread_info)) - 1); | |
853 | init_idle(idle, cpu); | |
854 | return idle; | |
855 | } | |
856 | idle = fork_idle(cpu); | |
857 | ||
858 | if (!IS_ERR(idle)) | |
859 | cpu_idle_tasks[cpu] = idle; | |
860 | return idle; | |
861 | } | |
862 | #else | |
863 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
864 | #endif | |
1da177e4 | 865 | |
e1367daf | 866 | static int __devinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
867 | /* |
868 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
869 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
870 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
871 | */ | |
872 | { | |
873 | struct task_struct *idle; | |
874 | unsigned long boot_error; | |
e1367daf | 875 | int timeout; |
1da177e4 LT |
876 | unsigned long start_eip; |
877 | unsigned short nmi_high = 0, nmi_low = 0; | |
878 | ||
e1367daf LS |
879 | ++cpucount; |
880 | ||
1da177e4 LT |
881 | /* |
882 | * We can't use kernel_thread since we must avoid to | |
883 | * reschedule the child. | |
884 | */ | |
e1367daf | 885 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
886 | if (IS_ERR(idle)) |
887 | panic("failed fork for CPU %d", cpu); | |
888 | idle->thread.eip = (unsigned long) start_secondary; | |
889 | /* start_eip had better be page-aligned! */ | |
890 | start_eip = setup_trampoline(); | |
891 | ||
892 | /* So we see what's up */ | |
893 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
894 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
895 | stack_start.esp = (void *) idle->thread.esp; | |
896 | ||
897 | irq_ctx_init(cpu); | |
898 | ||
899 | /* | |
900 | * This grunge runs the startup process for | |
901 | * the targeted processor. | |
902 | */ | |
903 | ||
904 | atomic_set(&init_deasserted, 0); | |
905 | ||
906 | Dprintk("Setting warm reset code and vector.\n"); | |
907 | ||
908 | store_NMI_vector(&nmi_high, &nmi_low); | |
909 | ||
910 | smpboot_setup_warm_reset_vector(start_eip); | |
911 | ||
912 | /* | |
913 | * Starting actual IPI sequence... | |
914 | */ | |
915 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
916 | ||
917 | if (!boot_error) { | |
918 | /* | |
919 | * allow APs to start initializing. | |
920 | */ | |
921 | Dprintk("Before Callout %d.\n", cpu); | |
922 | cpu_set(cpu, cpu_callout_map); | |
923 | Dprintk("After Callout %d.\n", cpu); | |
924 | ||
925 | /* | |
926 | * Wait 5s total for a response | |
927 | */ | |
928 | for (timeout = 0; timeout < 50000; timeout++) { | |
929 | if (cpu_isset(cpu, cpu_callin_map)) | |
930 | break; /* It has booted */ | |
931 | udelay(100); | |
932 | } | |
933 | ||
934 | if (cpu_isset(cpu, cpu_callin_map)) { | |
935 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
936 | Dprintk("OK.\n"); | |
937 | printk("CPU%d: ", cpu); | |
938 | print_cpu_info(&cpu_data[cpu]); | |
939 | Dprintk("CPU has booted.\n"); | |
940 | } else { | |
941 | boot_error= 1; | |
942 | if (*((volatile unsigned char *)trampoline_base) | |
943 | == 0xA5) | |
944 | /* trampoline started but...? */ | |
945 | printk("Stuck ??\n"); | |
946 | else | |
947 | /* trampoline code not run */ | |
948 | printk("Not responding.\n"); | |
949 | inquire_remote_apic(apicid); | |
950 | } | |
951 | } | |
e1367daf | 952 | |
1da177e4 LT |
953 | if (boot_error) { |
954 | /* Try to put things back the way they were before ... */ | |
955 | unmap_cpu_to_logical_apicid(cpu); | |
956 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
957 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
958 | cpucount--; | |
e1367daf LS |
959 | } else { |
960 | x86_cpu_to_apicid[cpu] = apicid; | |
961 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
962 | } |
963 | ||
964 | /* mark "stuck" area as not stuck */ | |
965 | *((volatile unsigned long *)trampoline_base) = 0; | |
966 | ||
967 | return boot_error; | |
968 | } | |
969 | ||
e1367daf LS |
970 | #ifdef CONFIG_HOTPLUG_CPU |
971 | void cpu_exit_clear(void) | |
972 | { | |
973 | int cpu = raw_smp_processor_id(); | |
974 | ||
975 | idle_task_exit(); | |
976 | ||
977 | cpucount --; | |
978 | cpu_uninit(); | |
979 | irq_ctx_exit(cpu); | |
980 | ||
981 | cpu_clear(cpu, cpu_callout_map); | |
982 | cpu_clear(cpu, cpu_callin_map); | |
983 | cpu_clear(cpu, cpu_present_map); | |
984 | ||
985 | cpu_clear(cpu, smp_commenced_mask); | |
986 | unmap_cpu_to_logical_apicid(cpu); | |
987 | } | |
988 | ||
989 | struct warm_boot_cpu_info { | |
990 | struct completion *complete; | |
991 | int apicid; | |
992 | int cpu; | |
993 | }; | |
994 | ||
995 | static void __devinit do_warm_boot_cpu(void *p) | |
996 | { | |
997 | struct warm_boot_cpu_info *info = p; | |
998 | do_boot_cpu(info->apicid, info->cpu); | |
999 | complete(info->complete); | |
1000 | } | |
1001 | ||
1002 | int __devinit smp_prepare_cpu(int cpu) | |
1003 | { | |
1004 | DECLARE_COMPLETION(done); | |
1005 | struct warm_boot_cpu_info info; | |
1006 | struct work_struct task; | |
1007 | int apicid, ret; | |
1008 | ||
1009 | lock_cpu_hotplug(); | |
1010 | apicid = x86_cpu_to_apicid[cpu]; | |
1011 | if (apicid == BAD_APICID) { | |
1012 | ret = -ENODEV; | |
1013 | goto exit; | |
1014 | } | |
1015 | ||
1016 | info.complete = &done; | |
1017 | info.apicid = apicid; | |
1018 | info.cpu = cpu; | |
1019 | INIT_WORK(&task, do_warm_boot_cpu, &info); | |
1020 | ||
1021 | tsc_sync_disabled = 1; | |
1022 | ||
1023 | /* init low mem mapping */ | |
d7271b14 ZA |
1024 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
1025 | KERNEL_PGD_PTRS); | |
e1367daf LS |
1026 | flush_tlb_all(); |
1027 | schedule_work(&task); | |
1028 | wait_for_completion(&done); | |
1029 | ||
1030 | tsc_sync_disabled = 0; | |
1031 | zap_low_mappings(); | |
1032 | ret = 0; | |
1033 | exit: | |
1034 | unlock_cpu_hotplug(); | |
1035 | return ret; | |
1036 | } | |
1037 | #endif | |
1038 | ||
1da177e4 LT |
1039 | static void smp_tune_scheduling (void) |
1040 | { | |
1041 | unsigned long cachesize; /* kB */ | |
1042 | unsigned long bandwidth = 350; /* MB/s */ | |
1043 | /* | |
1044 | * Rough estimation for SMP scheduling, this is the number of | |
1045 | * cycles it takes for a fully memory-limited process to flush | |
1046 | * the SMP-local cache. | |
1047 | * | |
1048 | * (For a P5 this pretty much means we will choose another idle | |
1049 | * CPU almost always at wakeup time (this is due to the small | |
1050 | * L1 cache), on PIIs it's around 50-100 usecs, depending on | |
1051 | * the cache size) | |
1052 | */ | |
1053 | ||
1054 | if (!cpu_khz) { | |
1055 | /* | |
1056 | * this basically disables processor-affinity | |
1057 | * scheduling on SMP without a TSC. | |
1058 | */ | |
1059 | return; | |
1060 | } else { | |
1061 | cachesize = boot_cpu_data.x86_cache_size; | |
1062 | if (cachesize == -1) { | |
1063 | cachesize = 16; /* Pentiums, 2x8kB cache */ | |
1064 | bandwidth = 100; | |
1065 | } | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | /* | |
1070 | * Cycle through the processors sending APIC IPIs to boot each. | |
1071 | */ | |
1072 | ||
1073 | static int boot_cpu_logical_apicid; | |
1074 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
1075 | void *xquad_portio; | |
129f6946 AD |
1076 | #ifdef CONFIG_X86_NUMAQ |
1077 | EXPORT_SYMBOL(xquad_portio); | |
1078 | #endif | |
1da177e4 | 1079 | |
1da177e4 LT |
1080 | static void __init smp_boot_cpus(unsigned int max_cpus) |
1081 | { | |
1082 | int apicid, cpu, bit, kicked; | |
1083 | unsigned long bogosum = 0; | |
1084 | ||
1085 | /* | |
1086 | * Setup boot CPU information | |
1087 | */ | |
1088 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1089 | printk("CPU%d: ", 0); | |
1090 | print_cpu_info(&cpu_data[0]); | |
1091 | ||
1e4c85f9 | 1092 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1093 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1094 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1095 | ||
1096 | current_thread_info()->cpu = 0; | |
1097 | smp_tune_scheduling(); | |
1098 | cpus_clear(cpu_sibling_map[0]); | |
1099 | cpu_set(0, cpu_sibling_map[0]); | |
1100 | ||
3dd9d514 AK |
1101 | cpus_clear(cpu_core_map[0]); |
1102 | cpu_set(0, cpu_core_map[0]); | |
1103 | ||
1da177e4 LT |
1104 | /* |
1105 | * If we couldn't find an SMP configuration at boot time, | |
1106 | * get out of here now! | |
1107 | */ | |
1108 | if (!smp_found_config && !acpi_lapic) { | |
1109 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1110 | smpboot_clear_io_apic_irqs(); |
1111 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1112 | if (APIC_init_uniprocessor()) | |
1113 | printk(KERN_NOTICE "Local APIC not detected." | |
1114 | " Using dummy APIC emulation.\n"); | |
1115 | map_cpu_to_logical_apicid(); | |
1116 | cpu_set(0, cpu_sibling_map[0]); | |
1117 | cpu_set(0, cpu_core_map[0]); | |
1118 | return; | |
1119 | } | |
1120 | ||
1121 | /* | |
1122 | * Should not be necessary because the MP table should list the boot | |
1123 | * CPU too, but we do it for the sake of robustness anyway. | |
1124 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1125 | */ | |
1126 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1127 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1128 | boot_cpu_physical_apicid); | |
1129 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1130 | } | |
1131 | ||
1132 | /* | |
1133 | * If we couldn't find a local APIC, then get out of here now! | |
1134 | */ | |
1135 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1136 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1137 | boot_cpu_physical_apicid); | |
1138 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1139 | smpboot_clear_io_apic_irqs(); | |
1140 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1141 | cpu_set(0, cpu_sibling_map[0]); | |
1142 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1143 | return; |
1144 | } | |
1145 | ||
1e4c85f9 LT |
1146 | verify_local_APIC(); |
1147 | ||
1da177e4 LT |
1148 | /* |
1149 | * If SMP should be disabled, then really disable it! | |
1150 | */ | |
1e4c85f9 LT |
1151 | if (!max_cpus) { |
1152 | smp_found_config = 0; | |
1153 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1154 | smpboot_clear_io_apic_irqs(); | |
1155 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1156 | cpu_set(0, cpu_sibling_map[0]); | |
1157 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1158 | return; |
1159 | } | |
1160 | ||
1e4c85f9 LT |
1161 | connect_bsp_APIC(); |
1162 | setup_local_APIC(); | |
1163 | map_cpu_to_logical_apicid(); | |
1164 | ||
1165 | ||
1da177e4 LT |
1166 | setup_portio_remap(); |
1167 | ||
1168 | /* | |
1169 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1170 | * | |
1171 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1172 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1173 | * clustered apic ID. | |
1174 | */ | |
1175 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1176 | ||
1177 | kicked = 1; | |
1178 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1179 | apicid = cpu_present_to_apicid(bit); | |
1180 | /* | |
1181 | * Don't even attempt to start the boot CPU! | |
1182 | */ | |
1183 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1184 | continue; | |
1185 | ||
1186 | if (!check_apicid_present(bit)) | |
1187 | continue; | |
1188 | if (max_cpus <= cpucount+1) | |
1189 | continue; | |
1190 | ||
e1367daf | 1191 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1192 | printk("CPU #%d not responding - cannot use it.\n", |
1193 | apicid); | |
1194 | else | |
1195 | ++kicked; | |
1196 | } | |
1197 | ||
1198 | /* | |
1199 | * Cleanup possible dangling ends... | |
1200 | */ | |
1201 | smpboot_restore_warm_reset_vector(); | |
1202 | ||
1203 | /* | |
1204 | * Allow the user to impress friends. | |
1205 | */ | |
1206 | Dprintk("Before bogomips.\n"); | |
1207 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1208 | if (cpu_isset(cpu, cpu_callout_map)) | |
1209 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1210 | printk(KERN_INFO | |
1211 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1212 | cpucount+1, | |
1213 | bogosum/(500000/HZ), | |
1214 | (bogosum/(5000/HZ))%100); | |
1215 | ||
1216 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1217 | ||
1218 | if (smp_b_stepping) | |
1219 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1220 | ||
1221 | /* | |
1222 | * Don't taint if we are running SMP kernel on a single non-MP | |
1223 | * approved Athlon | |
1224 | */ | |
1225 | if (tainted & TAINT_UNSAFE_SMP) { | |
1226 | if (cpucount) | |
1227 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1228 | else | |
1229 | tainted &= ~TAINT_UNSAFE_SMP; | |
1230 | } | |
1231 | ||
1232 | Dprintk("Boot done.\n"); | |
1233 | ||
1234 | /* | |
1235 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1236 | * efficiently. | |
1237 | */ | |
3dd9d514 | 1238 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1239 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1240 | cpus_clear(cpu_core_map[cpu]); |
1241 | } | |
1da177e4 | 1242 | |
d720803a LS |
1243 | cpu_set(0, cpu_sibling_map[0]); |
1244 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1245 | |
1e4c85f9 LT |
1246 | smpboot_setup_io_apic(); |
1247 | ||
1248 | setup_boot_APIC_clock(); | |
1249 | ||
1da177e4 LT |
1250 | /* |
1251 | * Synchronize the TSC with the AP | |
1252 | */ | |
1253 | if (cpu_has_tsc && cpucount && cpu_khz) | |
1254 | synchronize_tsc_bp(); | |
1255 | } | |
1256 | ||
1257 | /* These are wrappers to interface to the new boot process. Someone | |
1258 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1259 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1260 | { | |
f3705136 ZM |
1261 | smp_commenced_mask = cpumask_of_cpu(0); |
1262 | cpu_callin_map = cpumask_of_cpu(0); | |
1263 | mb(); | |
1da177e4 LT |
1264 | smp_boot_cpus(max_cpus); |
1265 | } | |
1266 | ||
1267 | void __devinit smp_prepare_boot_cpu(void) | |
1268 | { | |
1269 | cpu_set(smp_processor_id(), cpu_online_map); | |
1270 | cpu_set(smp_processor_id(), cpu_callout_map); | |
e1367daf | 1271 | cpu_set(smp_processor_id(), cpu_present_map); |
4ad8d383 | 1272 | cpu_set(smp_processor_id(), cpu_possible_map); |
e1367daf | 1273 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
1274 | } |
1275 | ||
f3705136 | 1276 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1277 | static void |
1278 | remove_siblinginfo(int cpu) | |
1da177e4 | 1279 | { |
e1367daf LS |
1280 | int sibling; |
1281 | ||
1282 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) | |
1283 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
1284 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) | |
1285 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1286 | cpus_clear(cpu_sibling_map[cpu]); | |
1287 | cpus_clear(cpu_core_map[cpu]); | |
1288 | phys_proc_id[cpu] = BAD_APICID; | |
1289 | cpu_core_id[cpu] = BAD_APICID; | |
f3705136 ZM |
1290 | } |
1291 | ||
1292 | int __cpu_disable(void) | |
1293 | { | |
1294 | cpumask_t map = cpu_online_map; | |
1295 | int cpu = smp_processor_id(); | |
1296 | ||
1297 | /* | |
1298 | * Perhaps use cpufreq to drop frequency, but that could go | |
1299 | * into generic code. | |
1300 | * | |
1301 | * We won't take down the boot processor on i386 due to some | |
1302 | * interrupts only being able to be serviced by the BSP. | |
1303 | * Especially so if we're not using an IOAPIC -zwane | |
1304 | */ | |
1305 | if (cpu == 0) | |
1306 | return -EBUSY; | |
1307 | ||
1308 | /* We enable the timer again on the exit path of the death loop */ | |
1309 | disable_APIC_timer(); | |
1310 | /* Allow any queued timer interrupts to get serviced */ | |
1311 | local_irq_enable(); | |
1312 | mdelay(1); | |
1313 | local_irq_disable(); | |
1314 | ||
e1367daf LS |
1315 | remove_siblinginfo(cpu); |
1316 | ||
f3705136 ZM |
1317 | cpu_clear(cpu, map); |
1318 | fixup_irqs(map); | |
1319 | /* It's now safe to remove this processor from the online map */ | |
1320 | cpu_clear(cpu, cpu_online_map); | |
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | void __cpu_die(unsigned int cpu) | |
1325 | { | |
1326 | /* We don't do anything here: idle task is faking death itself. */ | |
1327 | unsigned int i; | |
1328 | ||
1329 | for (i = 0; i < 10; i++) { | |
1330 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1331 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1332 | printk ("CPU %d is now offline\n", cpu); | |
f3705136 | 1333 | return; |
e1367daf | 1334 | } |
aeb8397b | 1335 | msleep(100); |
1da177e4 | 1336 | } |
f3705136 ZM |
1337 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1338 | } | |
1339 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1340 | int __cpu_disable(void) | |
1341 | { | |
1342 | return -ENOSYS; | |
1343 | } | |
1da177e4 | 1344 | |
f3705136 ZM |
1345 | void __cpu_die(unsigned int cpu) |
1346 | { | |
1347 | /* We said "no" in __cpu_disable */ | |
1348 | BUG(); | |
1349 | } | |
1350 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1351 | ||
1352 | int __devinit __cpu_up(unsigned int cpu) | |
1353 | { | |
1da177e4 LT |
1354 | /* In case one didn't come up */ |
1355 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1356 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1357 | local_irq_enable(); |
1358 | return -EIO; | |
1359 | } | |
1360 | ||
1361 | local_irq_enable(); | |
e1367daf | 1362 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1363 | /* Unleash the CPU! */ |
1364 | cpu_set(cpu, smp_commenced_mask); | |
1365 | while (!cpu_isset(cpu, cpu_online_map)) | |
1366 | mb(); | |
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | void __init smp_cpus_done(unsigned int max_cpus) | |
1371 | { | |
1372 | #ifdef CONFIG_X86_IO_APIC | |
1373 | setup_ioapic_dest(); | |
1374 | #endif | |
1375 | zap_low_mappings(); | |
e1367daf | 1376 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1377 | /* |
1378 | * Disable executability of the SMP trampoline: | |
1379 | */ | |
1380 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1381 | #endif |
1da177e4 LT |
1382 | } |
1383 | ||
1384 | void __init smp_intr_init(void) | |
1385 | { | |
1386 | /* | |
1387 | * IRQ0 must be given a fixed assignment and initialized, | |
1388 | * because it's used before the IO-APIC is set up. | |
1389 | */ | |
1390 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1391 | ||
1392 | /* | |
1393 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1394 | * IPI, driven by wakeup. | |
1395 | */ | |
1396 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1397 | ||
1398 | /* IPI for invalidation */ | |
1399 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1400 | ||
1401 | /* IPI for generic function call */ | |
1402 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1403 | } |