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CommitLineData
1da177e4
LT
1/*
2 * Cyrix MediaGX and NatSemi Geode Suspend Modulation
3 * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
4 * (C) 2002 Hiroshi Miura <miura@da-cha.org>
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
32ee8c3e 9 * version 2 as published by the Free Software Foundation
1da177e4
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10 *
11 * The author(s) of this software shall not be held liable for damages
12 * of any nature resulting due to the use of this software. This
13 * software is provided AS-IS with no warranties.
32ee8c3e 14 *
1da177e4
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15 * Theoritical note:
16 *
17 * (see Geode(tm) CS5530 manual (rev.4.1) page.56)
18 *
19 * CPU frequency control on NatSemi Geode GX1/GXLV processor and CS55x0
20 * are based on Suspend Moduration.
21 *
22 * Suspend Modulation works by asserting and de-asserting the SUSP# pin
23 * to CPU(GX1/GXLV) for configurable durations. When asserting SUSP#
32ee8c3e 24 * the CPU enters an idle state. GX1 stops its core clock when SUSP# is
1da177e4
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25 * asserted then power consumption is reduced.
26 *
32ee8c3e 27 * Suspend Modulation's OFF/ON duration are configurable
1da177e4
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28 * with 'Suspend Modulation OFF Count Register'
29 * and 'Suspend Modulation ON Count Register'.
32ee8c3e 30 * These registers are 8bit counters that represent the number of
1da177e4
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31 * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
32 * to the processor.
33 *
32ee8c3e
DJ
34 * These counters define a ratio which is the effective frequency
35 * of operation of the system.
1da177e4
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36 *
37 * OFF Count
38 * F_eff = Fgx * ----------------------
39 * OFF Count + ON Count
40 *
41 * 0 <= On Count, Off Count <= 255
42 *
32ee8c3e 43 * From these limits, we can get register values
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44 *
45 * off_duration + on_duration <= MAX_DURATION
46 * on_duration = off_duration * (stock_freq - freq) / freq
47 *
32ee8c3e
DJ
48 * off_duration = (freq * DURATION) / stock_freq
49 * on_duration = DURATION - off_duration
1da177e4
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50 *
51 *
52 *---------------------------------------------------------------------------
53 *
54 * ChangeLog:
32ee8c3e
DJ
55 * Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org>
56 * - fix on/off register mistake
57 * - fix cpu_khz calc when it stops cpu modulation.
1da177e4 58 *
32ee8c3e
DJ
59 * Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org>
60 * - rewrite for Cyrix MediaGX Cx5510/5520 and
1da177e4
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61 * NatSemi Geode Cs5530(A).
62 *
63 * Jul. ??, 2002 Zwane Mwaikambo <zwane@commfireservices.com>
64 * - cs5530_mod patch for 2.4.19-rc1.
65 *
66 *---------------------------------------------------------------------------
67 *
68 * Todo
69 * Test on machines with 5510, 5530, 5530A
70 */
71
72/************************************************************************
73 * Suspend Modulation - Definitions *
74 ************************************************************************/
75
76#include <linux/kernel.h>
32ee8c3e 77#include <linux/module.h>
1da177e4
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78#include <linux/init.h>
79#include <linux/smp.h>
80#include <linux/cpufreq.h>
81#include <linux/pci.h>
32ee8c3e 82#include <asm/processor.h>
1da177e4
LT
83#include <asm/errno.h>
84
85/* PCI config registers, all at F0 */
32ee8c3e
DJ
86#define PCI_PMER1 0x80 /* power management enable register 1 */
87#define PCI_PMER2 0x81 /* power management enable register 2 */
88#define PCI_PMER3 0x82 /* power management enable register 3 */
89#define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */
90#define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
91#define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
92#define PCI_MODON 0x95 /* suspend modulation ON counter register */
93#define PCI_SUSCFG 0x96 /* suspend configuration register */
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94
95/* PMER1 bits */
32ee8c3e
DJ
96#define GPM (1<<0) /* global power management */
97#define GIT (1<<1) /* globally enable PM device idle timers */
98#define GTR (1<<2) /* globally enable IO traps */
99#define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */
100#define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */
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101
102/* SUSCFG bits */
32ee8c3e
DJ
103#define SUSMOD (1<<0) /* enable/disable suspend modulation */
104/* the belows support only with cs5530 (after rev.1.2)/cs5530A */
105#define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */
106 /* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
107#define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
108/* the belows support only with cs5530A */
109#define PWRSVE_ISA (1<<3) /* stop ISA clock */
110#define PWRSVE (1<<4) /* active idle */
1da177e4
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111
112struct gxfreq_params {
113 u8 on_duration;
114 u8 off_duration;
115 u8 pci_suscfg;
116 u8 pci_pmer1;
117 u8 pci_pmer2;
118 u8 pci_rev;
119 struct pci_dev *cs55x0;
120};
121
122static struct gxfreq_params *gx_params;
123static int stock_freq;
124
125/* PCI bus clock - defaults to 30.000 if cpu_khz is not available */
126static int pci_busclk = 0;
127module_param (pci_busclk, int, 0444);
128
129/* maximum duration for which the cpu may be suspended
130 * (32us * MAX_DURATION). If no parameter is given, this defaults
32ee8c3e 131 * to 255.
1da177e4
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132 * Note that this leads to a maximum of 8 ms(!) where the CPU clock
133 * is suspended -- processing power is just 0.39% of what it used to be,
134 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
135static int max_duration = 255;
136module_param (max_duration, int, 0444);
137
138/* For the default policy, we want at least some processing power
139 * - let's say 5%. (min = maxfreq / POLICY_MIN_DIV)
140 */
141#define POLICY_MIN_DIV 20
142
143
144#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "gx-suspmod", msg)
145
146/**
32ee8c3e
DJ
147 * we can detect a core multipiler from dir0_lsb
148 * from GX1 datasheet p.56,
149 * MULT[3:0]:
150 * 0000 = SYSCLK multiplied by 4 (test only)
151 * 0001 = SYSCLK multiplied by 10
152 * 0010 = SYSCLK multiplied by 4
153 * 0011 = SYSCLK multiplied by 6
154 * 0100 = SYSCLK multiplied by 9
155 * 0101 = SYSCLK multiplied by 5
156 * 0110 = SYSCLK multiplied by 7
157 * 0111 = SYSCLK multiplied by 8
1da177e4
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158 * of 33.3MHz
159 **/
160static int gx_freq_mult[16] = {
161 4, 10, 4, 6, 9, 5, 7, 8,
162 0, 0, 0, 0, 0, 0, 0, 0
163};
164
165
166/****************************************************************
32ee8c3e 167 * Low Level chipset interface *
1da177e4
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168 ****************************************************************/
169static struct pci_device_id gx_chipset_tbl[] __initdata = {
32ee8c3e
DJ
170 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, PCI_ANY_ID, PCI_ANY_ID },
171 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID },
172 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID },
173 { 0, },
1da177e4
LT
174};
175
176/**
32ee8c3e 177 * gx_detect_chipset:
1da177e4
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178 *
179 **/
180static __init struct pci_dev *gx_detect_chipset(void)
181{
182 struct pci_dev *gx_pci = NULL;
183
184 /* check if CPU is a MediaGX or a Geode. */
32ee8c3e 185 if ((current_cpu_data.x86_vendor != X86_VENDOR_NSC) &&
1da177e4
LT
186 (current_cpu_data.x86_vendor != X86_VENDOR_CYRIX)) {
187 dprintk("error: no MediaGX/Geode processor found!\n");
32ee8c3e 188 return NULL;
1da177e4
LT
189 }
190
191 /* detect which companion chip is used */
192 while ((gx_pci = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, gx_pci)) != NULL) {
32ee8c3e 193 if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
1da177e4 194 return gx_pci;
1da177e4
LT
195 }
196
197 dprintk("error: no supported chipset found!\n");
198 return NULL;
199}
200
201/**
32ee8c3e 202 * gx_get_cpuspeed:
1da177e4
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203 *
204 * Finds out at which efficient frequency the Cyrix MediaGX/NatSemi Geode CPU runs.
205 */
206static unsigned int gx_get_cpuspeed(unsigned int cpu)
207{
32ee8c3e 208 if ((gx_params->pci_suscfg & SUSMOD) == 0)
1da177e4
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209 return stock_freq;
210
32ee8c3e 211 return (stock_freq * gx_params->off_duration)
1da177e4
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212 / (gx_params->on_duration + gx_params->off_duration);
213}
214
215/**
216 * gx_validate_speed:
217 * determine current cpu speed
32ee8c3e
DJ
218 *
219 **/
1da177e4
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220
221static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, u8 *off_duration)
222{
223 unsigned int i;
224 u8 tmp_on, tmp_off;
225 int old_tmp_freq = stock_freq;
226 int tmp_freq;
227
228 *off_duration=1;
229 *on_duration=0;
230
231 for (i=max_duration; i>0; i--) {
32ee8c3e 232 tmp_off = ((khz * i) / stock_freq) & 0xff;
1da177e4
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233 tmp_on = i - tmp_off;
234 tmp_freq = (stock_freq * tmp_off) / i;
235 /* if this relation is closer to khz, use this. If it's equal,
236 * prefer it, too - lower latency */
237 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) {
238 *on_duration = tmp_on;
239 *off_duration = tmp_off;
240 old_tmp_freq = tmp_freq;
241 }
242 }
243
244 return old_tmp_freq;
245}
246
247
248/**
32ee8c3e
DJ
249 * gx_set_cpuspeed:
250 * set cpu speed in khz.
1da177e4
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251 **/
252
253static void gx_set_cpuspeed(unsigned int khz)
254{
32ee8c3e 255 u8 suscfg, pmer1;
1da177e4
LT
256 unsigned int new_khz;
257 unsigned long flags;
258 struct cpufreq_freqs freqs;
259
1da177e4
LT
260 freqs.cpu = 0;
261 freqs.old = gx_get_cpuspeed(0);
262
263 new_khz = gx_validate_speed(khz, &gx_params->on_duration, &gx_params->off_duration);
264
265 freqs.new = new_khz;
266
267 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
268 local_irq_save(flags);
269
270 if (new_khz != stock_freq) { /* if new khz == 100% of CPU speed, it is special case */
271 switch (gx_params->cs55x0->device) {
272 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
273 pmer1 = gx_params->pci_pmer1 | IRQ_SPDUP | VID_SPDUP;
274 /* FIXME: need to test other values -- Zwane,Miura */
275 pci_write_config_byte(gx_params->cs55x0, PCI_IRQTC, 4); /* typical 2 to 4ms */
276 pci_write_config_byte(gx_params->cs55x0, PCI_VIDTC, 100);/* typical 50 to 100ms */
277 pci_write_config_byte(gx_params->cs55x0, PCI_PMER1, pmer1);
278
279 if (gx_params->pci_rev < 0x10) { /* CS5530(rev 1.2, 1.3) */
280 suscfg = gx_params->pci_suscfg | SUSMOD;
281 } else { /* CS5530A,B.. */
282 suscfg = gx_params->pci_suscfg | SUSMOD | PWRSVE;
283 }
284 break;
285 case PCI_DEVICE_ID_CYRIX_5520:
286 case PCI_DEVICE_ID_CYRIX_5510:
287 suscfg = gx_params->pci_suscfg | SUSMOD;
288 break;
289 default:
290 local_irq_restore(flags);
291 dprintk("fatal: try to set unknown chipset.\n");
292 return;
293 }
294 } else {
295 suscfg = gx_params->pci_suscfg & ~(SUSMOD);
296 gx_params->off_duration = 0;
297 gx_params->on_duration = 0;
298 dprintk("suspend modulation disabled: cpu runs 100 percent speed.\n");
299 }
300
301 pci_write_config_byte(gx_params->cs55x0, PCI_MODOFF, gx_params->off_duration);
302 pci_write_config_byte(gx_params->cs55x0, PCI_MODON, gx_params->on_duration);
303
32ee8c3e
DJ
304 pci_write_config_byte(gx_params->cs55x0, PCI_SUSCFG, suscfg);
305 pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);
1da177e4 306
32ee8c3e 307 local_irq_restore(flags);
1da177e4
LT
308
309 gx_params->pci_suscfg = suscfg;
310
311 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
312
32ee8c3e
DJ
313 dprintk("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
314 gx_params->on_duration * 32, gx_params->off_duration * 32);
315 dprintk("suspend modulation w/ clock speed: %d kHz.\n", freqs.new);
1da177e4
LT
316}
317
318/****************************************************************
319 * High level functions *
320 ****************************************************************/
321
322/*
32ee8c3e 323 * cpufreq_gx_verify: test if frequency range is valid
1da177e4 324 *
32ee8c3e
DJ
325 * This function checks if a given frequency range in kHz is valid
326 * for the hardware supported by the driver.
1da177e4
LT
327 */
328
329static int cpufreq_gx_verify(struct cpufreq_policy *policy)
330{
331 unsigned int tmp_freq = 0;
332 u8 tmp1, tmp2;
333
32ee8c3e
DJ
334 if (!stock_freq || !policy)
335 return -EINVAL;
1da177e4
LT
336
337 policy->cpu = 0;
338 cpufreq_verify_within_limits(policy, (stock_freq / max_duration), stock_freq);
339
340 /* it needs to be assured that at least one supported frequency is
341 * within policy->min and policy->max. If it is not, policy->max
342 * needs to be increased until one freuqency is supported.
32ee8c3e 343 * policy->min may not be decreased, though. This way we guarantee a
1da177e4
LT
344 * specific processing capacity.
345 */
346 tmp_freq = gx_validate_speed(policy->min, &tmp1, &tmp2);
32ee8c3e 347 if (tmp_freq < policy->min)
1da177e4
LT
348 tmp_freq += stock_freq / max_duration;
349 policy->min = tmp_freq;
32ee8c3e 350 if (policy->min > policy->max)
1da177e4
LT
351 policy->max = tmp_freq;
352 tmp_freq = gx_validate_speed(policy->max, &tmp1, &tmp2);
353 if (tmp_freq > policy->max)
354 tmp_freq -= stock_freq / max_duration;
355 policy->max = tmp_freq;
356 if (policy->max < policy->min)
357 policy->max = policy->min;
358 cpufreq_verify_within_limits(policy, (stock_freq / max_duration), stock_freq);
32ee8c3e 359
1da177e4
LT
360 return 0;
361}
362
363/*
32ee8c3e 364 * cpufreq_gx_target:
1da177e4
LT
365 *
366 */
367static int cpufreq_gx_target(struct cpufreq_policy *policy,
368 unsigned int target_freq,
369 unsigned int relation)
370{
371 u8 tmp1, tmp2;
372 unsigned int tmp_freq;
373
32ee8c3e
DJ
374 if (!stock_freq || !policy)
375 return -EINVAL;
1da177e4
LT
376
377 policy->cpu = 0;
378
379 tmp_freq = gx_validate_speed(target_freq, &tmp1, &tmp2);
380 while (tmp_freq < policy->min) {
381 tmp_freq += stock_freq / max_duration;
382 tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
383 }
384 while (tmp_freq > policy->max) {
385 tmp_freq -= stock_freq / max_duration;
386 tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
387 }
388
389 gx_set_cpuspeed(tmp_freq);
390
391 return 0;
392}
393
394static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy)
395{
396 unsigned int maxfreq, curfreq;
397
398 if (!policy || policy->cpu != 0)
399 return -ENODEV;
400
401 /* determine maximum frequency */
402 if (pci_busclk) {
403 maxfreq = pci_busclk * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
404 } else if (cpu_khz) {
405 maxfreq = cpu_khz;
406 } else {
407 maxfreq = 30000 * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
408 }
409 stock_freq = maxfreq;
410 curfreq = gx_get_cpuspeed(0);
411
412 dprintk("cpu max frequency is %d.\n", maxfreq);
413 dprintk("cpu current frequency is %dkHz.\n",curfreq);
414
415 /* setup basic struct for cpufreq API */
416 policy->cpu = 0;
417
418 if (max_duration < POLICY_MIN_DIV)
419 policy->min = maxfreq / max_duration;
420 else
421 policy->min = maxfreq / POLICY_MIN_DIV;
422 policy->max = maxfreq;
423 policy->cur = curfreq;
424 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
425 policy->cpuinfo.min_freq = maxfreq / max_duration;
426 policy->cpuinfo.max_freq = maxfreq;
427 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
428
429 return 0;
430}
431
32ee8c3e 432/*
1da177e4
LT
433 * cpufreq_gx_init:
434 * MediaGX/Geode GX initialize cpufreq driver
435 */
436static struct cpufreq_driver gx_suspmod_driver = {
437 .get = gx_get_cpuspeed,
438 .verify = cpufreq_gx_verify,
439 .target = cpufreq_gx_target,
440 .init = cpufreq_gx_cpu_init,
441 .name = "gx-suspmod",
442 .owner = THIS_MODULE,
443};
444
445static int __init cpufreq_gx_init(void)
446{
447 int ret;
448 struct gxfreq_params *params;
449 struct pci_dev *gx_pci;
1da177e4
LT
450
451 /* Test if we have the right hardware */
32ee8c3e 452 if ((gx_pci = gx_detect_chipset()) == NULL)
1da177e4
LT
453 return -ENODEV;
454
455 /* check whether module parameters are sane */
456 if (max_duration > 0xff)
457 max_duration = 0xff;
458
459 dprintk("geode suspend modulation available.\n");
460
84f0b1ef 461 params = kzalloc(sizeof(struct gxfreq_params), GFP_KERNEL);
1da177e4
LT
462 if (params == NULL)
463 return -ENOMEM;
1da177e4
LT
464
465 params->cs55x0 = gx_pci;
466 gx_params = params;
467
468 /* keep cs55x0 configurations */
469 pci_read_config_byte(params->cs55x0, PCI_SUSCFG, &(params->pci_suscfg));
470 pci_read_config_byte(params->cs55x0, PCI_PMER1, &(params->pci_pmer1));
471 pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));
472 pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));
473 pci_read_config_byte(params->cs55x0, PCI_MODOFF, &(params->off_duration));
55e33734 474 pci_read_config_byte(params->cs55x0, PCI_REVISION_ID, &params->pci_rev);
1da177e4 475
32ee8c3e 476 if ((ret = cpufreq_register_driver(&gx_suspmod_driver))) {
1da177e4
LT
477 kfree(params);
478 return ret; /* register error! */
479 }
480
481 return 0;
482}
483
484static void __exit cpufreq_gx_exit(void)
485{
486 cpufreq_unregister_driver(&gx_suspmod_driver);
487 pci_dev_put(gx_params->cs55x0);
488 kfree(gx_params);
489}
490
491MODULE_AUTHOR ("Hiroshi Miura <miura@da-cha.org>");
492MODULE_DESCRIPTION ("Cpufreq driver for Cyrix MediaGX and NatSemi Geode");
493MODULE_LICENSE ("GPL");
494
495module_init(cpufreq_gx_init);
496module_exit(cpufreq_gx_exit);
497