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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/smp_lock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/mc146818rtc.h> | |
25 | #include <linux/kernel_stat.h> | |
26 | #include <linux/sysdev.h> | |
f3705136 | 27 | #include <linux/cpu.h> |
6eb0a0fd | 28 | #include <linux/module.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/desc.h> | |
35 | #include <asm/arch_hooks.h> | |
36 | #include <asm/hpet.h> | |
306e440d | 37 | #include <asm/i8253.h> |
3e4ff115 | 38 | #include <asm/nmi.h> |
2ff2d3d7 | 39 | #include <asm/idle.h> |
1da177e4 LT |
40 | |
41 | #include <mach_apic.h> | |
382dbd07 | 42 | #include <mach_apicdef.h> |
6eb0a0fd | 43 | #include <mach_ipi.h> |
1da177e4 LT |
44 | |
45 | #include "io_ports.h" | |
46 | ||
6eb0a0fd VP |
47 | /* |
48 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
49 | * IPIs in place of local APIC timers | |
50 | */ | |
51 | static cpumask_t timer_bcast_ipi; | |
52 | ||
9635b47d EB |
53 | /* |
54 | * Knob to control our willingness to enable the local APIC. | |
55 | */ | |
3d08a256 AB |
56 | static int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */ |
57 | ||
58 | static inline void lapic_disable(void) | |
59 | { | |
60 | enable_local_apic = -1; | |
61 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
62 | } | |
63 | ||
64 | static inline void lapic_enable(void) | |
65 | { | |
66 | enable_local_apic = 1; | |
67 | } | |
9635b47d | 68 | |
1da177e4 LT |
69 | /* |
70 | * Debug level | |
71 | */ | |
72 | int apic_verbosity; | |
73 | ||
74 | ||
75 | static void apic_pm_activate(void); | |
76 | ||
a0b4da91 | 77 | static int modern_apic(void) |
95d769aa AK |
78 | { |
79 | unsigned int lvr, version; | |
80 | /* AMD systems use old APIC versions, so check the CPU */ | |
81 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
82 | boot_cpu_data.x86 >= 0xf) | |
83 | return 1; | |
84 | lvr = apic_read(APIC_LVR); | |
85 | version = GET_APIC_VERSION(lvr); | |
86 | return version >= 0x14; | |
87 | } | |
88 | ||
1da177e4 LT |
89 | /* |
90 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
91 | * each architecture has to answer this themselves. | |
92 | */ | |
93 | void ack_bad_irq(unsigned int irq) | |
94 | { | |
95 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
96 | /* | |
97 | * Currently unexpected vectors happen only on SMP and APIC. | |
98 | * We _must_ ack these because every local APIC has only N | |
99 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
100 | * holds up an irq slot - in excessive cases (when multiple | |
101 | * unexpected vectors occur) that might lock up the APIC | |
102 | * completely. | |
3777a959 | 103 | * But only ack when the APIC is enabled -AK |
1da177e4 | 104 | */ |
e1a8e6c9 | 105 | if (cpu_has_apic) |
3777a959 | 106 | ack_APIC_irq(); |
1da177e4 LT |
107 | } |
108 | ||
109 | void __init apic_intr_init(void) | |
110 | { | |
111 | #ifdef CONFIG_SMP | |
112 | smp_intr_init(); | |
113 | #endif | |
114 | /* self generated IPI for local APIC timer */ | |
115 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
116 | ||
117 | /* IPI vectors for APIC spurious and error interrupts */ | |
118 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
119 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
120 | ||
121 | /* thermal monitor LVT interrupt */ | |
122 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
123 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
124 | #endif | |
125 | } | |
126 | ||
127 | /* Using APIC to generate smp_local_timer_interrupt? */ | |
acae9d32 | 128 | int using_apic_timer __read_mostly = 0; |
1da177e4 | 129 | |
1da177e4 LT |
130 | static int enabled_via_apicbase; |
131 | ||
132 | void enable_NMI_through_LVT0 (void * dummy) | |
133 | { | |
134 | unsigned int v, ver; | |
135 | ||
136 | ver = apic_read(APIC_LVR); | |
137 | ver = GET_APIC_VERSION(ver); | |
138 | v = APIC_DM_NMI; /* unmask and set to NMI */ | |
139 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
140 | v |= APIC_LVT_LEVEL_TRIGGER; | |
141 | apic_write_around(APIC_LVT0, v); | |
142 | } | |
143 | ||
144 | int get_physical_broadcast(void) | |
145 | { | |
95d769aa | 146 | if (modern_apic()) |
1da177e4 LT |
147 | return 0xff; |
148 | else | |
149 | return 0xf; | |
150 | } | |
151 | ||
152 | int get_maxlvt(void) | |
153 | { | |
154 | unsigned int v, ver, maxlvt; | |
155 | ||
156 | v = apic_read(APIC_LVR); | |
157 | ver = GET_APIC_VERSION(v); | |
158 | /* 82489DXs do not report # of LVT entries. */ | |
159 | maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; | |
160 | return maxlvt; | |
161 | } | |
162 | ||
163 | void clear_local_APIC(void) | |
164 | { | |
165 | int maxlvt; | |
166 | unsigned long v; | |
167 | ||
168 | maxlvt = get_maxlvt(); | |
169 | ||
170 | /* | |
704fc59e | 171 | * Masking an LVT entry can trigger a local APIC error |
1da177e4 LT |
172 | * if the vector is zero. Mask LVTERR first to prevent this. |
173 | */ | |
174 | if (maxlvt >= 3) { | |
175 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
176 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
177 | } | |
178 | /* | |
179 | * Careful: we have to set masks only first to deassert | |
180 | * any level-triggered sources. | |
181 | */ | |
182 | v = apic_read(APIC_LVTT); | |
183 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
184 | v = apic_read(APIC_LVT0); | |
185 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
186 | v = apic_read(APIC_LVT1); | |
187 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
188 | if (maxlvt >= 4) { | |
189 | v = apic_read(APIC_LVTPC); | |
190 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
191 | } | |
192 | ||
193 | /* lets not touch this if we didn't frob it */ | |
194 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
195 | if (maxlvt >= 5) { | |
196 | v = apic_read(APIC_LVTTHMR); | |
197 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
198 | } | |
199 | #endif | |
200 | /* | |
201 | * Clean APIC state for other OSs: | |
202 | */ | |
203 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); | |
204 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
205 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
206 | if (maxlvt >= 3) | |
207 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
208 | if (maxlvt >= 4) | |
209 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
210 | ||
211 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
212 | if (maxlvt >= 5) | |
213 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
214 | #endif | |
215 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
216 | if (APIC_INTEGRATED(v)) { /* !82489DX */ | |
217 | if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */ | |
218 | apic_write(APIC_ESR, 0); | |
219 | apic_read(APIC_ESR); | |
220 | } | |
221 | } | |
222 | ||
223 | void __init connect_bsp_APIC(void) | |
224 | { | |
225 | if (pic_mode) { | |
226 | /* | |
227 | * Do not trust the local APIC being empty at bootup. | |
228 | */ | |
229 | clear_local_APIC(); | |
230 | /* | |
231 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
232 | * connect BSP's local APIC to INT and NMI lines. | |
233 | */ | |
234 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
235 | "enabling APIC mode.\n"); | |
236 | outb(0x70, 0x22); | |
237 | outb(0x01, 0x23); | |
238 | } | |
239 | enable_apic_mode(); | |
240 | } | |
241 | ||
650927ef | 242 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
243 | { |
244 | if (pic_mode) { | |
245 | /* | |
246 | * Put the board back into PIC mode (has an effect | |
247 | * only on certain older boards). Note that APIC | |
248 | * interrupts, including IPIs, won't work beyond | |
249 | * this point! The only exception are INIT IPIs. | |
250 | */ | |
251 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
252 | "entering PIC mode.\n"); | |
253 | outb(0x70, 0x22); | |
254 | outb(0x00, 0x23); | |
255 | } | |
650927ef EB |
256 | else { |
257 | /* Go back to Virtual Wire compatibility mode */ | |
258 | unsigned long value; | |
259 | ||
260 | /* For the spurious interrupt use vector F, and enable it */ | |
261 | value = apic_read(APIC_SPIV); | |
262 | value &= ~APIC_VECTOR_MASK; | |
263 | value |= APIC_SPIV_APIC_ENABLED; | |
264 | value |= 0xf; | |
265 | apic_write_around(APIC_SPIV, value); | |
266 | ||
267 | if (!virt_wire_setup) { | |
268 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
269 | value = apic_read(APIC_LVT0); | |
270 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
271 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
272 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
273 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
274 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
275 | apic_write_around(APIC_LVT0, value); | |
276 | } | |
277 | else { | |
278 | /* Disable LVT0 */ | |
279 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
280 | } | |
281 | ||
282 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
283 | value = apic_read(APIC_LVT1); | |
284 | value &= ~( | |
285 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
286 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
287 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
288 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
289 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
290 | apic_write_around(APIC_LVT1, value); | |
291 | } | |
1da177e4 LT |
292 | } |
293 | ||
294 | void disable_local_APIC(void) | |
295 | { | |
296 | unsigned long value; | |
297 | ||
298 | clear_local_APIC(); | |
299 | ||
300 | /* | |
301 | * Disable APIC (implies clearing of registers | |
302 | * for 82489DX!). | |
303 | */ | |
304 | value = apic_read(APIC_SPIV); | |
305 | value &= ~APIC_SPIV_APIC_ENABLED; | |
306 | apic_write_around(APIC_SPIV, value); | |
307 | ||
308 | if (enabled_via_apicbase) { | |
309 | unsigned int l, h; | |
310 | rdmsr(MSR_IA32_APICBASE, l, h); | |
311 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
312 | wrmsr(MSR_IA32_APICBASE, l, h); | |
313 | } | |
314 | } | |
315 | ||
316 | /* | |
317 | * This is to verify that we're looking at a real local APIC. | |
318 | * Check these against your board if the CPUs aren't getting | |
319 | * started for no apparent reason. | |
320 | */ | |
321 | int __init verify_local_APIC(void) | |
322 | { | |
323 | unsigned int reg0, reg1; | |
324 | ||
325 | /* | |
326 | * The version register is read-only in a real APIC. | |
327 | */ | |
328 | reg0 = apic_read(APIC_LVR); | |
329 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
330 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
331 | reg1 = apic_read(APIC_LVR); | |
332 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
333 | ||
334 | /* | |
335 | * The two version reads above should print the same | |
336 | * numbers. If the second one is different, then we | |
337 | * poke at a non-APIC. | |
338 | */ | |
339 | if (reg1 != reg0) | |
340 | return 0; | |
341 | ||
342 | /* | |
343 | * Check if the version looks reasonably. | |
344 | */ | |
345 | reg1 = GET_APIC_VERSION(reg0); | |
346 | if (reg1 == 0x00 || reg1 == 0xff) | |
347 | return 0; | |
348 | reg1 = get_maxlvt(); | |
349 | if (reg1 < 0x02 || reg1 == 0xff) | |
350 | return 0; | |
351 | ||
352 | /* | |
353 | * The ID register is read/write in a real APIC. | |
354 | */ | |
355 | reg0 = apic_read(APIC_ID); | |
356 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
357 | ||
358 | /* | |
359 | * The next two are just to see if we have sane values. | |
360 | * They're only really relevant if we're in Virtual Wire | |
361 | * compatibility mode, but most boxes are anymore. | |
362 | */ | |
363 | reg0 = apic_read(APIC_LVT0); | |
364 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
365 | reg1 = apic_read(APIC_LVT1); | |
366 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
367 | ||
368 | return 1; | |
369 | } | |
370 | ||
371 | void __init sync_Arb_IDs(void) | |
372 | { | |
95d769aa AK |
373 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 |
374 | And not needed on AMD */ | |
375 | if (modern_apic()) | |
1da177e4 LT |
376 | return; |
377 | /* | |
378 | * Wait for idle. | |
379 | */ | |
380 | apic_wait_icr_idle(); | |
381 | ||
382 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
383 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
384 | | APIC_DM_INIT); | |
385 | } | |
386 | ||
387 | extern void __error_in_apic_c (void); | |
388 | ||
389 | /* | |
390 | * An initial setup of the virtual wire mode. | |
391 | */ | |
392 | void __init init_bsp_APIC(void) | |
393 | { | |
394 | unsigned long value, ver; | |
395 | ||
396 | /* | |
397 | * Don't do the setup now if we have a SMP BIOS as the | |
398 | * through-I/O-APIC virtual wire mode might be active. | |
399 | */ | |
400 | if (smp_found_config || !cpu_has_apic) | |
401 | return; | |
402 | ||
403 | value = apic_read(APIC_LVR); | |
404 | ver = GET_APIC_VERSION(value); | |
405 | ||
406 | /* | |
407 | * Do not trust the local APIC being empty at bootup. | |
408 | */ | |
409 | clear_local_APIC(); | |
410 | ||
411 | /* | |
412 | * Enable APIC. | |
413 | */ | |
414 | value = apic_read(APIC_SPIV); | |
415 | value &= ~APIC_VECTOR_MASK; | |
416 | value |= APIC_SPIV_APIC_ENABLED; | |
417 | ||
418 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
419 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15)) | |
420 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
421 | else | |
422 | value |= APIC_SPIV_FOCUS_DISABLED; | |
423 | value |= SPURIOUS_APIC_VECTOR; | |
424 | apic_write_around(APIC_SPIV, value); | |
425 | ||
426 | /* | |
427 | * Set up the virtual wire mode. | |
428 | */ | |
429 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
430 | value = APIC_DM_NMI; | |
431 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
432 | value |= APIC_LVT_LEVEL_TRIGGER; | |
433 | apic_write_around(APIC_LVT1, value); | |
434 | } | |
435 | ||
0bb3184d | 436 | void __devinit setup_local_APIC(void) |
1da177e4 LT |
437 | { |
438 | unsigned long oldvalue, value, ver, maxlvt; | |
1a75a3f0 | 439 | int i, j; |
1da177e4 LT |
440 | |
441 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
442 | if (esr_disable) { | |
443 | apic_write(APIC_ESR, 0); | |
444 | apic_write(APIC_ESR, 0); | |
445 | apic_write(APIC_ESR, 0); | |
446 | apic_write(APIC_ESR, 0); | |
447 | } | |
448 | ||
449 | value = apic_read(APIC_LVR); | |
450 | ver = GET_APIC_VERSION(value); | |
451 | ||
452 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
453 | __error_in_apic_c(); | |
454 | ||
455 | /* | |
456 | * Double-check whether this APIC is really registered. | |
457 | */ | |
458 | if (!apic_id_registered()) | |
459 | BUG(); | |
460 | ||
461 | /* | |
462 | * Intel recommends to set DFR, LDR and TPR before enabling | |
463 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
464 | * document number 292116). So here it goes... | |
465 | */ | |
466 | init_apic_ldr(); | |
467 | ||
468 | /* | |
469 | * Set Task Priority to 'accept all'. We never change this | |
470 | * later on. | |
471 | */ | |
472 | value = apic_read(APIC_TASKPRI); | |
473 | value &= ~APIC_TPRI_MASK; | |
474 | apic_write_around(APIC_TASKPRI, value); | |
475 | ||
1a75a3f0 VG |
476 | /* |
477 | * After a crash, we no longer service the interrupts and a pending | |
478 | * interrupt from previous kernel might still have ISR bit set. | |
479 | * | |
480 | * Most probably by now CPU has serviced that pending interrupt and | |
481 | * it might not have done the ack_APIC_irq() because it thought, | |
482 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
483 | * does not clear the ISR bit and cpu thinks it has already serivced | |
484 | * the interrupt. Hence a vector might get locked. It was noticed | |
485 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
486 | */ | |
487 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
488 | value = apic_read(APIC_ISR + i*0x10); | |
489 | for (j = 31; j >= 0; j--) { | |
490 | if (value & (1<<j)) | |
491 | ack_APIC_irq(); | |
492 | } | |
493 | } | |
494 | ||
1da177e4 LT |
495 | /* |
496 | * Now that we are all set up, enable the APIC | |
497 | */ | |
498 | value = apic_read(APIC_SPIV); | |
499 | value &= ~APIC_VECTOR_MASK; | |
500 | /* | |
501 | * Enable APIC | |
502 | */ | |
503 | value |= APIC_SPIV_APIC_ENABLED; | |
504 | ||
505 | /* | |
506 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
507 | * certain networking cards. If high frequency interrupts are | |
508 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
509 | * entry is masked/unmasked at a high rate as well then sooner or | |
510 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
511 | * from the device. If focus CPU is disabled then the hang goes | |
512 | * away, oh well :-( | |
513 | * | |
514 | * [ This bug can be reproduced easily with a level-triggered | |
515 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
516 | * BX chipset. ] | |
517 | */ | |
518 | /* | |
519 | * Actually disabling the focus CPU check just makes the hang less | |
520 | * frequent as it makes the interrupt distributon model be more | |
521 | * like LRU than MRU (the short-term load is more even across CPUs). | |
522 | * See also the comment in end_level_ioapic_irq(). --macro | |
523 | */ | |
524 | #if 1 | |
525 | /* Enable focus processor (bit==0) */ | |
526 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
527 | #else | |
528 | /* Disable focus processor (bit==1) */ | |
529 | value |= APIC_SPIV_FOCUS_DISABLED; | |
530 | #endif | |
531 | /* | |
532 | * Set spurious IRQ vector | |
533 | */ | |
534 | value |= SPURIOUS_APIC_VECTOR; | |
535 | apic_write_around(APIC_SPIV, value); | |
536 | ||
537 | /* | |
538 | * Set up LVT0, LVT1: | |
539 | * | |
540 | * set up through-local-APIC on the BP's LINT0. This is not | |
541 | * strictly necessery in pure symmetric-IO mode, but sometimes | |
542 | * we delegate interrupts to the 8259A. | |
543 | */ | |
544 | /* | |
545 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
546 | */ | |
547 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
548 | if (!smp_processor_id() && (pic_mode || !value)) { | |
549 | value = APIC_DM_EXTINT; | |
550 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
551 | smp_processor_id()); | |
552 | } else { | |
553 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
554 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
555 | smp_processor_id()); | |
556 | } | |
557 | apic_write_around(APIC_LVT0, value); | |
558 | ||
559 | /* | |
560 | * only the BP should see the LINT1 NMI signal, obviously. | |
561 | */ | |
562 | if (!smp_processor_id()) | |
563 | value = APIC_DM_NMI; | |
564 | else | |
565 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
566 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
567 | value |= APIC_LVT_LEVEL_TRIGGER; | |
568 | apic_write_around(APIC_LVT1, value); | |
569 | ||
570 | if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */ | |
571 | maxlvt = get_maxlvt(); | |
572 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
573 | apic_write(APIC_ESR, 0); | |
574 | oldvalue = apic_read(APIC_ESR); | |
575 | ||
576 | value = ERROR_APIC_VECTOR; // enables sending errors | |
577 | apic_write_around(APIC_LVTERR, value); | |
578 | /* | |
579 | * spec says clear errors after enabling vector. | |
580 | */ | |
581 | if (maxlvt > 3) | |
582 | apic_write(APIC_ESR, 0); | |
583 | value = apic_read(APIC_ESR); | |
584 | if (value != oldvalue) | |
585 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
586 | "vector: 0x%08lx after: 0x%08lx\n", | |
587 | oldvalue, value); | |
588 | } else { | |
589 | if (esr_disable) | |
590 | /* | |
591 | * Something untraceble is creating bad interrupts on | |
592 | * secondary quads ... for the moment, just leave the | |
593 | * ESR disabled - we can't do anything useful with the | |
594 | * errors anyway - mbligh | |
595 | */ | |
596 | printk("Leaving ESR disabled.\n"); | |
597 | else | |
598 | printk("No ESR for 82489DX.\n"); | |
599 | } | |
600 | ||
b7471c6d | 601 | setup_apic_nmi_watchdog(NULL); |
1da177e4 LT |
602 | apic_pm_activate(); |
603 | } | |
604 | ||
605 | /* | |
606 | * If Linux enabled the LAPIC against the BIOS default | |
607 | * disable it down before re-entering the BIOS on shutdown. | |
608 | * Otherwise the BIOS may get confused and not power-off. | |
77f72b19 ZM |
609 | * Additionally clear all LVT entries before disable_local_APIC |
610 | * for the case where Linux didn't enable the LAPIC. | |
1da177e4 LT |
611 | */ |
612 | void lapic_shutdown(void) | |
613 | { | |
67963132 MS |
614 | unsigned long flags; |
615 | ||
77f72b19 | 616 | if (!cpu_has_apic) |
1da177e4 LT |
617 | return; |
618 | ||
67963132 | 619 | local_irq_save(flags); |
77f72b19 ZM |
620 | clear_local_APIC(); |
621 | ||
622 | if (enabled_via_apicbase) | |
623 | disable_local_APIC(); | |
624 | ||
67963132 | 625 | local_irq_restore(flags); |
1da177e4 LT |
626 | } |
627 | ||
628 | #ifdef CONFIG_PM | |
629 | ||
630 | static struct { | |
631 | int active; | |
632 | /* r/w apic fields */ | |
633 | unsigned int apic_id; | |
634 | unsigned int apic_taskpri; | |
635 | unsigned int apic_ldr; | |
636 | unsigned int apic_dfr; | |
637 | unsigned int apic_spiv; | |
638 | unsigned int apic_lvtt; | |
639 | unsigned int apic_lvtpc; | |
640 | unsigned int apic_lvt0; | |
641 | unsigned int apic_lvt1; | |
642 | unsigned int apic_lvterr; | |
643 | unsigned int apic_tmict; | |
644 | unsigned int apic_tdcr; | |
645 | unsigned int apic_thmr; | |
646 | } apic_pm_state; | |
647 | ||
438510f6 | 648 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
649 | { |
650 | unsigned long flags; | |
f990fff4 | 651 | int maxlvt; |
1da177e4 LT |
652 | |
653 | if (!apic_pm_state.active) | |
654 | return 0; | |
655 | ||
f990fff4 KW |
656 | maxlvt = get_maxlvt(); |
657 | ||
1da177e4 LT |
658 | apic_pm_state.apic_id = apic_read(APIC_ID); |
659 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
660 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
661 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
662 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
663 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
f990fff4 KW |
664 | if (maxlvt >= 4) |
665 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1da177e4 LT |
666 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
667 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
668 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
669 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
670 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
f990fff4 KW |
671 | #ifdef CONFIG_X86_MCE_P4THERMAL |
672 | if (maxlvt >= 5) | |
673 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
674 | #endif | |
1da177e4 LT |
675 | |
676 | local_irq_save(flags); | |
677 | disable_local_APIC(); | |
678 | local_irq_restore(flags); | |
679 | return 0; | |
680 | } | |
681 | ||
682 | static int lapic_resume(struct sys_device *dev) | |
683 | { | |
684 | unsigned int l, h; | |
685 | unsigned long flags; | |
f990fff4 | 686 | int maxlvt; |
1da177e4 LT |
687 | |
688 | if (!apic_pm_state.active) | |
689 | return 0; | |
690 | ||
f990fff4 KW |
691 | maxlvt = get_maxlvt(); |
692 | ||
1da177e4 LT |
693 | local_irq_save(flags); |
694 | ||
695 | /* | |
696 | * Make sure the APICBASE points to the right address | |
697 | * | |
698 | * FIXME! This will be wrong if we ever support suspend on | |
699 | * SMP! We'll need to do this as part of the CPU restore! | |
700 | */ | |
701 | rdmsr(MSR_IA32_APICBASE, l, h); | |
702 | l &= ~MSR_IA32_APICBASE_BASE; | |
703 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
704 | wrmsr(MSR_IA32_APICBASE, l, h); | |
705 | ||
706 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
707 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
708 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
709 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
710 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
711 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
712 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
713 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
f990fff4 KW |
714 | #ifdef CONFIG_X86_MCE_P4THERMAL |
715 | if (maxlvt >= 5) | |
716 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
717 | #endif | |
718 | if (maxlvt >= 4) | |
719 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1da177e4 LT |
720 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); |
721 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
722 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
723 | apic_write(APIC_ESR, 0); | |
724 | apic_read(APIC_ESR); | |
725 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
726 | apic_write(APIC_ESR, 0); | |
727 | apic_read(APIC_ESR); | |
728 | local_irq_restore(flags); | |
729 | return 0; | |
730 | } | |
731 | ||
732 | /* | |
733 | * This device has no shutdown method - fully functioning local APICs | |
734 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
735 | */ | |
736 | ||
737 | static struct sysdev_class lapic_sysclass = { | |
738 | set_kset_name("lapic"), | |
739 | .resume = lapic_resume, | |
740 | .suspend = lapic_suspend, | |
741 | }; | |
742 | ||
743 | static struct sys_device device_lapic = { | |
744 | .id = 0, | |
745 | .cls = &lapic_sysclass, | |
746 | }; | |
747 | ||
0bb3184d | 748 | static void __devinit apic_pm_activate(void) |
1da177e4 LT |
749 | { |
750 | apic_pm_state.active = 1; | |
751 | } | |
752 | ||
753 | static int __init init_lapic_sysfs(void) | |
754 | { | |
755 | int error; | |
756 | ||
757 | if (!cpu_has_apic) | |
758 | return 0; | |
759 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
760 | ||
761 | error = sysdev_class_register(&lapic_sysclass); | |
762 | if (!error) | |
763 | error = sysdev_register(&device_lapic); | |
764 | return error; | |
765 | } | |
766 | device_initcall(init_lapic_sysfs); | |
767 | ||
768 | #else /* CONFIG_PM */ | |
769 | ||
770 | static void apic_pm_activate(void) { } | |
771 | ||
772 | #endif /* CONFIG_PM */ | |
773 | ||
774 | /* | |
775 | * Detect and enable local APICs on non-SMP boards. | |
776 | * Original code written by Keir Fraser. | |
777 | */ | |
778 | ||
1da177e4 LT |
779 | static int __init apic_set_verbosity(char *str) |
780 | { | |
781 | if (strcmp("debug", str) == 0) | |
782 | apic_verbosity = APIC_DEBUG; | |
783 | else if (strcmp("verbose", str) == 0) | |
784 | apic_verbosity = APIC_VERBOSE; | |
9b41046c | 785 | return 1; |
1da177e4 LT |
786 | } |
787 | ||
788 | __setup("apic=", apic_set_verbosity); | |
789 | ||
790 | static int __init detect_init_APIC (void) | |
791 | { | |
792 | u32 h, l, features; | |
1da177e4 LT |
793 | |
794 | /* Disabled by kernel option? */ | |
795 | if (enable_local_apic < 0) | |
796 | return -1; | |
797 | ||
1da177e4 LT |
798 | switch (boot_cpu_data.x86_vendor) { |
799 | case X86_VENDOR_AMD: | |
800 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
801 | (boot_cpu_data.x86 == 15)) | |
802 | break; | |
803 | goto no_apic; | |
804 | case X86_VENDOR_INTEL: | |
805 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
806 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
807 | break; | |
808 | goto no_apic; | |
809 | default: | |
810 | goto no_apic; | |
811 | } | |
812 | ||
813 | if (!cpu_has_apic) { | |
814 | /* | |
815 | * Over-ride BIOS and try to enable the local | |
816 | * APIC only if "lapic" specified. | |
817 | */ | |
818 | if (enable_local_apic <= 0) { | |
819 | printk("Local APIC disabled by BIOS -- " | |
820 | "you can enable it with \"lapic\"\n"); | |
821 | return -1; | |
822 | } | |
823 | /* | |
824 | * Some BIOSes disable the local APIC in the | |
825 | * APIC_BASE MSR. This can only be done in | |
826 | * software for Intel P6 or later and AMD K7 | |
827 | * (Model > 1) or later. | |
828 | */ | |
829 | rdmsr(MSR_IA32_APICBASE, l, h); | |
830 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
831 | printk("Local APIC disabled by BIOS -- reenabling.\n"); | |
832 | l &= ~MSR_IA32_APICBASE_BASE; | |
833 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
834 | wrmsr(MSR_IA32_APICBASE, l, h); | |
835 | enabled_via_apicbase = 1; | |
836 | } | |
837 | } | |
838 | /* | |
839 | * The APIC feature bit should now be enabled | |
840 | * in `cpuid' | |
841 | */ | |
842 | features = cpuid_edx(1); | |
843 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
844 | printk("Could not enable APIC!\n"); | |
845 | return -1; | |
846 | } | |
847 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
848 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
849 | ||
850 | /* The BIOS may have set up the APIC at some other address */ | |
851 | rdmsr(MSR_IA32_APICBASE, l, h); | |
852 | if (l & MSR_IA32_APICBASE_ENABLE) | |
853 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
854 | ||
855 | if (nmi_watchdog != NMI_NONE) | |
856 | nmi_watchdog = NMI_LOCAL_APIC; | |
857 | ||
858 | printk("Found and enabled local APIC!\n"); | |
859 | ||
860 | apic_pm_activate(); | |
861 | ||
862 | return 0; | |
863 | ||
864 | no_apic: | |
865 | printk("No local APIC present or hardware disabled\n"); | |
866 | return -1; | |
867 | } | |
868 | ||
869 | void __init init_apic_mappings(void) | |
870 | { | |
871 | unsigned long apic_phys; | |
872 | ||
873 | /* | |
874 | * If no local APIC can be found then set up a fake all | |
875 | * zeroes page to simulate the local APIC and another | |
876 | * one for the IO-APIC. | |
877 | */ | |
878 | if (!smp_found_config && detect_init_APIC()) { | |
879 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
880 | apic_phys = __pa(apic_phys); | |
881 | } else | |
882 | apic_phys = mp_lapic_addr; | |
883 | ||
884 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
885 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
886 | apic_phys); | |
887 | ||
888 | /* | |
889 | * Fetch the APIC ID of the BSP in case we have a | |
890 | * default configuration (or the MP table is broken). | |
891 | */ | |
1e4c85f9 LT |
892 | if (boot_cpu_physical_apicid == -1U) |
893 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 LT |
894 | |
895 | #ifdef CONFIG_X86_IO_APIC | |
896 | { | |
897 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
898 | int i; | |
899 | ||
900 | for (i = 0; i < nr_ioapics; i++) { | |
901 | if (smp_found_config) { | |
902 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
903 | if (!ioapic_phys) { | |
904 | printk(KERN_ERR | |
905 | "WARNING: bogus zero IO-APIC " | |
906 | "address found in MPTABLE, " | |
907 | "disabling IO/APIC support!\n"); | |
908 | smp_found_config = 0; | |
909 | skip_ioapic_setup = 1; | |
910 | goto fake_ioapic_page; | |
911 | } | |
912 | } else { | |
913 | fake_ioapic_page: | |
914 | ioapic_phys = (unsigned long) | |
915 | alloc_bootmem_pages(PAGE_SIZE); | |
916 | ioapic_phys = __pa(ioapic_phys); | |
917 | } | |
918 | set_fixmap_nocache(idx, ioapic_phys); | |
919 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
920 | __fix_to_virt(idx), ioapic_phys); | |
921 | idx++; | |
922 | } | |
923 | } | |
924 | #endif | |
925 | } | |
926 | ||
927 | /* | |
928 | * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts | |
929 | * per second. We assume that the caller has already set up the local | |
930 | * APIC. | |
931 | * | |
932 | * The APIC timer is not exactly sync with the external timer chip, it | |
933 | * closely follows bus clocks. | |
934 | */ | |
935 | ||
936 | /* | |
937 | * The timer chip is already set up at HZ interrupts per second here, | |
938 | * but we do not accept timer interrupts yet. We only allow the BP | |
939 | * to calibrate. | |
940 | */ | |
0bb3184d | 941 | static unsigned int __devinit get_8254_timer_count(void) |
1da177e4 | 942 | { |
1da177e4 LT |
943 | unsigned long flags; |
944 | ||
945 | unsigned int count; | |
946 | ||
947 | spin_lock_irqsave(&i8253_lock, flags); | |
948 | ||
949 | outb_p(0x00, PIT_MODE); | |
950 | count = inb_p(PIT_CH0); | |
951 | count |= inb_p(PIT_CH0) << 8; | |
952 | ||
953 | spin_unlock_irqrestore(&i8253_lock, flags); | |
954 | ||
955 | return count; | |
956 | } | |
957 | ||
958 | /* next tick in 8254 can be caught by catching timer wraparound */ | |
0bb3184d | 959 | static void __devinit wait_8254_wraparound(void) |
1da177e4 LT |
960 | { |
961 | unsigned int curr_count, prev_count; | |
962 | ||
963 | curr_count = get_8254_timer_count(); | |
964 | do { | |
965 | prev_count = curr_count; | |
966 | curr_count = get_8254_timer_count(); | |
967 | ||
968 | /* workaround for broken Mercury/Neptune */ | |
969 | if (prev_count >= curr_count + 0x100) | |
970 | curr_count = get_8254_timer_count(); | |
971 | ||
972 | } while (prev_count >= curr_count); | |
973 | } | |
974 | ||
975 | /* | |
976 | * Default initialization for 8254 timers. If we use other timers like HPET, | |
977 | * we override this later | |
978 | */ | |
0bb3184d | 979 | void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound; |
1da177e4 LT |
980 | |
981 | /* | |
982 | * This function sets up the local APIC timer, with a timeout of | |
983 | * 'clocks' APIC bus clock. During calibration we actually call | |
984 | * this function twice on the boot CPU, once with a bogus timeout | |
985 | * value, second time for real. The other (noncalibrating) CPUs | |
986 | * call this function only once, with the real, calibrated value. | |
987 | * | |
988 | * We do reads before writes even if unnecessary, to get around the | |
989 | * P5 APIC double write bug. | |
990 | */ | |
991 | ||
992 | #define APIC_DIVISOR 16 | |
993 | ||
994 | static void __setup_APIC_LVTT(unsigned int clocks) | |
995 | { | |
996 | unsigned int lvtt_value, tmp_value, ver; | |
6eb0a0fd | 997 | int cpu = smp_processor_id(); |
1da177e4 LT |
998 | |
999 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1000 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
1001 | if (!APIC_INTEGRATED(ver)) | |
1002 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
6eb0a0fd VP |
1003 | |
1004 | if (cpu_isset(cpu, timer_bcast_ipi)) | |
1005 | lvtt_value |= APIC_LVT_MASKED; | |
1006 | ||
1da177e4 LT |
1007 | apic_write_around(APIC_LVTT, lvtt_value); |
1008 | ||
1009 | /* | |
1010 | * Divide PICLK by 16 | |
1011 | */ | |
1012 | tmp_value = apic_read(APIC_TDCR); | |
1013 | apic_write_around(APIC_TDCR, (tmp_value | |
1014 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
1015 | | APIC_TDR_DIV_16); | |
1016 | ||
1017 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
1018 | } | |
1019 | ||
0bb3184d | 1020 | static void __devinit setup_APIC_timer(unsigned int clocks) |
1da177e4 LT |
1021 | { |
1022 | unsigned long flags; | |
1023 | ||
1024 | local_irq_save(flags); | |
1025 | ||
1026 | /* | |
1027 | * Wait for IRQ0's slice: | |
1028 | */ | |
1029 | wait_timer_tick(); | |
1030 | ||
1031 | __setup_APIC_LVTT(clocks); | |
1032 | ||
1033 | local_irq_restore(flags); | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * In this function we calibrate APIC bus clocks to the external | |
1038 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
1039 | * to calibrate, since some later bootup code depends on getting | |
1040 | * the first irq? Ugh. | |
1041 | * | |
1042 | * We want to do the calibration only once since we | |
1043 | * want to have local timer irqs syncron. CPUs connected | |
1044 | * by the same APIC bus have the very same bus frequency. | |
1045 | * And we want to have irqs off anyways, no accidental | |
1046 | * APIC irq that way. | |
1047 | */ | |
1048 | ||
1049 | static int __init calibrate_APIC_clock(void) | |
1050 | { | |
1051 | unsigned long long t1 = 0, t2 = 0; | |
1052 | long tt1, tt2; | |
1053 | long result; | |
1054 | int i; | |
1055 | const int LOOPS = HZ/10; | |
1056 | ||
1057 | apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n"); | |
1058 | ||
1059 | /* | |
1060 | * Put whatever arbitrary (but long enough) timeout | |
1061 | * value into the APIC clock, we just want to get the | |
1062 | * counter running for calibration. | |
1063 | */ | |
1064 | __setup_APIC_LVTT(1000000000); | |
1065 | ||
1066 | /* | |
1067 | * The timer chip counts down to zero. Let's wait | |
1068 | * for a wraparound to start exact measurement: | |
1069 | * (the current tick might have been already half done) | |
1070 | */ | |
1071 | ||
1072 | wait_timer_tick(); | |
1073 | ||
1074 | /* | |
1075 | * We wrapped around just now. Let's start: | |
1076 | */ | |
1077 | if (cpu_has_tsc) | |
1078 | rdtscll(t1); | |
1079 | tt1 = apic_read(APIC_TMCCT); | |
1080 | ||
1081 | /* | |
1082 | * Let's wait LOOPS wraprounds: | |
1083 | */ | |
1084 | for (i = 0; i < LOOPS; i++) | |
1085 | wait_timer_tick(); | |
1086 | ||
1087 | tt2 = apic_read(APIC_TMCCT); | |
1088 | if (cpu_has_tsc) | |
1089 | rdtscll(t2); | |
1090 | ||
1091 | /* | |
1092 | * The APIC bus clock counter is 32 bits only, it | |
1093 | * might have overflown, but note that we use signed | |
1094 | * longs, thus no extra care needed. | |
1095 | * | |
1096 | * underflown to be exact, as the timer counts down ;) | |
1097 | */ | |
1098 | ||
1099 | result = (tt1-tt2)*APIC_DIVISOR/LOOPS; | |
1100 | ||
1101 | if (cpu_has_tsc) | |
1102 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
1103 | "%ld.%04ld MHz.\n", | |
1104 | ((long)(t2-t1)/LOOPS)/(1000000/HZ), | |
1105 | ((long)(t2-t1)/LOOPS)%(1000000/HZ)); | |
1106 | ||
1107 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
1108 | "%ld.%04ld MHz.\n", | |
1109 | result/(1000000/HZ), | |
1110 | result%(1000000/HZ)); | |
1111 | ||
1112 | return result; | |
1113 | } | |
1114 | ||
1115 | static unsigned int calibration_result; | |
1116 | ||
1117 | void __init setup_boot_APIC_clock(void) | |
1118 | { | |
f2b36db6 | 1119 | unsigned long flags; |
1da177e4 LT |
1120 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"); |
1121 | using_apic_timer = 1; | |
1122 | ||
f2b36db6 | 1123 | local_irq_save(flags); |
1da177e4 LT |
1124 | |
1125 | calibration_result = calibrate_APIC_clock(); | |
1126 | /* | |
1127 | * Now set up the timer for real. | |
1128 | */ | |
1129 | setup_APIC_timer(calibration_result); | |
1130 | ||
f2b36db6 | 1131 | local_irq_restore(flags); |
1da177e4 LT |
1132 | } |
1133 | ||
0bb3184d | 1134 | void __devinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
1135 | { |
1136 | setup_APIC_timer(calibration_result); | |
1137 | } | |
1138 | ||
6eb0a0fd | 1139 | void disable_APIC_timer(void) |
1da177e4 LT |
1140 | { |
1141 | if (using_apic_timer) { | |
1142 | unsigned long v; | |
1143 | ||
1144 | v = apic_read(APIC_LVTT); | |
704fc59e SS |
1145 | /* |
1146 | * When an illegal vector value (0-15) is written to an LVT | |
1147 | * entry and delivery mode is Fixed, the APIC may signal an | |
1148 | * illegal vector error, with out regard to whether the mask | |
1149 | * bit is set or whether an interrupt is actually seen on input. | |
1150 | * | |
1151 | * Boot sequence might call this function when the LVTT has | |
1152 | * '0' vector value. So make sure vector field is set to | |
1153 | * valid value. | |
1154 | */ | |
1155 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1156 | apic_write_around(APIC_LVTT, v); | |
1da177e4 LT |
1157 | } |
1158 | } | |
1159 | ||
1160 | void enable_APIC_timer(void) | |
1161 | { | |
6eb0a0fd VP |
1162 | int cpu = smp_processor_id(); |
1163 | ||
1164 | if (using_apic_timer && | |
1165 | !cpu_isset(cpu, timer_bcast_ipi)) { | |
1da177e4 LT |
1166 | unsigned long v; |
1167 | ||
1168 | v = apic_read(APIC_LVTT); | |
1169 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); | |
1170 | } | |
1171 | } | |
1172 | ||
6eb0a0fd VP |
1173 | void switch_APIC_timer_to_ipi(void *cpumask) |
1174 | { | |
1175 | cpumask_t mask = *(cpumask_t *)cpumask; | |
1176 | int cpu = smp_processor_id(); | |
1177 | ||
1178 | if (cpu_isset(cpu, mask) && | |
1179 | !cpu_isset(cpu, timer_bcast_ipi)) { | |
1180 | disable_APIC_timer(); | |
1181 | cpu_set(cpu, timer_bcast_ipi); | |
1182 | } | |
1183 | } | |
1184 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); | |
1185 | ||
1186 | void switch_ipi_to_APIC_timer(void *cpumask) | |
1187 | { | |
1188 | cpumask_t mask = *(cpumask_t *)cpumask; | |
1189 | int cpu = smp_processor_id(); | |
1190 | ||
1191 | if (cpu_isset(cpu, mask) && | |
1192 | cpu_isset(cpu, timer_bcast_ipi)) { | |
1193 | cpu_clear(cpu, timer_bcast_ipi); | |
1194 | enable_APIC_timer(); | |
1195 | } | |
1196 | } | |
1197 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); | |
1198 | ||
1da177e4 LT |
1199 | #undef APIC_DIVISOR |
1200 | ||
1201 | /* | |
1202 | * Local timer interrupt handler. It does both profiling and | |
1203 | * process statistics/rescheduling. | |
1204 | * | |
1205 | * We do profiling in every local tick, statistics/rescheduling | |
1206 | * happen only every 'profiling multiplier' ticks. The default | |
1207 | * multiplier is 1 and it can be changed by writing the new multiplier | |
1208 | * value into /proc/profile. | |
1209 | */ | |
1210 | ||
7d12e780 | 1211 | inline void smp_local_timer_interrupt(void) |
1da177e4 | 1212 | { |
7d12e780 | 1213 | profile_tick(CPU_PROFILING); |
1da177e4 | 1214 | #ifdef CONFIG_SMP |
d195412c | 1215 | update_process_times(user_mode_vm(get_irq_regs())); |
1da177e4 | 1216 | #endif |
1da177e4 LT |
1217 | |
1218 | /* | |
1219 | * We take the 'long' return path, and there every subsystem | |
1220 | * grabs the apropriate locks (kernel lock/ irq lock). | |
1221 | * | |
1222 | * we might want to decouple profiling from the 'long path', | |
1223 | * and do the profiling totally in assembly. | |
1224 | * | |
1225 | * Currently this isn't too much of an issue (performance wise), | |
1226 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
1227 | */ | |
1228 | } | |
1229 | ||
1230 | /* | |
1231 | * Local APIC timer interrupt. This is the most natural way for doing | |
1232 | * local interrupts, but local timer interrupts can be emulated by | |
1233 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
1234 | * | |
1235 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
1236 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
1237 | */ | |
1238 | ||
1239 | fastcall void smp_apic_timer_interrupt(struct pt_regs *regs) | |
1240 | { | |
7d12e780 | 1241 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 LT |
1242 | int cpu = smp_processor_id(); |
1243 | ||
1244 | /* | |
1245 | * the NMI deadlock-detector uses this. | |
1246 | */ | |
1247 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
1248 | ||
1249 | /* | |
1250 | * NOTE! We'd better ACK the irq immediately, | |
1251 | * because timer handling can be slow. | |
1252 | */ | |
1253 | ack_APIC_irq(); | |
1254 | /* | |
1255 | * update_process_times() expects us to have done irq_enter(). | |
1256 | * Besides, if we don't timer interrupts ignore the global | |
1257 | * interrupt lock, which is the WrongThing (tm) to do. | |
1258 | */ | |
2ff2d3d7 | 1259 | exit_idle(); |
1da177e4 | 1260 | irq_enter(); |
7d12e780 | 1261 | smp_local_timer_interrupt(); |
1da177e4 | 1262 | irq_exit(); |
7d12e780 | 1263 | set_irq_regs(old_regs); |
1da177e4 LT |
1264 | } |
1265 | ||
6eb0a0fd | 1266 | #ifndef CONFIG_SMP |
7d12e780 | 1267 | static void up_apic_timer_interrupt_call(void) |
6eb0a0fd VP |
1268 | { |
1269 | int cpu = smp_processor_id(); | |
1270 | ||
1271 | /* | |
1272 | * the NMI deadlock-detector uses this. | |
1273 | */ | |
1274 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
1275 | ||
7d12e780 | 1276 | smp_local_timer_interrupt(); |
6eb0a0fd VP |
1277 | } |
1278 | #endif | |
1279 | ||
7d12e780 | 1280 | void smp_send_timer_broadcast_ipi(void) |
6eb0a0fd VP |
1281 | { |
1282 | cpumask_t mask; | |
1283 | ||
1284 | cpus_and(mask, cpu_online_map, timer_bcast_ipi); | |
1285 | if (!cpus_empty(mask)) { | |
1286 | #ifdef CONFIG_SMP | |
1287 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
1288 | #else | |
1289 | /* | |
1290 | * We can directly call the apic timer interrupt handler | |
1291 | * in UP case. Minus all irq related functions | |
1292 | */ | |
7d12e780 | 1293 | up_apic_timer_interrupt_call(); |
6eb0a0fd VP |
1294 | #endif |
1295 | } | |
1296 | } | |
1297 | ||
5a07a30c VP |
1298 | int setup_profiling_timer(unsigned int multiplier) |
1299 | { | |
1300 | return -EINVAL; | |
1301 | } | |
1302 | ||
1da177e4 LT |
1303 | /* |
1304 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1305 | */ | |
1306 | fastcall void smp_spurious_interrupt(struct pt_regs *regs) | |
1307 | { | |
1308 | unsigned long v; | |
1309 | ||
2ff2d3d7 | 1310 | exit_idle(); |
1da177e4 LT |
1311 | irq_enter(); |
1312 | /* | |
1313 | * Check if this really is a spurious interrupt and ACK it | |
1314 | * if it is a vectored one. Just in case... | |
1315 | * Spurious interrupts should not be ACKed. | |
1316 | */ | |
1317 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1318 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1319 | ack_APIC_irq(); | |
1320 | ||
1321 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1322 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n", | |
1323 | smp_processor_id()); | |
1324 | irq_exit(); | |
1325 | } | |
1326 | ||
1327 | /* | |
1328 | * This interrupt should never happen with our APIC/SMP architecture | |
1329 | */ | |
1330 | ||
1331 | fastcall void smp_error_interrupt(struct pt_regs *regs) | |
1332 | { | |
1333 | unsigned long v, v1; | |
1334 | ||
2ff2d3d7 | 1335 | exit_idle(); |
1da177e4 LT |
1336 | irq_enter(); |
1337 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1338 | v = apic_read(APIC_ESR); | |
1339 | apic_write(APIC_ESR, 0); | |
1340 | v1 = apic_read(APIC_ESR); | |
1341 | ack_APIC_irq(); | |
1342 | atomic_inc(&irq_err_count); | |
1343 | ||
1344 | /* Here is what the APIC error bits mean: | |
1345 | 0: Send CS error | |
1346 | 1: Receive CS error | |
1347 | 2: Send accept error | |
1348 | 3: Receive accept error | |
1349 | 4: Reserved | |
1350 | 5: Send illegal vector | |
1351 | 6: Received illegal vector | |
1352 | 7: Illegal register address | |
1353 | */ | |
1354 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
1355 | smp_processor_id(), v , v1); | |
1356 | irq_exit(); | |
1357 | } | |
1358 | ||
1359 | /* | |
1e4c85f9 LT |
1360 | * This initializes the IO-APIC and APIC hardware if this is |
1361 | * a UP kernel. | |
1da177e4 | 1362 | */ |
1e4c85f9 | 1363 | int __init APIC_init_uniprocessor (void) |
1da177e4 | 1364 | { |
1e4c85f9 LT |
1365 | if (enable_local_apic < 0) |
1366 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1da177e4 | 1367 | |
1e4c85f9 | 1368 | if (!smp_found_config && !cpu_has_apic) |
1da177e4 LT |
1369 | return -1; |
1370 | ||
1371 | /* | |
1e4c85f9 | 1372 | * Complain if the BIOS pretends there is one. |
1da177e4 LT |
1373 | */ |
1374 | if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1375 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1376 | boot_cpu_physical_apicid); | |
3777a959 | 1377 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); |
1da177e4 LT |
1378 | return -1; |
1379 | } | |
1380 | ||
1381 | verify_local_APIC(); | |
1382 | ||
1383 | connect_bsp_APIC(); | |
1384 | ||
be0d03f1 VG |
1385 | /* |
1386 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1387 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1388 | * might be zero if read from MP tables. Get it from LAPIC. | |
1389 | */ | |
1390 | #ifdef CONFIG_CRASH_DUMP | |
1391 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1392 | #endif | |
1e4c85f9 | 1393 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); |
1da177e4 | 1394 | |
1e4c85f9 | 1395 | setup_local_APIC(); |
1da177e4 | 1396 | |
1da177e4 | 1397 | #ifdef CONFIG_X86_IO_APIC |
1e4c85f9 LT |
1398 | if (smp_found_config) |
1399 | if (!skip_ioapic_setup && nr_ioapics) | |
1400 | setup_IO_APIC(); | |
1da177e4 | 1401 | #endif |
bbab4f3b | 1402 | setup_boot_clock(); |
1e4c85f9 LT |
1403 | |
1404 | return 0; | |
1da177e4 | 1405 | } |
1a3f239d RR |
1406 | |
1407 | static int __init parse_lapic(char *arg) | |
1408 | { | |
1409 | lapic_enable(); | |
1410 | return 0; | |
1411 | } | |
1412 | early_param("lapic", parse_lapic); | |
1413 | ||
1414 | static int __init parse_nolapic(char *arg) | |
1415 | { | |
1416 | lapic_disable(); | |
1417 | return 0; | |
1418 | } | |
1419 | early_param("nolapic", parse_nolapic); | |
1420 |