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8d67bca5 | 1 | /* |
1da177e4 LT |
2 | * linux/arch/cris/kernel/irq.c |
3 | * | |
4 | * Copyright (c) 2000-2002 Axis Communications AB | |
5 | * | |
6 | * Authors: Bjorn Wesen (bjornw@axis.com) | |
7 | * | |
8 | * This file contains the interrupt vectors and some | |
9 | * helper functions | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <asm/irq.h> | |
7b275523 | 14 | #include <asm/current.h> |
2e0cea1d | 15 | #include <linux/irq.h> |
7b275523 | 16 | #include <linux/interrupt.h> |
1da177e4 LT |
17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | |
1da177e4 | 19 | |
4150764f JN |
20 | #define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); |
21 | #define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); | |
1da177e4 LT |
22 | |
23 | /* don't use set_int_vector, it bypasses the linux interrupt handlers. it is | |
24 | * global just so that the kernel gdb can use it. | |
25 | */ | |
26 | ||
27 | void | |
28 | set_int_vector(int n, irqvectptr addr) | |
29 | { | |
30 | etrax_irv->v[n + 0x20] = (irqvectptr)addr; | |
31 | } | |
32 | ||
33 | /* the breakpoint vector is obviously not made just like the normal irq handlers | |
34 | * but needs to contain _code_ to jump to addr. | |
35 | * | |
36 | * the BREAK n instruction jumps to IBR + n * 8 | |
37 | */ | |
38 | ||
39 | void | |
40 | set_break_vector(int n, irqvectptr addr) | |
41 | { | |
42 | unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2]; | |
43 | unsigned long *jaddr = (unsigned long *)(jinstr + 1); | |
44 | ||
45 | /* if you don't know what this does, do not touch it! */ | |
46 | ||
47 | *jinstr = 0x0d3f; | |
48 | *jaddr = (unsigned long)addr; | |
49 | ||
50 | /* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */ | |
51 | } | |
52 | ||
53 | /* | |
54 | * This builds up the IRQ handler stubs using some ugly macros in irq.h | |
55 | * | |
56 | * These macros create the low-level assembly IRQ routines that do all | |
57 | * the operations that are needed. They are also written to be fast - and to | |
58 | * disable interrupts as little as humanly possible. | |
59 | * | |
60 | */ | |
61 | ||
62 | /* IRQ0 and 1 are special traps */ | |
63 | void hwbreakpoint(void); | |
64 | void IRQ1_interrupt(void); | |
65 | BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */ | |
66 | BUILD_IRQ(3, 0x08) | |
67 | BUILD_IRQ(4, 0x10) | |
68 | BUILD_IRQ(5, 0x20) | |
69 | BUILD_IRQ(6, 0x40) | |
70 | BUILD_IRQ(7, 0x80) | |
71 | BUILD_IRQ(8, 0x100) | |
72 | BUILD_IRQ(9, 0x200) | |
73 | BUILD_IRQ(10, 0x400) | |
74 | BUILD_IRQ(11, 0x800) | |
75 | BUILD_IRQ(12, 0x1000) | |
76 | BUILD_IRQ(13, 0x2000) | |
77 | void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */ | |
78 | void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */ | |
7b275523 JN |
79 | BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */ |
80 | BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */ | |
1da177e4 LT |
81 | BUILD_IRQ(18, 0x40000) |
82 | BUILD_IRQ(19, 0x80000) | |
83 | BUILD_IRQ(20, 0x100000) | |
84 | BUILD_IRQ(21, 0x200000) | |
85 | BUILD_IRQ(22, 0x400000) | |
86 | BUILD_IRQ(23, 0x800000) | |
87 | BUILD_IRQ(24, 0x1000000) | |
88 | BUILD_IRQ(25, 0x2000000) | |
89 | /* IRQ 26-30 are reserved */ | |
90 | BUILD_IRQ(31, 0x80000000) | |
91 | ||
92 | /* | |
93 | * Pointers to the low-level handlers | |
94 | */ | |
95 | ||
96 | static void (*interrupt[NR_IRQS])(void) = { | |
97 | NULL, NULL, IRQ2_interrupt, IRQ3_interrupt, | |
98 | IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt, | |
99 | IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt, | |
100 | IRQ12_interrupt, IRQ13_interrupt, NULL, NULL, | |
101 | IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt, | |
102 | IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt, | |
103 | IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL, | |
104 | IRQ31_interrupt | |
105 | }; | |
106 | ||
2e0cea1d MS |
107 | static void enable_crisv10_irq(unsigned int irq); |
108 | ||
109 | static unsigned int startup_crisv10_irq(unsigned int irq) | |
110 | { | |
111 | enable_crisv10_irq(irq); | |
112 | return 0; | |
113 | } | |
114 | ||
115 | #define shutdown_crisv10_irq disable_crisv10_irq | |
1da177e4 | 116 | |
2e0cea1d | 117 | static void enable_crisv10_irq(unsigned int irq) |
1da177e4 | 118 | { |
4150764f | 119 | crisv10_unmask_irq(irq); |
1da177e4 LT |
120 | } |
121 | ||
2e0cea1d | 122 | static void disable_crisv10_irq(unsigned int irq) |
1da177e4 | 123 | { |
4150764f | 124 | crisv10_mask_irq(irq); |
1da177e4 LT |
125 | } |
126 | ||
2e0cea1d MS |
127 | static void ack_crisv10_irq(unsigned int irq) |
128 | { | |
129 | } | |
130 | ||
131 | static void end_crisv10_irq(unsigned int irq) | |
132 | { | |
133 | } | |
134 | ||
c01ce829 | 135 | static struct irq_chip crisv10_irq_type = { |
d8fe989e | 136 | .name = "CRISv10", |
2e0cea1d MS |
137 | .startup = startup_crisv10_irq, |
138 | .shutdown = shutdown_crisv10_irq, | |
139 | .enable = enable_crisv10_irq, | |
140 | .disable = disable_crisv10_irq, | |
141 | .ack = ack_crisv10_irq, | |
142 | .end = end_crisv10_irq, | |
143 | .set_affinity = NULL | |
144 | }; | |
145 | ||
1da177e4 LT |
146 | void weird_irq(void); |
147 | void system_call(void); /* from entry.S */ | |
148 | void do_sigtrap(void); /* from entry.S */ | |
149 | void gdb_handle_breakpoint(void); /* from entry.S */ | |
150 | ||
7b275523 JN |
151 | extern void do_IRQ(int irq, struct pt_regs * regs); |
152 | ||
153 | /* Handle multiple IRQs */ | |
154 | void do_multiple_IRQ(struct pt_regs* regs) | |
155 | { | |
156 | int bit; | |
157 | unsigned masked; | |
158 | unsigned mask; | |
159 | unsigned ethmask = 0; | |
160 | ||
161 | /* Get interrupts to mask and handle */ | |
162 | mask = masked = *R_VECT_MASK_RD; | |
163 | ||
164 | /* Never mask timer IRQ */ | |
165 | mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0)); | |
166 | ||
167 | /* | |
168 | * If either ethernet interrupt (rx or tx) is active then block | |
169 | * the other one too. Unblock afterwards also. | |
170 | */ | |
171 | if (mask & | |
172 | (IO_STATE(R_VECT_MASK_RD, dma0, active) | | |
173 | IO_STATE(R_VECT_MASK_RD, dma1, active))) { | |
174 | ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) | | |
175 | IO_MASK(R_VECT_MASK_RD, dma1)); | |
176 | } | |
177 | ||
178 | /* Block them */ | |
179 | *R_VECT_MASK_CLR = (mask | ethmask); | |
180 | ||
181 | /* An extra irq_enter here to prevent softIRQs to run after | |
182 | * each do_IRQ. This will decrease the interrupt latency. | |
183 | */ | |
184 | irq_enter(); | |
185 | ||
186 | /* Handle all IRQs */ | |
187 | for (bit = 2; bit < 32; bit++) { | |
188 | if (masked & (1 << bit)) { | |
189 | do_IRQ(bit, regs); | |
190 | } | |
191 | } | |
192 | ||
193 | /* This irq_exit() will trigger the soft IRQs. */ | |
194 | irq_exit(); | |
195 | ||
196 | /* Unblock the IRQs again */ | |
197 | *R_VECT_MASK_SET = (masked | ethmask); | |
198 | } | |
199 | ||
1da177e4 | 200 | /* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and |
2e0cea1d | 201 | setting the irq vector table. |
1da177e4 LT |
202 | */ |
203 | ||
204 | void __init | |
205 | init_IRQ(void) | |
206 | { | |
207 | int i; | |
208 | ||
209 | /* clear all interrupt masks */ | |
210 | ||
211 | #ifndef CONFIG_SVINTO_SIM | |
212 | *R_IRQ_MASK0_CLR = 0xffffffff; | |
213 | *R_IRQ_MASK1_CLR = 0xffffffff; | |
214 | *R_IRQ_MASK2_CLR = 0xffffffff; | |
215 | #endif | |
216 | ||
217 | *R_VECT_MASK_CLR = 0xffffffff; | |
218 | ||
1da177e4 LT |
219 | for (i = 0; i < 256; i++) |
220 | etrax_irv->v[i] = weird_irq; | |
221 | ||
49b4ff33 | 222 | /* Initialize IRQ handler descriptors. */ |
2e0cea1d | 223 | for(i = 2; i < NR_IRQS; i++) { |
d1bef4ed | 224 | irq_desc[i].chip = &crisv10_irq_type; |
2e0cea1d MS |
225 | set_int_vector(i, interrupt[i]); |
226 | } | |
227 | ||
1da177e4 LT |
228 | /* the entries in the break vector contain actual code to be |
229 | executed by the associated break handler, rather than just a jump | |
230 | address. therefore we need to setup a default breakpoint handler | |
231 | for all breakpoints */ | |
232 | ||
233 | for (i = 0; i < 16; i++) | |
234 | set_break_vector(i, do_sigtrap); | |
235 | ||
1da177e4 LT |
236 | /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */ |
237 | ||
238 | set_int_vector(15, multiple_interrupt); | |
239 | ||
240 | /* 0 and 1 which are special breakpoint/NMI traps */ | |
241 | ||
242 | set_int_vector(0, hwbreakpoint); | |
243 | set_int_vector(1, IRQ1_interrupt); | |
244 | ||
245 | /* and irq 14 which is the mmu bus fault handler */ | |
246 | ||
247 | set_int_vector(14, mmu_bus_fault); | |
248 | ||
249 | /* setup the system-call trap, which is reached by BREAK 13 */ | |
250 | ||
251 | set_break_vector(13, system_call); | |
252 | ||
253 | /* setup a breakpoint handler for debugging used for both user and | |
254 | kernel mode debugging (which is why it is not inside an ifdef | |
255 | CONFIG_ETRAX_KGDB) */ | |
256 | set_break_vector(8, gdb_handle_breakpoint); | |
257 | ||
258 | #ifdef CONFIG_ETRAX_KGDB | |
259 | /* setup kgdb if its enabled, and break into the debugger */ | |
260 | kgdb_init(); | |
261 | breakpoint(); | |
262 | #endif | |
263 | } |