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Blackfin: add support for the Acvilon BF561 board
[net-next-2.6.git] / arch / blackfin / mach-bf561 / boards / acvilon.c
CommitLineData
ab843c79
VY		 1/*
2 * File: arch/blackfin/mach-bf561/acvilon.c
3 * Based on: arch/blackfin/mach-bf561/ezkit.c
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 * Copyright 2009 CJSC "NII STT"
12 *
13 * Bugs:
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 *
30 *
31 * For more information about Acvilon BF561 SoM please
32 * go to http://www.niistt.ru/
33 *
34 */
35
36#include <linux/device.h>
37#include <linux/platform_device.h>
38#include <linux/mtd/mtd.h>
39#include <linux/mtd/partitions.h>
40#include <linux/mtd/physmap.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/plat-ram.h>
43#include <linux/spi/spi.h>
44#include <linux/spi/flash.h>
45#include <linux/irq.h>
46#include <linux/interrupt.h>
47#include <linux/i2c-pca-platform.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <asm/dma.h>
51#include <asm/bfin5xx_spi.h>
52#include <asm/portmux.h>
53#include <asm/dpmc.h>
54#include <asm/cacheflush.h>
55#include <linux/i2c.h>
56
57/*
58 * Name the Board for the /proc/cpuinfo
59 */
60const char bfin_board_name[] = "Acvilon board";
61
62#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
63#include <linux/usb/isp1760.h>
64static struct resource bfin_isp1760_resources[] = {
65 [0] = {
66 .start = 0x20000000,
67 .end = 0x20000000 + 0x000fffff,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = IRQ_PF15,
72 .end = IRQ_PF15,
73 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
74 },
75};
76
77static struct isp1760_platform_data isp1760_priv = {
78 .is_isp1761 = 0,
79 .port1_disable = 0,
80 .bus_width_16 = 1,
81 .port1_otg = 0,
82 .analog_oc = 0,
83 .dack_polarity_high = 0,
84 .dreq_polarity_high = 0,
85};
86
87static struct platform_device bfin_isp1760_device = {
88 .name = "isp1760-hcd",
89 .id = 0,
90 .dev = {
91 .platform_data = &isp1760_priv,
92 },
93 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
94 .resource = bfin_isp1760_resources,
95};
96#endif
97
98static struct resource bfin_i2c_pca_resources[] = {
99 {
100 .name = "pca9564-regs",
101 .start = 0x2C000000,
102 .end = 0x2C000000 + 16,
103 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
104 }, {
105
106 .start = IRQ_PF8,
107 .end = IRQ_PF8,
108 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
109 },
110};
111
112struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
113 .gpio = -1,
114 .i2c_clock_speed = 330000,
115 .timeout = 10000
116};
117
118/* PCA9564 I2C Bus driver */
119static struct platform_device bfin_i2c_pca_device = {
120 .name = "i2c-pca-platform",
121 .id = 0,
122 .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
123 .resource = bfin_i2c_pca_resources,
124 .dev = {
125 .platform_data = &pca9564_platform_data,
126 }
127};
128
129/* I2C devices fitted. */
130static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
131 {
132 I2C_BOARD_INFO("ds1339", 0x68),
133 },
134 {
135 I2C_BOARD_INFO("tcn75", 0x49),
136 },
137};
138
139#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
140static struct platdata_mtd_ram mtd_ram_data = {
141 .mapname = "rootfs(RAM)",
142 .bankwidth = 4,
143};
144
145static struct resource mtd_ram_resource = {
146 .start = 0x4000000,
147 .end = 0x5ffffff,
148 .flags = IORESOURCE_MEM,
149};
150
151static struct platform_device mtd_ram_device = {
152 .name = "mtd-ram",
153 .id = 0,
154 .dev = {
155 .platform_data = &mtd_ram_data,
156 },
157 .num_resources = 1,
158 .resource = &mtd_ram_resource,
159};
160#endif
161
162#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
163#include <linux/smsc911x.h>
164static struct resource smsc911x_resources[] = {
165 {
166 .name = "smsc911x-memory",
167 .start = 0x28000000,
168 .end = 0x28000000 + 0xFF,
169 .flags = IORESOURCE_MEM,
170 },
171 {
172 .start = IRQ_PF7,
173 .end = IRQ_PF7,
174 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
175 },
176};
177
178static struct smsc911x_platform_config smsc911x_config = {
179 .flags = SMSC911X_USE_32BIT,
180 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
181 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
182 .phy_interface = PHY_INTERFACE_MODE_MII,
183};
184
185static struct platform_device smsc911x_device = {
186 .name = "smsc911x",
187 .id = 0,
188 .num_resources = ARRAY_SIZE(smsc911x_resources),
189 .resource = smsc911x_resources,
190 .dev = {
191 .platform_data = &smsc911x_config,
192 },
193};
194#endif
195
196#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
197#ifdef CONFIG_SERIAL_BFIN_UART0
198static struct resource bfin_uart0_resources[] = {
199 {
200 .start = BFIN_UART_THR,
201 .end = BFIN_UART_GCTL + 2,
202 .flags = IORESOURCE_MEM,
203 },
204 {
205 .start = IRQ_UART_RX,
206 .end = IRQ_UART_RX + 1,
207 .flags = IORESOURCE_IRQ,
208 },
209 {
210 .start = IRQ_UART_ERROR,
211 .end = IRQ_UART_ERROR,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .start = CH_UART_TX,
216 .end = CH_UART_TX,
217 .flags = IORESOURCE_DMA,
218 },
219 {
220 .start = CH_UART_RX,
221 .end = CH_UART_RX,
222 .flags = IORESOURCE_DMA,
223 },
224};
225
226unsigned short bfin_uart0_peripherals[] = {
227 P_UART0_TX, P_UART0_RX, 0
228};
229
230static struct platform_device bfin_uart0_device = {
231 .name = "bfin-uart",
232 .id = 0,
233 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
234 .resource = bfin_uart0_resources,
235 .dev = {
236 /* Passed to driver */
237 .platform_data = &bfin_uart0_peripherals,
238 },
239};
240#endif
241#endif
242
243#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
244
245#ifdef CONFIG_MTD_PARTITIONS
246const char *part_probes[] = { "cmdlinepart", NULL };
247
248static struct mtd_partition bfin_plat_nand_partitions[] = {
249 {
250 .name = "params(nand)",
251 .size = 32 * 1024 * 1024,
252 .offset = 0,
253 }, {
254 .name = "userfs(nand)",
255 .size = MTDPART_SIZ_FULL,
256 .offset = MTDPART_OFS_APPEND,
257 },
258};
259#endif
260
261#define BFIN_NAND_PLAT_CLE 2
262#define BFIN_NAND_PLAT_ALE 3
263
264static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
265 unsigned int ctrl)
266{
267 struct nand_chip *this = mtd->priv;
268
269 if (cmd == NAND_CMD_NONE)
270 return;
271
272 if (ctrl & NAND_CLE)
273 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
274 else
275 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
276}
277
278#define BFIN_NAND_PLAT_READY GPIO_PF10
279static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
280{
281 return gpio_get_value(BFIN_NAND_PLAT_READY);
282}
283
284static struct platform_nand_data bfin_plat_nand_data = {
285 .chip = {
286 .chip_delay = 30,
287#ifdef CONFIG_MTD_PARTITIONS
288 .part_probe_types = part_probes,
289 .partitions = bfin_plat_nand_partitions,
290 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
291#endif
292 },
293 .ctrl = {
294 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
295 .dev_ready = bfin_plat_nand_dev_ready,
296 },
297};
298
299#define MAX(x, y) (x > y ? x : y)
300static struct resource bfin_plat_nand_resources = {
301 .start = 0x24000000,
302 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
303 .flags = IORESOURCE_IO,
304};
305
306static struct platform_device bfin_async_nand_device = {
307 .name = "gen_nand",
308 .id = -1,
309 .num_resources = 1,
310 .resource = &bfin_plat_nand_resources,
311 .dev = {
312 .platform_data = &bfin_plat_nand_data,
313 },
314};
315
316static void bfin_plat_nand_init(void)
317{
318 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
319}
320#else
321static void bfin_plat_nand_init(void)
322{
323}
324#endif
325
326#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
327static struct mtd_partition bfin_spi_dataflash_partitions[] = {
328 {
329 .name = "bootloader",
330 .size = 0x4200,
331 .offset = 0,
332 .mask_flags = MTD_CAP_ROM},
333 {
334 .name = "u-boot",
335 .size = 0x42000,
336 .offset = MTDPART_OFS_APPEND,
337 },
338 {
339 .name = "u-boot(params)",
340 .size = 0x4200,
341 .offset = MTDPART_OFS_APPEND,
342 },
343 {
344 .name = "kernel",
345 .size = 0x294000,
346 .offset = MTDPART_OFS_APPEND,
347 },
348 {
349 .name = "params",
350 .size = 0x42000,
351 .offset = MTDPART_OFS_APPEND,
352 },
353 {
354 .name = "rootfs",
355 .size = MTDPART_SIZ_FULL,
356 .offset = MTDPART_OFS_APPEND,
357 }
358};
359
360static struct flash_platform_data bfin_spi_dataflash_data = {
361 .name = "SPI Dataflash",
362 .parts = bfin_spi_dataflash_partitions,
363 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
364};
365
366/* DataFlash chip */
367static struct bfin5xx_spi_chip data_flash_chip_info = {
368 .enable_dma = 0, /* use dma transfer with this chip */
369 .bits_per_word = 8,
370};
371#endif
372
373#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
374static struct bfin5xx_spi_chip spidev_chip_info = {
375 .enable_dma = 0,
376 .bits_per_word = 8,
377};
378#endif
379
380#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
381/* SPI (0) */
382static struct resource bfin_spi0_resource[] = {
383 [0] = {
384 .start = SPI0_REGBASE,
385 .end = SPI0_REGBASE + 0xFF,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = CH_SPI,
390 .end = CH_SPI,
391 .flags = IORESOURCE_DMA,
392 },
393 [2] = {
394 .start = IRQ_SPI,
395 .end = IRQ_SPI,
396 .flags = IORESOURCE_IRQ,
397 },
398};
399
400/* SPI controller data */
401static struct bfin5xx_spi_master bfin_spi0_info = {
402 .num_chipselect = 8,
403 .enable_dma = 1, /* master has the ability to do dma transfer */
404 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
405};
406
407static struct platform_device bfin_spi0_device = {
408 .name = "bfin-spi",
409 .id = 0, /* Bus number */
410 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
411 .resource = bfin_spi0_resource,
412 .dev = {
413 .platform_data = &bfin_spi0_info, /* Passed to driver */
414 },
415};
416#endif
417
418static struct spi_board_info bfin_spi_board_info[] __initdata = {
419#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
420 {
421 .modalias = "spidev",
422 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
423 .bus_num = 0,
424 .chip_select = 3,
425 .controller_data = &spidev_chip_info,
426 },
427#endif
428#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
429 { /* DataFlash chip */
430 .modalias = "mtd_dataflash",
431 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
432 .bus_num = 0, /* Framework bus number */
433 .chip_select = 2, /* Framework chip select */
434 .platform_data = &bfin_spi_dataflash_data,
435 .controller_data = &data_flash_chip_info,
436 .mode = SPI_MODE_3,
437 },
438#endif
439};
440
441static struct resource bfin_gpios_resources = {
442 .start = 31,
443/* .end = MAX_BLACKFIN_GPIOS - 1, */
444 .end = 32,
445 .flags = IORESOURCE_IRQ,
446};
447
448static struct platform_device bfin_gpios_device = {
449 .name = "simple-gpio",
450 .id = -1,
451 .num_resources = 1,
452 .resource = &bfin_gpios_resources,
453};
454
455static const unsigned int cclk_vlev_datasheet[] = {
456 VRPAIR(VLEV_085, 250000000),
457 VRPAIR(VLEV_090, 300000000),
458 VRPAIR(VLEV_095, 313000000),
459 VRPAIR(VLEV_100, 350000000),
460 VRPAIR(VLEV_105, 400000000),
461 VRPAIR(VLEV_110, 444000000),
462 VRPAIR(VLEV_115, 450000000),
463 VRPAIR(VLEV_120, 475000000),
464 VRPAIR(VLEV_125, 500000000),
465 VRPAIR(VLEV_130, 600000000),
466};
467
468static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
469 .tuple_tab = cclk_vlev_datasheet,
470 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
471 .vr_settling_time = 25 /* us */ ,
472};
473
474static struct platform_device bfin_dpmc = {
475 .name = "bfin dpmc",
476 .dev = {
477 .platform_data = &bfin_dmpc_vreg_data,
478 },
479};
480
481static struct platform_device *acvilon_devices[] __initdata = {
482 &bfin_dpmc,
483
484#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
485 &bfin_spi0_device,
486#endif
487
488#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
489#ifdef CONFIG_SERIAL_BFIN_UART0
490 &bfin_uart0_device,
491#endif
492#endif
493
494 &bfin_gpios_device,
495
496#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
497 &smsc911x_device,
498#endif
499
500 &bfin_i2c_pca_device,
501
502#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
503 &bfin_async_nand_device,
504#endif
505
506#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
507 &mtd_ram_device,
508#endif
509
510};
511
512static int __init acvilon_init(void)
513{
514 int ret;
515
516 printk(KERN_INFO "%s(): registering device resources\n", __func__);
517
518 bfin_plat_nand_init();
519 ret =
520 platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
521 if (ret < 0)
522 return ret;
523
524 i2c_register_board_info(0, acvilon_i2c_devs,
525 ARRAY_SIZE(acvilon_i2c_devs));
526
527 bfin_write_FIO0_FLAG_C(1 << 14);
528 msleep(5);
529 bfin_write_FIO0_FLAG_S(1 << 14);
530
531 spi_register_board_info(bfin_spi_board_info,
532 ARRAY_SIZE(bfin_spi_board_info));
533 return 0;
534}
535
536arch_initcall(acvilon_init);
537
538static struct platform_device *acvilon_early_devices[] __initdata = {
539#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
540#ifdef CONFIG_SERIAL_BFIN_UART0
541 &bfin_uart0_device,
542#endif
543#endif
544};
545
546void __init native_machine_early_platform_add_devices(void)
547{
548 printk(KERN_INFO "register early platform devices\n");
549 early_platform_add_devices(acvilon_early_devices,
550 ARRAY_SIZE(acvilon_early_devices));
551}
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