]> bbs.cooldavid.org Git - net-next-2.6.git/blame - arch/blackfin/mach-bf537/boards/cm_bf537e.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Blackfin: rename AD1836 to AD183X in board files
[net-next-2.6.git] / arch / blackfin / mach-bf537 / boards / cm_bf537e.c
CommitLineData
1394f032 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
1394f032 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
1394f032
BW		 8 */
9
10#include <linux/device.h>
43f73fef 11#include <linux/etherdevice.h>
1394f032
BW		 12#include <linux/platform_device.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
8ea89497 15#include <linux/mtd/physmap.h>
1394f032
BW		 16#include <linux/spi/spi.h>
17#include <linux/spi/flash.h>
b964c592 18#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 19#include <linux/usb/isp1362.h>
b964c592 20#endif
0a87e3e9 21#include <linux/ata_platform.h>
1f83b8f1 22#include <linux/irq.h>
c6c4d7bb 23#include <asm/dma.h>
1394f032 24#include <asm/bfin5xx_spi.h>
5d448dd5 25#include <asm/portmux.h>
14b03204 26#include <asm/dpmc.h>
1394f032
BW		 27
28/*
29 * Name the Board for the /proc/cpuinfo
30 */
60584344 31const char bfin_board_name[] = "Bluetechnix CM BF537E";
1394f032
BW		 32
33#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
34/* all SPI peripherals info goes here */
35
36#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
37static struct mtd_partition bfin_spi_flash_partitions[] = {
38 {
aa582977 39 .name = "bootloader(spi)",
1394f032
BW		 40 .size = 0x00020000,
41 .offset = 0,
42 .mask_flags = MTD_CAP_ROM
1f83b8f1 43 }, {
aa582977 44 .name = "linux kernel(spi)",
1394f032
BW		 45 .size = 0xe0000,
46 .offset = 0x20000
1f83b8f1 47 }, {
aa582977 48 .name = "file system(spi)",
1394f032
BW		 49 .size = 0x700000,
50 .offset = 0x00100000,
51 }
52};
53
54static struct flash_platform_data bfin_spi_flash_data = {
55 .name = "m25p80",
56 .parts = bfin_spi_flash_partitions,
57 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
58 .type = "m25p64",
59};
60
61/* SPI flash chip (m25p64) */
62static struct bfin5xx_spi_chip spi_flash_chip_info = {
63 .enable_dma = 0, /* use dma transfer with this chip*/
64 .bits_per_word = 8,
65};
66#endif
67
a261eec0 68#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 69/* SPI ADC chip */
70static struct bfin5xx_spi_chip spi_adc_chip_info = {
71 .enable_dma = 1, /* use dma transfer with this chip*/
72 .bits_per_word = 16,
73};
74#endif
75
d40bd71f 76#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
1394f032
BW		 77static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
78 .enable_dma = 0,
79 .bits_per_word = 16,
80};
81#endif
82
f3f704d3
MH		 83#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
84static struct bfin5xx_spi_chip mmc_spi_chip_info = {
85 .enable_dma = 0,
1394f032
BW		 86 .bits_per_word = 8,
87};
88#endif
89
90static struct spi_board_info bfin_spi_board_info[] __initdata = {
91#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
92 {
93 /* the modalias must be the same as spi device driver name */
94 .modalias = "m25p80", /* Name of spi_driver for this device */
95 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 96 .bus_num = 0, /* Framework bus number */
1394f032
BW		 97 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
98 .platform_data = &bfin_spi_flash_data,
99 .controller_data = &spi_flash_chip_info,
100 .mode = SPI_MODE_3,
101 },
102#endif
103
a261eec0 104#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 105 {
106 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
107 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 108 .bus_num = 0, /* Framework bus number */
1394f032
BW		 109 .chip_select = 1, /* Framework chip select. */
110 .platform_data = NULL, /* No spi_driver specific config */
111 .controller_data = &spi_adc_chip_info,
112 },
113#endif
114
d40bd71f 115#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
1394f032 116 {
dac98174 117 .modalias = "ad1836",
1394f032 118 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 119 .bus_num = 0,
1394f032
BW		 120 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
121 .controller_data = &ad1836_spi_chip_info,
122 },
123#endif
124
f3f704d3 125#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
1394f032 126 {
f3f704d3
MH		 127 .modalias = "mmc_spi",
128 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 129 .bus_num = 0,
f3f704d3
MH		 130 .chip_select = 1,
131 .controller_data = &mmc_spi_chip_info,
1394f032
BW		 132 .mode = SPI_MODE_3,
133 },
134#endif
135};
136
c6c4d7bb
BW		 137/* SPI (0) */
138static struct resource bfin_spi0_resource[] = {
139 [0] = {
140 .start = SPI0_REGBASE,
141 .end = SPI0_REGBASE + 0xFF,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 .start = CH_SPI,
146 .end = CH_SPI,
53122693
YL		 147 .flags = IORESOURCE_DMA,
148 },
149 [2] = {
150 .start = IRQ_SPI,
151 .end = IRQ_SPI,
c6c4d7bb 152 .flags = IORESOURCE_IRQ,
53122693 153 },
c6c4d7bb
BW		 154};
155
1394f032 156/* SPI controller data */
c6c4d7bb 157static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 158 .num_chipselect = 8,
159 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 160 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 161};
162
c6c4d7bb
BW		 163static struct platform_device bfin_spi0_device = {
164 .name = "bfin-spi",
165 .id = 0, /* Bus number */
166 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
167 .resource = bfin_spi0_resource,
1394f032 168 .dev = {
c6c4d7bb 169 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 170 },
171};
172#endif /* spi master and devices */
173
174#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
175static struct platform_device rtc_device = {
176 .name = "rtc-bfin",
177 .id = -1,
178};
179#endif
180
0d4a89bb
MH		 181#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
182static struct platform_device hitachi_fb_device = {
183 .name = "hitachi-tx09",
184};
185#endif
186
1394f032 187#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 188#include <linux/smc91x.h>
189
190static struct smc91x_platdata smc91x_info = {
191 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
192 .leda = RPC_LED_100_10,
193 .ledb = RPC_LED_TX_RX,
194};
195
1394f032
BW		 196static struct resource smc91x_resources[] = {
197 {
198 .start = 0x20200300,
199 .end = 0x20200300 + 16,
200 .flags = IORESOURCE_MEM,
1f83b8f1 201 }, {
1394f032
BW		 202 .start = IRQ_PF14,
203 .end = IRQ_PF14,
204 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
205 },
206};
207
208static struct platform_device smc91x_device = {
209 .name = "smc91x",
210 .id = 0,
211 .num_resources = ARRAY_SIZE(smc91x_resources),
212 .resource = smc91x_resources,
61f09b5a
MH		 213 .dev = {
214 .platform_data = &smc91x_info,
215 },
1394f032
BW		 216};
217#endif
218
219#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
220static struct resource isp1362_hcd_resources[] = {
221 {
222 .start = 0x20308000,
223 .end = 0x20308000,
224 .flags = IORESOURCE_MEM,
1f83b8f1 225 }, {
1394f032
BW		 226 .start = 0x20308004,
227 .end = 0x20308004,
228 .flags = IORESOURCE_MEM,
1f83b8f1 229 }, {
1394f032
BW		 230 .start = IRQ_PG15,
231 .end = IRQ_PG15,
232 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
233 },
234};
235
236static struct isp1362_platform_data isp1362_priv = {
237 .sel15Kres = 1,
238 .clknotstop = 0,
239 .oc_enable = 0,
240 .int_act_high = 0,
241 .int_edge_triggered = 0,
242 .remote_wakeup_connected = 0,
243 .no_power_switching = 1,
244 .power_switching_mode = 0,
245};
246
247static struct platform_device isp1362_hcd_device = {
248 .name = "isp1362-hcd",
249 .id = 0,
250 .dev = {
251 .platform_data = &isp1362_priv,
252 },
253 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
254 .resource = isp1362_hcd_resources,
255};
256#endif
257
258#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
259static struct resource net2272_bfin_resources[] = {
260 {
60584344
HK		 261 .start = 0x20300000,
262 .end = 0x20300000 + 0x100,
1394f032 263 .flags = IORESOURCE_MEM,
1f83b8f1 264 }, {
60584344
HK		 265 .start = IRQ_PG13,
266 .end = IRQ_PG13,
1394f032
BW		 267 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
268 },
269};
270
271static struct platform_device net2272_bfin_device = {
272 .name = "net2272",
273 .id = -1,
274 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
275 .resource = net2272_bfin_resources,
276};
277#endif
278
8ea89497
MF		 279#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
280static struct mtd_partition cm_partitions[] = {
281 {
282 .name = "bootloader(nor)",
283 .size = 0x40000,
284 .offset = 0,
285 }, {
286 .name = "linux kernel(nor)",
60584344 287 .size = 0x100000,
8ea89497
MF		 288 .offset = MTDPART_OFS_APPEND,
289 }, {
290 .name = "file system(nor)",
291 .size = MTDPART_SIZ_FULL,
292 .offset = MTDPART_OFS_APPEND,
293 }
294};
295
296static struct physmap_flash_data cm_flash_data = {
297 .width = 2,
298 .parts = cm_partitions,
299 .nr_parts = ARRAY_SIZE(cm_partitions),
300};
301
302static unsigned cm_flash_gpios[] = { GPIO_PF4 };
303
304static struct resource cm_flash_resource[] = {
305 {
306 .name = "cfi_probe",
307 .start = 0x20000000,
308 .end = 0x201fffff,
309 .flags = IORESOURCE_MEM,
310 }, {
311 .start = (unsigned long)cm_flash_gpios,
312 .end = ARRAY_SIZE(cm_flash_gpios),
313 .flags = IORESOURCE_IRQ,
314 }
315};
316
317static struct platform_device cm_flash_device = {
318 .name = "gpio-addr-flash",
319 .id = 0,
320 .dev = {
321 .platform_data = &cm_flash_data,
322 },
323 .num_resources = ARRAY_SIZE(cm_flash_resource),
324 .resource = cm_flash_resource,
325};
326#endif
327
1394f032 328#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
60584344
HK		 329#ifdef CONFIG_SERIAL_BFIN_UART0
330static struct resource bfin_uart0_resources[] = {
1394f032 331 {
6bd1fbea
SZ		 332 .start = UART0_THR,
333 .end = UART0_GCTL+2,
1394f032 334 .flags = IORESOURCE_MEM,
60584344
HK		 335 },
336 {
337 .start = IRQ_UART0_RX,
338 .end = IRQ_UART0_RX+1,
339 .flags = IORESOURCE_IRQ,
340 },
341 {
342 .start = IRQ_UART0_ERROR,
343 .end = IRQ_UART0_ERROR,
344 .flags = IORESOURCE_IRQ,
345 },
346 {
347 .start = CH_UART0_TX,
348 .end = CH_UART0_TX,
349 .flags = IORESOURCE_DMA,
350 },
351 {
352 .start = CH_UART0_RX,
353 .end = CH_UART0_RX,
354 .flags = IORESOURCE_DMA,
355 },
356#ifdef CONFIG_BFIN_UART0_CTSRTS
357 {
358 /*
359 * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
360 */
361 .start = -1,
362 .end = -1,
363 .flags = IORESOURCE_IO,
364 },
365 {
366 /*
367 * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
368 */
369 .start = -1,
370 .end = -1,
371 .flags = IORESOURCE_IO,
372 },
373#endif
374};
375
6bd1fbea
SZ		 376unsigned short bfin_uart0_peripherals[] = {
377 P_UART0_TX, P_UART0_RX, 0
378};
379
60584344
HK		 380static struct platform_device bfin_uart0_device = {
381 .name = "bfin-uart",
382 .id = 0,
383 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
384 .resource = bfin_uart0_resources,
6bd1fbea
SZ		 385 .dev = {
386 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
387 },
60584344
HK		 388};
389#endif
390#ifdef CONFIG_SERIAL_BFIN_UART1
391static struct resource bfin_uart1_resources[] = {
392 {
6bd1fbea
SZ		 393 .start = UART1_THR,
394 .end = UART1_GCTL+2,
1394f032
BW		 395 .flags = IORESOURCE_MEM,
396 },
60584344
HK		 397 {
398 .start = IRQ_UART1_RX,
399 .end = IRQ_UART1_RX+1,
400 .flags = IORESOURCE_IRQ,
401 },
402 {
403 .start = IRQ_UART1_ERROR,
404 .end = IRQ_UART1_ERROR,
405 .flags = IORESOURCE_IRQ,
406 },
407 {
408 .start = CH_UART1_TX,
409 .end = CH_UART1_TX,
410 .flags = IORESOURCE_DMA,
411 },
412 {
413 .start = CH_UART1_RX,
414 .end = CH_UART1_RX,
415 .flags = IORESOURCE_DMA,
416 },
417#ifdef CONFIG_BFIN_UART1_CTSRTS
418 {
419 /*
420 * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
421 */
422 .start = -1,
423 .end = -1,
424 .flags = IORESOURCE_IO,
425 },
426 {
427 /*
428 * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
429 */
430 .start = -1,
431 .end = -1,
432 .flags = IORESOURCE_IO,
433 },
434#endif
1394f032
BW		 435};
436
6bd1fbea
SZ		 437unsigned short bfin_uart1_peripherals[] = {
438 P_UART1_TX, P_UART1_RX, 0
439};
440
60584344 441static struct platform_device bfin_uart1_device = {
1394f032
BW		 442 .name = "bfin-uart",
443 .id = 1,
60584344
HK		 444 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
445 .resource = bfin_uart1_resources,
6bd1fbea
SZ		 446 .dev = {
447 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
448 },
1394f032
BW		 449};
450#endif
60584344 451#endif
1394f032 452
5be36d22 453#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 454#ifdef CONFIG_BFIN_SIR0
42bd8bcb 455static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 456 {
457 .start = 0xFFC00400,
458 .end = 0xFFC004FF,
459 .flags = IORESOURCE_MEM,
460 },
42bd8bcb
GY		 461 {
462 .start = IRQ_UART0_RX,
463 .end = IRQ_UART0_RX+1,
464 .flags = IORESOURCE_IRQ,
465 },
466 {
467 .start = CH_UART0_RX,
468 .end = CH_UART0_RX+1,
469 .flags = IORESOURCE_DMA,
470 },
471};
472static struct platform_device bfin_sir0_device = {
473 .name = "bfin_sir",
474 .id = 0,
475 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
476 .resource = bfin_sir0_resources,
477};
5be36d22
GY		 478#endif
479#ifdef CONFIG_BFIN_SIR1
42bd8bcb 480static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 481 {
482 .start = 0xFFC02000,
483 .end = 0xFFC020FF,
484 .flags = IORESOURCE_MEM,
485 },
42bd8bcb
GY		 486 {
487 .start = IRQ_UART1_RX,
488 .end = IRQ_UART1_RX+1,
489 .flags = IORESOURCE_IRQ,
490 },
491 {
492 .start = CH_UART1_RX,
493 .end = CH_UART1_RX+1,
494 .flags = IORESOURCE_DMA,
495 },
5be36d22 496};
42bd8bcb 497static struct platform_device bfin_sir1_device = {
5be36d22 498 .name = "bfin_sir",
42bd8bcb
GY		 499 .id = 1,
500 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
501 .resource = bfin_sir1_resources,
5be36d22
GY		 502};
503#endif
42bd8bcb 504#endif
5be36d22 505
56ce835b
MF		 506#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
507static struct resource bfin_twi0_resource[] = {
508 [0] = {
509 .start = TWI0_REGBASE,
510 .end = TWI0_REGBASE,
511 .flags = IORESOURCE_MEM,
512 },
513 [1] = {
514 .start = IRQ_TWI,
515 .end = IRQ_TWI,
516 .flags = IORESOURCE_IRQ,
517 },
518};
519
520static struct platform_device i2c_bfin_twi_device = {
521 .name = "i2c-bfin-twi",
522 .id = 0,
523 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
524 .resource = bfin_twi0_resource,
525};
526#endif
527
1394f032 528#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 529#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
530static struct resource bfin_sport0_uart_resources[] = {
531 {
532 .start = SPORT0_TCR1,
533 .end = SPORT0_MRCS3+4,
534 .flags = IORESOURCE_MEM,
535 },
536 {
537 .start = IRQ_SPORT0_RX,
538 .end = IRQ_SPORT0_RX+1,
539 .flags = IORESOURCE_IRQ,
540 },
541 {
542 .start = IRQ_SPORT0_ERROR,
543 .end = IRQ_SPORT0_ERROR,
544 .flags = IORESOURCE_IRQ,
545 },
546};
547
548unsigned short bfin_sport0_peripherals[] = {
549 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
550 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
551};
552
1394f032
BW		 553static struct platform_device bfin_sport0_uart_device = {
554 .name = "bfin-sport-uart",
555 .id = 0,
df5de261
SZ		 556 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
557 .resource = bfin_sport0_uart_resources,
558 .dev = {
559 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
560 },
561};
562#endif
563#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
564static struct resource bfin_sport1_uart_resources[] = {
565 {
566 .start = SPORT1_TCR1,
567 .end = SPORT1_MRCS3+4,
568 .flags = IORESOURCE_MEM,
569 },
570 {
571 .start = IRQ_SPORT1_RX,
572 .end = IRQ_SPORT1_RX+1,
573 .flags = IORESOURCE_IRQ,
574 },
575 {
576 .start = IRQ_SPORT1_ERROR,
577 .end = IRQ_SPORT1_ERROR,
578 .flags = IORESOURCE_IRQ,
579 },
580};
581
582unsigned short bfin_sport1_peripherals[] = {
583 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
584 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
1394f032
BW		 585};
586
587static struct platform_device bfin_sport1_uart_device = {
588 .name = "bfin-sport-uart",
589 .id = 1,
df5de261
SZ		 590 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
591 .resource = bfin_sport1_uart_resources,
592 .dev = {
593 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
594 },
1394f032
BW		 595};
596#endif
df5de261 597#endif
1394f032
BW		 598
599#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 600static struct platform_device bfin_mii_bus = {
601 .name = "bfin_mii_bus",
602};
603
1394f032
BW		 604static struct platform_device bfin_mac_device = {
605 .name = "bfin_mac",
65319628 606 .dev.platform_data = &bfin_mii_bus,
1394f032
BW		 607};
608#endif
609
c6c4d7bb 610#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
fe5aeb93 611#define PATA_INT IRQ_PF14
c6c4d7bb
BW		 612
613static struct pata_platform_info bfin_pata_platform_data = {
614 .ioport_shift = 2,
615 .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
616};
617
618static struct resource bfin_pata_resources[] = {
619 {
620 .start = 0x2030C000,
621 .end = 0x2030C01F,
622 .flags = IORESOURCE_MEM,
623 },
624 {
625 .start = 0x2030D018,
626 .end = 0x2030D01B,
627 .flags = IORESOURCE_MEM,
628 },
629 {
630 .start = PATA_INT,
631 .end = PATA_INT,
632 .flags = IORESOURCE_IRQ,
633 },
634};
635
636static struct platform_device bfin_pata_device = {
637 .name = "pata_platform",
638 .id = -1,
639 .num_resources = ARRAY_SIZE(bfin_pata_resources),
640 .resource = bfin_pata_resources,
641 .dev = {
642 .platform_data = &bfin_pata_platform_data,
643 }
644};
645#endif
646
14b03204
MH		 647static const unsigned int cclk_vlev_datasheet[] =
648{
649 VRPAIR(VLEV_085, 250000000),
650 VRPAIR(VLEV_090, 376000000),
651 VRPAIR(VLEV_095, 426000000),
652 VRPAIR(VLEV_100, 426000000),
653 VRPAIR(VLEV_105, 476000000),
654 VRPAIR(VLEV_110, 476000000),
655 VRPAIR(VLEV_115, 476000000),
656 VRPAIR(VLEV_120, 500000000),
657 VRPAIR(VLEV_125, 533000000),
658 VRPAIR(VLEV_130, 600000000),
659};
660
661static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
662 .tuple_tab = cclk_vlev_datasheet,
663 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
664 .vr_settling_time = 25 /* us */,
665};
666
667static struct platform_device bfin_dpmc = {
668 .name = "bfin dpmc",
669 .dev = {
670 .platform_data = &bfin_dmpc_vreg_data,
671 },
672};
673
60584344 674static struct platform_device *cm_bf537e_devices[] __initdata = {
14b03204
MH		 675
676 &bfin_dpmc,
677
0d4a89bb
MH		 678#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
679 &hitachi_fb_device,
680#endif
681
1394f032
BW		 682#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
683 &rtc_device,
684#endif
685
686#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
60584344
HK		 687#ifdef CONFIG_SERIAL_BFIN_UART0
688 &bfin_uart0_device,
689#endif
690#ifdef CONFIG_SERIAL_BFIN_UART1
691 &bfin_uart1_device,
692#endif
1394f032
BW		 693#endif
694
5be36d22 695#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 696#ifdef CONFIG_BFIN_SIR0
697 &bfin_sir0_device,
698#endif
699#ifdef CONFIG_BFIN_SIR1
700 &bfin_sir1_device,
701#endif
5be36d22
GY		 702#endif
703
56ce835b
MF		 704#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
705 &i2c_bfin_twi_device,
706#endif
707
1394f032 708#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 709#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1394f032 710 &bfin_sport0_uart_device,
df5de261
SZ		 711#endif
712#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1394f032
BW		 713 &bfin_sport1_uart_device,
714#endif
df5de261 715#endif
1394f032
BW		 716
717#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
718 &isp1362_hcd_device,
719#endif
720
721#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
722 &smc91x_device,
723#endif
724
725#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 726 &bfin_mii_bus,
1394f032
BW		 727 &bfin_mac_device,
728#endif
729
730#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
731 &net2272_bfin_device,
732#endif
733
734#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 735 &bfin_spi0_device,
736#endif
737
738#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
739 &bfin_pata_device,
1394f032 740#endif
8ea89497
MF		 741
742#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
743 &cm_flash_device,
744#endif
1394f032
BW		 745};
746
60584344 747static int __init cm_bf537e_init(void)
1394f032 748{
b85d858b 749 printk(KERN_INFO "%s(): registering device resources\n", __func__);
60584344 750 platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
1394f032
BW		 751#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
752 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
753#endif
c6c4d7bb
BW		 754
755#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
756 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
757#endif
1394f032
BW		 758 return 0;
759}
760
60584344 761arch_initcall(cm_bf537e_init);
137b1529 762
c13ce9fd
SZ		 763static struct platform_device *cm_bf537e_early_devices[] __initdata = {
764#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
765#ifdef CONFIG_SERIAL_BFIN_UART0
766 &bfin_uart0_device,
767#endif
768#ifdef CONFIG_SERIAL_BFIN_UART1
769 &bfin_uart1_device,
770#endif
771#endif
772
773#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
774#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
775 &bfin_sport0_uart_device,
776#endif
777#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
778 &bfin_sport1_uart_device,
779#endif
780#endif
781};
782
783void __init native_machine_early_platform_add_devices(void)
784{
785 printk(KERN_INFO "register early platform devices\n");
786 early_platform_add_devices(cm_bf537e_early_devices,
787 ARRAY_SIZE(cm_bf537e_early_devices));
788}
789
9862cc52 790void bfin_get_ether_addr(char *addr)
137b1529
MF		 791{
792 random_ether_addr(addr);
793 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
794}
9862cc52 795EXPORT_SYMBOL(bfin_get_ether_addr);
Clone of davem's net-next-2.6 tree