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[net-next-2.6.git] / arch / blackfin / mach-bf527 / boards / cm_bf527.c
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9db144fe 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
9db144fe 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
9db144fe
MH		 8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/etherdevice.h>
9db144fe
MH		 18#include <linux/i2c.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
9db144fe 21#include <linux/usb/musb.h>
9db144fe
MH		 22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h>
24#include <asm/reboot.h>
25#include <asm/nand.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
28#include <linux/spi/ad7877.h>
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "Bluetechnix CM-BF527";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
9db144fe 39#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 40#include <linux/usb/isp1760.h>
41static struct resource bfin_isp1760_resources[] = {
9db144fe 42 [0] = {
3f375690
MH		 43 .start = 0x203C0000,
44 .end = 0x203C0000 + 0x000fffff,
9db144fe
MH		 45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
3f375690
MH		 48 .start = IRQ_PF7,
49 .end = IRQ_PF7,
9db144fe
MH		 50 .flags = IORESOURCE_IRQ,
51 },
52};
53
3f375690
MH		 54static struct isp1760_platform_data isp1760_priv = {
55 .is_isp1761 = 0,
3f375690
MH		 56 .bus_width_16 = 1,
57 .port1_otg = 0,
58 .analog_oc = 0,
59 .dack_polarity_high = 0,
60 .dreq_polarity_high = 0,
9db144fe
MH		 61};
62
3f375690 63static struct platform_device bfin_isp1760_device = {
c6feb768 64 .name = "isp1760",
3f375690
MH		 65 .id = 0,
66 .dev = {
67 .platform_data = &isp1760_priv,
68 },
69 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
70 .resource = bfin_isp1760_resources,
9db144fe 71};
9db144fe
MH		 72#endif
73
74#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
75static struct resource musb_resources[] = {
76 [0] = {
77 .start = 0xffc03800,
78 .end = 0xffc03cff,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = { /* general IRQ */
82 .start = IRQ_USB_INT0,
83 .end = IRQ_USB_INT0,
84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
85 },
86 [2] = { /* DMA IRQ */
87 .start = IRQ_USB_DMA,
88 .end = IRQ_USB_DMA,
89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
90 },
91};
92
50041acb
BW		 93static struct musb_hdrc_config musb_config = {
94 .multipoint = 0,
95 .dyn_fifo = 0,
96 .soft_con = 1,
97 .dma = 1,
fea05dac
BW		 98 .num_eps = 8,
99 .dma_channels = 8,
50041acb 100 .gpio_vrsel = GPIO_PF11,
85eb0e4b
CC		 101 /* Some custom boards need to be active low, just set it to "0"
102 * if it is the case.
103 */
104 .gpio_vrsel_active = 1,
50041acb
BW		 105};
106
9db144fe
MH		 107static struct musb_hdrc_platform_data musb_plat = {
108#if defined(CONFIG_USB_MUSB_OTG)
109 .mode = MUSB_OTG,
110#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
111 .mode = MUSB_HOST,
112#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
113 .mode = MUSB_PERIPHERAL,
114#endif
50041acb 115 .config = &musb_config,
9db144fe
MH		 116};
117
118static u64 musb_dmamask = ~(u32)0;
119
120static struct platform_device musb_device = {
121 .name = "musb_hdrc",
122 .id = 0,
123 .dev = {
124 .dma_mask = &musb_dmamask,
125 .coherent_dma_mask = 0xffffffff,
126 .platform_data = &musb_plat,
127 },
128 .num_resources = ARRAY_SIZE(musb_resources),
129 .resource = musb_resources,
130};
131#endif
132
9db144fe
MH		 133#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
134static struct mtd_partition partition_info[] = {
135 {
aa582977 136 .name = "linux kernel(nand)",
9db144fe 137 .offset = 0,
f4585a08 138 .size = 4 * 1024 * 1024,
9db144fe
MH		 139 },
140 {
aa582977 141 .name = "file system(nand)",
9db144fe
MH		 142 .offset = MTDPART_OFS_APPEND,
143 .size = MTDPART_SIZ_FULL,
144 },
145};
146
147static struct bf5xx_nand_platform bf5xx_nand_platform = {
9db144fe
MH		 148 .data_width = NFC_NWIDTH_8,
149 .partitions = partition_info,
150 .nr_partitions = ARRAY_SIZE(partition_info),
151 .rd_dly = 3,
152 .wr_dly = 3,
153};
154
155static struct resource bf5xx_nand_resources[] = {
156 {
157 .start = NFC_CTL,
158 .end = NFC_DATA_RD + 2,
159 .flags = IORESOURCE_MEM,
160 },
161 {
162 .start = CH_NFC,
163 .end = CH_NFC,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device bf5xx_nand_device = {
169 .name = "bf5xx-nand",
170 .id = 0,
171 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
172 .resource = bf5xx_nand_resources,
173 .dev = {
174 .platform_data = &bf5xx_nand_platform,
175 },
176};
177#endif
178
179#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
180static struct resource bfin_pcmcia_cf_resources[] = {
181 {
182 .start = 0x20310000, /* IO PORT */
183 .end = 0x20312000,
184 .flags = IORESOURCE_MEM,
185 }, {
186 .start = 0x20311000, /* Attribute Memory */
187 .end = 0x20311FFF,
188 .flags = IORESOURCE_MEM,
189 }, {
190 .start = IRQ_PF4,
191 .end = IRQ_PF4,
192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
193 }, {
194 .start = 6, /* Card Detect PF6 */
195 .end = 6,
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device bfin_pcmcia_cf_device = {
201 .name = "bfin_cf_pcmcia",
202 .id = -1,
203 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
204 .resource = bfin_pcmcia_cf_resources,
205};
206#endif
207
208#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
209static struct platform_device rtc_device = {
210 .name = "rtc-bfin",
211 .id = -1,
212};
213#endif
214
215#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 216#include <linux/smc91x.h>
217
218static struct smc91x_platdata smc91x_info = {
219 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
220 .leda = RPC_LED_100_10,
221 .ledb = RPC_LED_TX_RX,
222};
223
9db144fe
MH		 224static struct resource smc91x_resources[] = {
225 {
226 .name = "smc91x-regs",
227 .start = 0x20300300,
228 .end = 0x20300300 + 16,
229 .flags = IORESOURCE_MEM,
230 }, {
231
232 .start = IRQ_PF7,
233 .end = IRQ_PF7,
234 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
235 },
236};
237static struct platform_device smc91x_device = {
238 .name = "smc91x",
239 .id = 0,
240 .num_resources = ARRAY_SIZE(smc91x_resources),
241 .resource = smc91x_resources,
61f09b5a
MH		 242 .dev = {
243 .platform_data = &smc91x_info,
244 },
9db144fe
MH		 245};
246#endif
247
248#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
249static struct resource dm9000_resources[] = {
250 [0] = {
251 .start = 0x203FB800,
b3dec4a4 252 .end = 0x203FB800 + 1,
9db144fe
MH		 253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
b3dec4a4
BS		 256 .start = 0x203FB804,
257 .end = 0x203FB804 + 1,
258 .flags = IORESOURCE_MEM,
259 },
260 [2] = {
9db144fe
MH		 261 .start = IRQ_PF9,
262 .end = IRQ_PF9,
263 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
264 },
265};
266
267static struct platform_device dm9000_device = {
268 .name = "dm9000",
269 .id = -1,
270 .num_resources = ARRAY_SIZE(dm9000_resources),
271 .resource = dm9000_resources,
272};
273#endif
274
9db144fe 275#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
02460d08
SZ		 276#include <linux/bfin_mac.h>
277static const unsigned short bfin_mac_peripherals[] = P_RMII0;
278
279static struct bfin_phydev_platform_data bfin_phydev_data[] = {
280 {
281 .addr = 1,
282 .irq = IRQ_MAC_PHYINT,
283 },
284};
285
286static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
287 .phydev_number = 1,
288 .phydev_data = bfin_phydev_data,
289 .phy_mode = PHY_INTERFACE_MODE_RMII,
290 .mac_peripherals = bfin_mac_peripherals,
291};
292
65319628
GY		 293static struct platform_device bfin_mii_bus = {
294 .name = "bfin_mii_bus",
02460d08
SZ		 295 .dev = {
296 .platform_data = &bfin_mii_bus_data,
297 }
65319628
GY		 298};
299
9db144fe
MH		 300static struct platform_device bfin_mac_device = {
301 .name = "bfin_mac",
02460d08
SZ		 302 .dev = {
303 .platform_data = &bfin_mii_bus,
304 }
9db144fe
MH		 305};
306#endif
307
308#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
309static struct resource net2272_bfin_resources[] = {
310 {
311 .start = 0x20300000,
312 .end = 0x20300000 + 0x100,
313 .flags = IORESOURCE_MEM,
314 }, {
315 .start = IRQ_PF7,
316 .end = IRQ_PF7,
317 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
318 },
319};
320
321static struct platform_device net2272_bfin_device = {
322 .name = "net2272",
323 .id = -1,
324 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
325 .resource = net2272_bfin_resources,
326};
327#endif
328
329#if defined(CONFIG_MTD_M25P80) \
330 || defined(CONFIG_MTD_M25P80_MODULE)
331static struct mtd_partition bfin_spi_flash_partitions[] = {
332 {
aa582977 333 .name = "bootloader(spi)",
9db144fe
MH		 334 .size = 0x00040000,
335 .offset = 0,
336 .mask_flags = MTD_CAP_ROM
337 }, {
aa582977 338 .name = "linux kernel(spi)",
9db144fe
MH		 339 .size = MTDPART_SIZ_FULL,
340 .offset = MTDPART_OFS_APPEND,
341 }
342};
343
344static struct flash_platform_data bfin_spi_flash_data = {
345 .name = "m25p80",
346 .parts = bfin_spi_flash_partitions,
347 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
348 .type = "m25p16",
349};
350
351/* SPI flash chip (m25p64) */
352static struct bfin5xx_spi_chip spi_flash_chip_info = {
353 .enable_dma = 0, /* use dma transfer with this chip*/
354 .bits_per_word = 8,
355};
356#endif
357
a261eec0
MF		 358#if defined(CONFIG_BFIN_SPI_ADC) \
359 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 360/* SPI ADC chip */
361static struct bfin5xx_spi_chip spi_adc_chip_info = {
362 .enable_dma = 1, /* use dma transfer with this chip*/
363 .bits_per_word = 16,
364};
365#endif
366
7ba80063
BS		 367#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
368 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
9db144fe
MH		 369static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
370 .enable_dma = 0,
371 .bits_per_word = 16,
372};
373#endif
374
f3f704d3
MH		 375#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
376static struct bfin5xx_spi_chip mmc_spi_chip_info = {
377 .enable_dma = 0,
9db144fe
MH		 378 .bits_per_word = 8,
379};
380#endif
381
9db144fe
MH		 382#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
383static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
384 .enable_dma = 0,
385 .bits_per_word = 16,
386};
387
388static const struct ad7877_platform_data bfin_ad7877_ts_info = {
389 .model = 7877,
390 .vref_delay_usecs = 50, /* internal, no capacitor */
391 .x_plate_ohms = 419,
392 .y_plate_ohms = 486,
393 .pressure_max = 1000,
394 .pressure_min = 0,
395 .stopacq_polarity = 1,
396 .first_conversion_delay = 3,
397 .acquisition_time = 1,
398 .averaging = 1,
399 .pen_down_acc_interval = 1,
400};
401#endif
402
403#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
404 && defined(CONFIG_SND_SOC_WM8731_SPI)
405static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
406 .enable_dma = 0,
407 .bits_per_word = 16,
408};
409#endif
410
411#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
412static struct bfin5xx_spi_chip spidev_chip_info = {
413 .enable_dma = 0,
414 .bits_per_word = 8,
415};
416#endif
417
418static struct spi_board_info bfin_spi_board_info[] __initdata = {
419#if defined(CONFIG_MTD_M25P80) \
420 || defined(CONFIG_MTD_M25P80_MODULE)
421 {
422 /* the modalias must be the same as spi device driver name */
423 .modalias = "m25p80", /* Name of spi_driver for this device */
424 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
425 .bus_num = 0, /* Framework bus number */
426 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
427 .platform_data = &bfin_spi_flash_data,
428 .controller_data = &spi_flash_chip_info,
429 .mode = SPI_MODE_3,
430 },
431#endif
432
a261eec0
MF		 433#if defined(CONFIG_BFIN_SPI_ADC) \
434 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 435 {
436 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
437 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
438 .bus_num = 0, /* Framework bus number */
439 .chip_select = 1, /* Framework chip select. */
440 .platform_data = NULL, /* No spi_driver specific config */
441 .controller_data = &spi_adc_chip_info,
442 },
443#endif
444
7ba80063
BS		 445#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
446 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
9db144fe 447 {
7ba80063 448 .modalias = "ad183x",
9db144fe
MH		 449 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
450 .bus_num = 0,
7ba80063 451 .chip_select = 4,
9db144fe
MH		 452 .controller_data = &ad1836_spi_chip_info,
453 },
454#endif
f3f704d3 455#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
9db144fe 456 {
f3f704d3
MH		 457 .modalias = "mmc_spi",
458 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
9db144fe 459 .bus_num = 0,
f3f704d3
MH		 460 .chip_select = 5,
461 .controller_data = &mmc_spi_chip_info,
9db144fe
MH		 462 .mode = SPI_MODE_3,
463 },
464#endif
9db144fe
MH		 465#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
466 {
467 .modalias = "ad7877",
468 .platform_data = &bfin_ad7877_ts_info,
469 .irq = IRQ_PF8,
470 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0,
472 .chip_select = 2,
473 .controller_data = &spi_ad7877_chip_info,
474 },
475#endif
476#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
477 && defined(CONFIG_SND_SOC_WM8731_SPI)
478 {
479 .modalias = "wm8731",
480 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
481 .bus_num = 0,
482 .chip_select = 5,
483 .controller_data = &spi_wm8731_chip_info,
484 .mode = SPI_MODE_0,
485 },
486#endif
487#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
488 {
489 .modalias = "spidev",
490 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
491 .bus_num = 0,
492 .chip_select = 1,
493 .controller_data = &spidev_chip_info,
494 },
495#endif
496};
497
498#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
499/* SPI controller data */
500static struct bfin5xx_spi_master bfin_spi0_info = {
501 .num_chipselect = 8,
502 .enable_dma = 1, /* master has the ability to do dma transfer */
503 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
504};
505
506/* SPI (0) */
507static struct resource bfin_spi0_resource[] = {
508 [0] = {
509 .start = SPI0_REGBASE,
510 .end = SPI0_REGBASE + 0xFF,
511 .flags = IORESOURCE_MEM,
512 },
513 [1] = {
514 .start = CH_SPI,
515 .end = CH_SPI,
53122693
YL		 516 .flags = IORESOURCE_DMA,
517 },
518 [2] = {
519 .start = IRQ_SPI,
520 .end = IRQ_SPI,
9db144fe
MH		 521 .flags = IORESOURCE_IRQ,
522 },
523};
524
525static struct platform_device bfin_spi0_device = {
526 .name = "bfin-spi",
527 .id = 0, /* Bus number */
528 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
529 .resource = bfin_spi0_resource,
530 .dev = {
531 .platform_data = &bfin_spi0_info, /* Passed to driver */
532 },
533};
534#endif /* spi master and devices */
535
9c21453e
HK		 536#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
537static struct mtd_partition cm_partitions[] = {
538 {
539 .name = "bootloader(nor)",
540 .size = 0x40000,
541 .offset = 0,
542 }, {
543 .name = "linux kernel(nor)",
544 .size = 0x100000,
545 .offset = MTDPART_OFS_APPEND,
546 }, {
547 .name = "file system(nor)",
548 .size = MTDPART_SIZ_FULL,
549 .offset = MTDPART_OFS_APPEND,
550 }
551};
552
553static struct physmap_flash_data cm_flash_data = {
554 .width = 2,
555 .parts = cm_partitions,
556 .nr_parts = ARRAY_SIZE(cm_partitions),
557};
558
559static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
560
561static struct resource cm_flash_resource[] = {
562 {
563 .name = "cfi_probe",
564 .start = 0x20000000,
565 .end = 0x201fffff,
566 .flags = IORESOURCE_MEM,
567 }, {
568 .start = (unsigned long)cm_flash_gpios,
569 .end = ARRAY_SIZE(cm_flash_gpios),
570 .flags = IORESOURCE_IRQ,
571 }
572};
573
574static struct platform_device cm_flash_device = {
575 .name = "gpio-addr-flash",
576 .id = 0,
577 .dev = {
578 .platform_data = &cm_flash_data,
579 },
580 .num_resources = ARRAY_SIZE(cm_flash_resource),
581 .resource = cm_flash_resource,
582};
583#endif
584
9db144fe 585#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
9db144fe 586#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 587static struct resource bfin_uart0_resources[] = {
9db144fe 588 {
6bd1fbea
SZ		 589 .start = UART0_THR,
590 .end = UART0_GCTL+2,
9db144fe
MH		 591 .flags = IORESOURCE_MEM,
592 },
6bd1fbea
SZ		 593 {
594 .start = IRQ_UART0_RX,
595 .end = IRQ_UART0_RX+1,
596 .flags = IORESOURCE_IRQ,
597 },
598 {
599 .start = IRQ_UART0_ERROR,
600 .end = IRQ_UART0_ERROR,
601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 .start = CH_UART0_TX,
605 .end = CH_UART0_TX,
606 .flags = IORESOURCE_DMA,
607 },
608 {
609 .start = CH_UART0_RX,
610 .end = CH_UART0_RX,
611 .flags = IORESOURCE_DMA,
612 },
613};
614
615unsigned short bfin_uart0_peripherals[] = {
616 P_UART0_TX, P_UART0_RX, 0
617};
618
619static struct platform_device bfin_uart0_device = {
620 .name = "bfin-uart",
621 .id = 0,
622 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
623 .resource = bfin_uart0_resources,
624 .dev = {
625 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
626 },
627};
9db144fe
MH		 628#endif
629#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 630static struct resource bfin_uart1_resources[] = {
9db144fe 631 {
6bd1fbea
SZ		 632 .start = UART1_THR,
633 .end = UART1_GCTL+2,
9db144fe
MH		 634 .flags = IORESOURCE_MEM,
635 },
6bd1fbea
SZ		 636 {
637 .start = IRQ_UART1_RX,
638 .end = IRQ_UART1_RX+1,
639 .flags = IORESOURCE_IRQ,
640 },
641 {
642 .start = IRQ_UART1_ERROR,
643 .end = IRQ_UART1_ERROR,
644 .flags = IORESOURCE_IRQ,
645 },
646 {
647 .start = CH_UART1_TX,
648 .end = CH_UART1_TX,
649 .flags = IORESOURCE_DMA,
650 },
651 {
652 .start = CH_UART1_RX,
653 .end = CH_UART1_RX,
654 .flags = IORESOURCE_DMA,
655 },
656#ifdef CONFIG_BFIN_UART1_CTSRTS
657 { /* CTS pin */
658 .start = GPIO_PF9,
659 .end = GPIO_PF9,
660 .flags = IORESOURCE_IO,
661 },
662 { /* RTS pin */
663 .start = GPIO_PF10,
664 .end = GPIO_PF10,
665 .flags = IORESOURCE_IO,
666 },
9db144fe
MH		 667#endif
668};
669
6bd1fbea
SZ		 670unsigned short bfin_uart1_peripherals[] = {
671 P_UART1_TX, P_UART1_RX, 0
672};
673
674static struct platform_device bfin_uart1_device = {
9db144fe
MH		 675 .name = "bfin-uart",
676 .id = 1,
6bd1fbea
SZ		 677 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
678 .resource = bfin_uart1_resources,
679 .dev = {
680 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
681 },
9db144fe
MH		 682};
683#endif
6bd1fbea 684#endif
9db144fe
MH		 685
686#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
9db144fe 687#ifdef CONFIG_BFIN_SIR0
42bd8bcb 688static struct resource bfin_sir0_resources[] = {
9db144fe
MH		 689 {
690 .start = 0xFFC00400,
691 .end = 0xFFC004FF,
692 .flags = IORESOURCE_MEM,
693 },
42bd8bcb
GY		 694 {
695 .start = IRQ_UART0_RX,
696 .end = IRQ_UART0_RX+1,
697 .flags = IORESOURCE_IRQ,
698 },
699 {
700 .start = CH_UART0_RX,
701 .end = CH_UART0_RX+1,
702 .flags = IORESOURCE_DMA,
703 },
704};
705
706static struct platform_device bfin_sir0_device = {
707 .name = "bfin_sir",
708 .id = 0,
709 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
710 .resource = bfin_sir0_resources,
711};
9db144fe
MH		 712#endif
713#ifdef CONFIG_BFIN_SIR1
42bd8bcb 714static struct resource bfin_sir1_resources[] = {
9db144fe
MH		 715 {
716 .start = 0xFFC02000,
717 .end = 0xFFC020FF,
718 .flags = IORESOURCE_MEM,
719 },
42bd8bcb
GY		 720 {
721 .start = IRQ_UART1_RX,
722 .end = IRQ_UART1_RX+1,
723 .flags = IORESOURCE_IRQ,
724 },
725 {
726 .start = CH_UART1_RX,
727 .end = CH_UART1_RX+1,
728 .flags = IORESOURCE_DMA,
729 },
9db144fe
MH		 730};
731
42bd8bcb 732static struct platform_device bfin_sir1_device = {
9db144fe 733 .name = "bfin_sir",
42bd8bcb
GY		 734 .id = 1,
735 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
736 .resource = bfin_sir1_resources,
9db144fe
MH		 737};
738#endif
42bd8bcb 739#endif
9db144fe
MH		 740
741#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
742static struct resource bfin_twi0_resource[] = {
743 [0] = {
744 .start = TWI0_REGBASE,
745 .end = TWI0_REGBASE,
746 .flags = IORESOURCE_MEM,
747 },
748 [1] = {
749 .start = IRQ_TWI,
750 .end = IRQ_TWI,
751 .flags = IORESOURCE_IRQ,
752 },
753};
754
755static struct platform_device i2c_bfin_twi_device = {
756 .name = "i2c-bfin-twi",
757 .id = 0,
758 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
759 .resource = bfin_twi0_resource,
760};
761#endif
762
9db144fe 763static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
ebd58333 764#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
9db144fe
MH		 765 {
766 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
9db144fe
MH		 767 },
768#endif
204844eb 769#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
9db144fe
MH		 770 {
771 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
9db144fe
MH		 772 .irq = IRQ_PF8,
773 },
774#endif
50c4c086
MH		 775#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
776 {
777 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
778 },
779#endif
9db144fe 780};
9db144fe
MH		 781
782#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 783#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
784static struct resource bfin_sport0_uart_resources[] = {
785 {
786 .start = SPORT0_TCR1,
787 .end = SPORT0_MRCS3+4,
788 .flags = IORESOURCE_MEM,
789 },
790 {
791 .start = IRQ_SPORT0_RX,
792 .end = IRQ_SPORT0_RX+1,
793 .flags = IORESOURCE_IRQ,
794 },
795 {
796 .start = IRQ_SPORT0_ERROR,
797 .end = IRQ_SPORT0_ERROR,
798 .flags = IORESOURCE_IRQ,
799 },
800};
801
802unsigned short bfin_sport0_peripherals[] = {
803 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
804 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
805};
806
9db144fe
MH		 807static struct platform_device bfin_sport0_uart_device = {
808 .name = "bfin-sport-uart",
809 .id = 0,
df5de261
SZ		 810 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
811 .resource = bfin_sport0_uart_resources,
812 .dev = {
813 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
814 },
815};
816#endif
817#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
818static struct resource bfin_sport1_uart_resources[] = {
819 {
820 .start = SPORT1_TCR1,
821 .end = SPORT1_MRCS3+4,
822 .flags = IORESOURCE_MEM,
823 },
824 {
825 .start = IRQ_SPORT1_RX,
826 .end = IRQ_SPORT1_RX+1,
827 .flags = IORESOURCE_IRQ,
828 },
829 {
830 .start = IRQ_SPORT1_ERROR,
831 .end = IRQ_SPORT1_ERROR,
832 .flags = IORESOURCE_IRQ,
833 },
834};
835
836unsigned short bfin_sport1_peripherals[] = {
837 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
838 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
9db144fe
MH		 839};
840
841static struct platform_device bfin_sport1_uart_device = {
842 .name = "bfin-sport-uart",
843 .id = 1,
df5de261
SZ		 844 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
845 .resource = bfin_sport1_uart_resources,
846 .dev = {
847 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
848 },
9db144fe
MH		 849};
850#endif
df5de261 851#endif
9db144fe 852
9db144fe
MH		 853#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
854#include <linux/input.h>
855#include <linux/gpio_keys.h>
856
857static struct gpio_keys_button bfin_gpio_keys_table[] = {
858 {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
859};
860
861static struct gpio_keys_platform_data bfin_gpio_keys_data = {
862 .buttons = bfin_gpio_keys_table,
863 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
864};
865
866static struct platform_device bfin_device_gpiokeys = {
867 .name = "gpio-keys",
868 .dev = {
869 .platform_data = &bfin_gpio_keys_data,
870 },
871};
872#endif
873
9db144fe
MH		 874static const unsigned int cclk_vlev_datasheet[] =
875{
876 VRPAIR(VLEV_100, 400000000),
877 VRPAIR(VLEV_105, 426000000),
878 VRPAIR(VLEV_110, 500000000),
879 VRPAIR(VLEV_115, 533000000),
880 VRPAIR(VLEV_120, 600000000),
881};
882
883static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
884 .tuple_tab = cclk_vlev_datasheet,
885 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
886 .vr_settling_time = 25 /* us */,
887};
888
889static struct platform_device bfin_dpmc = {
890 .name = "bfin dpmc",
891 .dev = {
892 .platform_data = &bfin_dmpc_vreg_data,
893 },
894};
895
9c21453e 896static struct platform_device *cmbf527_devices[] __initdata = {
9db144fe
MH		 897
898 &bfin_dpmc,
899
900#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
901 &bf5xx_nand_device,
902#endif
903
904#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
905 &bfin_pcmcia_cf_device,
906#endif
907
908#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
909 &rtc_device,
910#endif
911
3f375690
MH		 912#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
913 &bfin_isp1760_device,
914#endif
915
9db144fe
MH		 916#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
917 &musb_device,
918#endif
919
920#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
921 &smc91x_device,
922#endif
923
924#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
925 &dm9000_device,
926#endif
927
928#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 929 &bfin_mii_bus,
9db144fe
MH		 930 &bfin_mac_device,
931#endif
932
933#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
934 &net2272_bfin_device,
935#endif
936
937#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
938 &bfin_spi0_device,
939#endif
940
9db144fe 941#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 942#ifdef CONFIG_SERIAL_BFIN_UART0
943 &bfin_uart0_device,
944#endif
945#ifdef CONFIG_SERIAL_BFIN_UART1
946 &bfin_uart1_device,
947#endif
9db144fe
MH		 948#endif
949
950#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 951#ifdef CONFIG_BFIN_SIR0
952 &bfin_sir0_device,
953#endif
954#ifdef CONFIG_BFIN_SIR1
955 &bfin_sir1_device,
956#endif
9db144fe
MH		 957#endif
958
959#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
960 &i2c_bfin_twi_device,
961#endif
962
963#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 964#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
9db144fe 965 &bfin_sport0_uart_device,
df5de261
SZ		 966#endif
967#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
9db144fe
MH		 968 &bfin_sport1_uart_device,
969#endif
df5de261 970#endif
9db144fe 971
9db144fe
MH		 972#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
973 &bfin_device_gpiokeys,
974#endif
975
9c21453e
HK		 976#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
977 &cm_flash_device,
9db144fe 978#endif
9db144fe
MH		 979};
980
7f6678c5 981static int __init cm_init(void)
9db144fe
MH		 982{
983 printk(KERN_INFO "%s(): registering device resources\n", __func__);
9db144fe
MH		 984 i2c_register_board_info(0, bfin_i2c_board_info,
985 ARRAY_SIZE(bfin_i2c_board_info));
9c21453e 986 platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
9db144fe 987 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
9db144fe
MH		 988 return 0;
989}
990
7f6678c5 991arch_initcall(cm_init);
9db144fe 992
c13ce9fd
SZ		 993static struct platform_device *cmbf527_early_devices[] __initdata = {
994#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
995#ifdef CONFIG_SERIAL_BFIN_UART0
996 &bfin_uart0_device,
997#endif
998#ifdef CONFIG_SERIAL_BFIN_UART1
999 &bfin_uart1_device,
1000#endif
1001#endif
1002
1003#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1004#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1005 &bfin_sport0_uart_device,
1006#endif
1007#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1008 &bfin_sport1_uart_device,
1009#endif
1010#endif
1011};
1012
1013void __init native_machine_early_platform_add_devices(void)
1014{
1015 printk(KERN_INFO "register early platform devices\n");
1016 early_platform_add_devices(cmbf527_early_devices,
1017 ARRAY_SIZE(cmbf527_early_devices));
1018}
1019
9db144fe
MH		 1020void native_machine_restart(char *cmd)
1021{
1022 /* workaround reboot hang when booting from SPI */
1023 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 1024 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
9db144fe
MH		 1025}
1026
1027void bfin_get_ether_addr(char *addr)
1028{
1029 random_ether_addr(addr);
1030 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
1031}
1032EXPORT_SYMBOL(bfin_get_ether_addr);
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