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BW
1/*
2 * file: include/asm-blackfin/mach-bf518/mem_map.h
3 * based on: include/asm-blackfin/mach-bf527/mem_map.h
4 * author: Bryan Wu <cooloney@kernel.org>
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF518/6/4/2 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_518_H_
32#define _MEM_MAP_518_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x8000
51
52/* Level 1 Memory */
53
54/* Memory Map for ADSP-BF518/6/4/2 processors */
55
56#ifdef CONFIG_BFIN_ICACHE
57#define BFIN_ICACHESIZE (16 * 1024)
58#else
59#define BFIN_ICACHESIZE (0)
60#endif
61
62#define L1_CODE_START 0xFFA00000
63#define L1_DATA_A_START 0xFF800000
64#define L1_DATA_B_START 0xFF900000
65
66#define L1_CODE_LENGTH 0xC000
67
68#ifdef CONFIG_BFIN_DCACHE
69
70#ifdef CONFIG_BFIN_DCACHE_BANKA
71#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
72#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
73#define L1_DATA_B_LENGTH 0x8000
74#define BFIN_DCACHESIZE (16 * 1024)
75#define BFIN_DSUPBANKS 1
76#else
77#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
78#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
79#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
80#define BFIN_DCACHESIZE (32 * 1024)
81#define BFIN_DSUPBANKS 2
82#endif
83
84#else
85#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
86#define L1_DATA_A_LENGTH 0x8000
87#define L1_DATA_B_LENGTH 0x8000
88#define BFIN_DCACHESIZE 0
89#define BFIN_DSUPBANKS 0
90#endif /*CONFIG_BFIN_DCACHE */
91
92/* Level 2 Memory - none */
93
94#define L2_START 0
95#define L2_LENGTH 0
96
97/* Scratch Pad Memory */
98
99#define L1_SCRATCH_START 0xFFB00000
100#define L1_SCRATCH_LENGTH 0x1000
101
46fa5eec
GY
102#define GET_PDA_SAFE(preg) \
103 preg.l = _cpu_pda; \
104 preg.h = _cpu_pda;
105
106#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
107
2f6f4bcd 108#endif /* _MEM_MAP_518_H_ */