git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 2f6f4bcd | 1 | /* |
| 96f1050d | 2 | * Copyright 2008 Analog Devices Inc. |
| 2f6f4bcd | 3 | * |
| 96f1050d | 4 | * Licensed under the ADI BSD license or the GPL-2 (or later) |
| 2f6f4bcd BW |
5 | */ |
| 6 | ||
| 7 | #ifndef _DEF_BF51X_H | |
| 8 | #define _DEF_BF51X_H | |
| 9 | ||
| 10 | ||
| 11 | /* ************************************************************** */ | |
| 12 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */ | |
| 13 | /* ************************************************************** */ | |
| 14 | ||
| 15 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | |
| 16 | #define PLL_CTL 0xFFC00000 /* PLL Control Register */ | |
| 17 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ | |
| 18 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ | |
| 19 | #define PLL_STAT 0xFFC0000C /* PLL Status Register */ | |
| 20 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ | |
| 21 | #define CHIPID 0xFFC00014 /* Device ID Register */ | |
| 22 | ||
| 23 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | |
| 24 | #define SWRST 0xFFC00100 /* Software Reset Register */ | |
| 25 | #define SYSCR 0xFFC00104 /* System Configuration Register */ | |
| 26 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ | |
| 27 | ||
| 28 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ | |
| 29 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | |
| 30 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | |
| 31 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | |
| 32 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ | |
| 33 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ | |
| 34 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ | |
| 35 | ||
| 36 | /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ | |
| 37 | #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ | |
| 38 | #define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ | |
| 39 | #define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ | |
| 40 | #define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ | |
| 41 | #define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ | |
| 42 | #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ | |
| 43 | #define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ | |
| 44 | ||
| 45 | ||
| 46 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | |
| 47 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | |
| 48 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | |
| 49 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | |
| 50 | ||
| 51 | ||
| 52 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | |
| 53 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | |
| 54 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | |
| 55 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | |
| 56 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | |
| 57 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | |
| 58 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | |
| 59 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ | |
| 60 | ||
| 61 | ||
| 62 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | |
| 63 | #define UART0_THR 0xFFC00400 /* Transmit Holding register */ | |
| 64 | #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ | |
| 65 | #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | |
| 66 | #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ | |
| 67 | #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | |
| 68 | #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ | |
| 69 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ | |
| 70 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ | |
| 71 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ | |
| 72 | #define UART0_MSR 0xFFC00418 /* Modem Status Register */ | |
| 73 | #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ | |
| 74 | #define UART0_GCTL 0xFFC00424 /* Global Control Register */ | |
| 75 | ||
| 76 | /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ | |
| 77 | #define SPI0_REGBASE 0xFFC00500 | |
| 78 | #define SPI0_CTL 0xFFC00500 /* SPI Control Register */ | |
| 79 | #define SPI0_FLG 0xFFC00504 /* SPI Flag register */ | |
| 80 | #define SPI0_STAT 0xFFC00508 /* SPI Status register */ | |
| 81 | #define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | |
| 82 | #define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | |
| 83 | #define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ | |
| 84 | #define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | |
| 85 | ||
| 86 | /* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ | |
| 87 | #define SPI1_REGBASE 0xFFC03400 | |
| 88 | #define SPI1_CTL 0xFFC03400 /* SPI Control Register */ | |
| 89 | #define SPI1_FLG 0xFFC03404 /* SPI Flag register */ | |
| 90 | #define SPI1_STAT 0xFFC03408 /* SPI Status register */ | |
| 91 | #define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */ | |
| 92 | #define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */ | |
| 93 | #define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */ | |
| 94 | #define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */ | |
| 95 | ||
| 96 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | |
| 97 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | |
| 98 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | |
| 99 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | |
| 100 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | |
| 101 | ||
| 102 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | |
| 103 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | |
| 104 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | |
| 105 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | |
| 106 | ||
| 107 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | |
| 108 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | |
| 109 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | |
| 110 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | |
| 111 | ||
| 112 | #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ | |
| 113 | #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ | |
| 114 | #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ | |
| 115 | #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ | |
| 116 | ||
| 117 | #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ | |
| 118 | #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ | |
| 119 | #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ | |
| 120 | #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ | |
| 121 | ||
| 122 | #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ | |
| 123 | #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ | |
| 124 | #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ | |
| 125 | #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ | |
| 126 | ||
| 127 | #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ | |
| 128 | #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ | |
| 129 | #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ | |
| 130 | #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ | |
| 131 | ||
| 132 | #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ | |
| 133 | #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ | |
| 134 | #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ | |
| 135 | #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ | |
| 136 | ||
| 137 | #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ | |
| 138 | #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ | |
| 139 | #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ | |
| 140 | ||
| 141 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | |
| 142 | #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ | |
| 143 | #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ | |
| 144 | #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ | |
| 145 | #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ | |
| 146 | #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ | |
| 147 | #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ | |
| 148 | #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ | |
| 149 | #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ | |
| 150 | #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ | |
| 151 | #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ | |
| 152 | #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ | |
| 153 | #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ | |
| 154 | #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ | |
| 155 | #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ | |
| 156 | #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ | |
| 157 | #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ | |
| 158 | #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ | |
| 159 | ||
| 160 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | |
| 161 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | |
| 162 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | |
| 163 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | |
| 164 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | |
| 165 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | |
| 166 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | |
| 167 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | |
| 168 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | |
| 169 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | |
| 170 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | |
| 171 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | |
| 172 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | |
| 173 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | |
| 174 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | |
| 175 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | |
| 176 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | |
| 177 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | |
| 178 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | |
| 179 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | |
| 180 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | |
| 181 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | |
| 182 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | |
| 183 | ||
| 184 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | |
| 185 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | |
| 186 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | |
| 187 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | |
| 188 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | |
| 189 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | |
| 190 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | |
| 191 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | |
| 192 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | |
| 193 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | |
| 194 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | |
| 195 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | |
| 196 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | |
| 197 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | |
| 198 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | |
| 199 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | |
| 200 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | |
| 201 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | |
| 202 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | |
| 203 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | |
| 204 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | |
| 205 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | |
| 206 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | |
| 207 | ||
| 208 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | |
| 209 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | |
| 210 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | |
| 211 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | |
| 212 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | |
| 213 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | |
| 214 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | |
| 215 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | |
| 216 | ||
| 217 | /* DMA Traffic Control Registers */ | |
| 218 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | |
| 219 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | |
| 220 | ||
| 221 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | |
| 222 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | |
| 223 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | |
| 224 | ||
| 225 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | |
| 226 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | |
| 227 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | |
| 228 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | |
| 229 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | |
| 230 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | |
| 231 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | |
| 232 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | |
| 233 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | |
| 234 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | |
| 235 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | |
| 236 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | |
| 237 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | |
| 238 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | |
| 239 | ||
| 240 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | |
| 241 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | |
| 242 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | |
| 243 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | |
| 244 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | |
| 245 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | |
| 246 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | |
| 247 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | |
| 248 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | |
| 249 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | |
| 250 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | |
| 251 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | |
| 252 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | |
| 253 | ||
| 254 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | |
| 255 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | |
| 256 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | |
| 257 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | |
| 258 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | |
| 259 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | |
| 260 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | |
| 261 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | |
| 262 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | |
| 263 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | |
| 264 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | |
| 265 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | |
| 266 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | |
| 267 | ||
| 268 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | |
| 269 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | |
| 270 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | |
| 271 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | |
| 272 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | |
| 273 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | |
| 274 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | |
| 275 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | |
| 276 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | |
| 277 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | |
| 278 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | |
| 279 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | |
| 280 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | |
| 281 | ||
| 282 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | |
| 283 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | |
| 284 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | |
| 285 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | |
| 286 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | |
| 287 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | |
| 288 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | |
| 289 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | |
| 290 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | |
| 291 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | |
| 292 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | |
| 293 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | |
| 294 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | |
| 295 | ||
| 296 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | |
| 297 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | |
| 298 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | |
| 299 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | |
| 300 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | |
| 301 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | |
| 302 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | |
| 303 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | |
| 304 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | |
| 305 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | |
| 306 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | |
| 307 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | |
| 308 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | |
| 309 | ||
| 310 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | |
| 311 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | |
| 312 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | |
| 313 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | |
| 314 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | |
| 315 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | |
| 316 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | |
| 317 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | |
| 318 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | |
| 319 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | |
| 320 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | |
| 321 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | |
| 322 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | |
| 323 | ||
| 324 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | |
| 325 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | |
| 326 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | |
| 327 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | |
| 328 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | |
| 329 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | |
| 330 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | |
| 331 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | |
| 332 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | |
| 333 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | |
| 334 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | |
| 335 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | |
| 336 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | |
| 337 | ||
| 338 | #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ | |
| 339 | #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ | |
| 340 | #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ | |
| 341 | #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ | |
| 342 | #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ | |
| 343 | #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ | |
| 344 | #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ | |
| 345 | #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ | |
| 346 | #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ | |
| 347 | #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ | |
| 348 | #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ | |
| 349 | #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ | |
| 350 | #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ | |
| 351 | ||
| 352 | #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ | |
| 353 | #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ | |
| 354 | #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ | |
| 355 | #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ | |
| 356 | #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ | |
| 357 | #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ | |
| 358 | #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ | |
| 359 | #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ | |
| 360 | #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ | |
| 361 | #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ | |
| 362 | #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ | |
| 363 | #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ | |
| 364 | #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ | |
| 365 | ||
| 366 | #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ | |
| 367 | #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ | |
| 368 | #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ | |
| 369 | #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ | |
| 370 | #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ | |
| 371 | #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ | |
| 372 | #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ | |
| 373 | #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ | |
| 374 | #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ | |
| 375 | #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ | |
| 376 | #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ | |
| 377 | #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ | |
| 378 | #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ | |
| 379 | ||
| 380 | #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ | |
| 381 | #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ | |
| 382 | #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ | |
| 383 | #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ | |
| 384 | #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ | |
| 385 | #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ | |
| 386 | #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ | |
| 387 | #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ | |
| 388 | #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ | |
| 389 | #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ | |
| 390 | #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ | |
| 391 | #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ | |
| 392 | #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ | |
| 393 | ||
| 394 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ | |
| 395 | #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ | |
| 396 | #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ | |
| 397 | #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ | |
| 398 | #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ | |
| 399 | #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ | |
| 400 | #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ | |
| 401 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ | |
| 402 | #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ | |
| 403 | #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ | |
| 404 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ | |
| 405 | #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ | |
| 406 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ | |
| 407 | ||
| 408 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ | |
| 409 | #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ | |
| 410 | #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ | |
| 411 | #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ | |
| 412 | #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ | |
| 413 | #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ | |
| 414 | #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ | |
| 415 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ | |
| 416 | #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ | |
| 417 | #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ | |
| 418 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ | |
| 419 | #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ | |
| 420 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ | |
| 421 | ||
| 422 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ | |
| 423 | #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ | |
| 424 | #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ | |
| 425 | #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ | |
| 426 | #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ | |
| 427 | #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ | |
| 428 | #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ | |
| 429 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ | |
| 430 | #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ | |
| 431 | #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ | |
| 432 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ | |
| 433 | #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ | |
| 434 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ | |
| 435 | ||
| 436 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ | |
| 437 | #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ | |
| 438 | #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ | |
| 439 | #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ | |
| 440 | #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ | |
| 441 | #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ | |
| 442 | #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ | |
| 443 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ | |
| 444 | #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ | |
| 445 | #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ | |
| 446 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ | |
| 447 | #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ | |
| 448 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ | |
| 449 | ||
| 450 | ||
| 451 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | |
| 452 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | |
| 453 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | |
| 454 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | |
| 455 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | |
| 456 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | |
| 457 | ||
| 458 | ||
| 459 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | |
| 460 | #define TWI0_REGBASE 0xFFC01400 | |
| ba3f5973 MF |
461 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| 462 | #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ | |
| 463 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | |
| 464 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | |
| 465 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | |
| 466 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | |
| 467 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | |
| 468 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | |
| 469 | #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | |
| 470 | #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | |
| 471 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | |
| 472 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | |
| 473 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | |
| 474 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | |
| 475 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | |
| 476 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | |
| 2f6f4bcd BW |
477 | |
| 478 | ||
| 479 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | |
| 480 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ | |
| 481 | #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ | |
| 482 | #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ | |
| 483 | #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ | |
| 484 | #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ | |
| 485 | #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ | |
| 486 | #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ | |
| 487 | #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ | |
| 488 | #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ | |
| 489 | #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ | |
| 490 | #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ | |
| 491 | #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ | |
| 492 | #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ | |
| 493 | #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ | |
| 494 | #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ | |
| 495 | #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ | |
| 496 | #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ | |
| 497 | ||
| 498 | ||
| 499 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | |
| 500 | #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ | |
| 501 | #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ | |
| 502 | #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ | |
| 503 | #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ | |
| 504 | #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ | |
| 505 | #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ | |
| 506 | #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ | |
| 507 | #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ | |
| 508 | #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ | |
| 509 | #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ | |
| 510 | #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ | |
| 511 | #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ | |
| 512 | #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ | |
| 513 | #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ | |
| 514 | #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ | |
| 515 | #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ | |
| 516 | #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ | |
| 517 | ||
| 518 | ||
| 519 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | |
| 520 | #define UART1_THR 0xFFC02000 /* Transmit Holding register */ | |
| 521 | #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ | |
| 522 | #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ | |
| 523 | #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ | |
| 524 | #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ | |
| 525 | #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ | |
| 526 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ | |
| 527 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ | |
| 528 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ | |
| 529 | #define UART1_MSR 0xFFC02018 /* Modem Status Register */ | |
| 530 | #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ | |
| 531 | #define UART1_GCTL 0xFFC02024 /* Global Control Register */ | |
| 532 | ||
| 533 | ||
| 534 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | |
| 535 | #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ | |
| 536 | #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ | |
| 537 | #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ | |
| 538 | #define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ | |
| 539 | ||
| 540 | ||
| 541 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | |
| 542 | #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ | |
| 543 | #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ | |
| 544 | #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ | |
| af901ca1 | 545 | #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ |
| 2f6f4bcd BW |
546 | #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ |
| 547 | #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ | |
| 548 | #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ | |
| 549 | ||
| 550 | #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ | |
| 551 | #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ | |
| 552 | #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ | |
| af901ca1 | 553 | #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ |
| 2f6f4bcd BW |
554 | #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ |
| 555 | #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ | |
| 556 | #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ | |
| 557 | ||
| 558 | ||
| 559 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | |
| 560 | #define PORTF_MUX 0xFFC03210 /* Port F mux control */ | |
| 561 | #define PORTG_MUX 0xFFC03214 /* Port G mux control */ | |
| 562 | #define PORTH_MUX 0xFFC03218 /* Port H mux control */ | |
| 563 | #define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ | |
| 564 | #define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ | |
| 565 | #define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ | |
| 566 | #define PORTF_SLEW 0xFFC03230 /* Port F slew control */ | |
| 567 | #define PORTG_SLEW 0xFFC03234 /* Port G slew control */ | |
| 568 | #define PORTH_SLEW 0xFFC03238 /* Port H slew control */ | |
| 569 | #define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ | |
| 570 | #define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ | |
| 571 | #define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ | |
| 572 | #define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ | |
| 573 | #define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ | |
| 574 | #define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ | |
| 575 | ||
| 576 | ||
| 577 | /*********************************************************************************** | |
| 578 | ** System MMR Register Bits And Macros | |
| 579 | ** | |
| 580 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | |
| 581 | ** Use these macros carefully, as any that do left shifts for field | |
| 582 | ** depositing will result in the lower order bits being destroyed. Any | |
| 583 | ** macro that shifts left to properly position the bit-field should be | |
| 584 | ** used as part of an OR to initialize a register and NOT as a dynamic | |
| 585 | ** modifier UNLESS the lower order bits are saved and ORed back in when | |
| 586 | ** the macro is used. | |
| 587 | *************************************************************************************/ | |
| 2f6f4bcd BW |
588 | |
| 589 | /* CHIPID Masks */ | |
| 590 | #define CHIPID_VERSION 0xF0000000 | |
| 591 | #define CHIPID_FAMILY 0x0FFFF000 | |
| 592 | #define CHIPID_MANUFACTURE 0x00000FFE | |
| 593 | ||
| 594 | /* SWRST Masks */ | |
| 595 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ | |
| 596 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | |
| 597 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | |
| 598 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | |
| 599 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | |
| 600 | ||
| 601 | /* SYSCR Masks */ | |
| 602 | #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ | |
| 603 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | |
| 604 | ||
| 605 | ||
| 606 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ | |
| 607 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ | |
| 608 | ||
| 609 | #if 0 | |
| 610 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ | |
| 611 | ||
| 612 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ | |
| 613 | #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ | |
| 614 | #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ | |
| 615 | #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ | |
| 616 | #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ | |
| 617 | #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ | |
| 618 | #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ | |
| 619 | ||
| 620 | #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ | |
| 621 | #define IRQ_TWI 0x00000200 /* TWI Interrupt */ | |
| 622 | #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ | |
| 623 | #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ | |
| 624 | #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ | |
| 625 | #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ | |
| 626 | #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ | |
| 627 | #define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ | |
| 628 | ||
| 629 | #define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ | |
| 630 | #define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ | |
| 631 | #define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ | |
| 632 | #define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ | |
| 633 | #define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ | |
| 634 | #define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ | |
| 635 | #define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ | |
| 636 | #define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ | |
| 637 | #define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ | |
| 638 | #define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ | |
| 639 | ||
| 640 | #define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ | |
| 641 | #define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ | |
| 642 | #define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ | |
| 643 | #define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ | |
| 644 | #define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ | |
| 645 | #define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ | |
| 646 | #define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ | |
| 647 | #define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ | |
| 648 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ | |
| 649 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ | |
| 650 | #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ | |
| 651 | #endif | |
| 652 | ||
| 653 | /* SIC_IAR0 Macros */ | |
| 654 | #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ | |
| 655 | #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ | |
| 656 | #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ | |
| 657 | #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ | |
| 658 | #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ | |
| 659 | #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ | |
| 660 | #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ | |
| 661 | #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ | |
| 662 | ||
| 663 | /* SIC_IAR1 Macros */ | |
| 664 | #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ | |
| 665 | #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ | |
| 666 | #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ | |
| 667 | #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ | |
| 668 | #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ | |
| 669 | #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ | |
| 670 | #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ | |
| 671 | #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ | |
| 672 | ||
| 673 | /* SIC_IAR2 Macros */ | |
| 674 | #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ | |
| 675 | #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ | |
| 676 | #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ | |
| 677 | #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ | |
| 678 | #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ | |
| 679 | #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ | |
| 680 | #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ | |
| 681 | #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ | |
| 682 | ||
| 683 | /* SIC_IAR3 Macros */ | |
| 684 | #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ | |
| 685 | #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ | |
| 686 | #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ | |
| 687 | #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ | |
| 688 | #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ | |
| 689 | #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ | |
| 690 | #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ | |
| 691 | #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ | |
| 692 | ||
| 693 | ||
| 694 | /* SIC_IMASK Masks */ | |
| 695 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | |
| 696 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | |
| 697 | #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ | |
| 698 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ | |
| 699 | ||
| 700 | /* SIC_IWR Masks */ | |
| 701 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | |
| 702 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | |
| 703 | #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ | |
| 704 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ | |
| 705 | ||
| 706 | ||
| 2f6f4bcd BW |
707 | /* ************** UART CONTROLLER MASKS *************************/ |
| 708 | /* UARTx_LCR Masks */ | |
| 709 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ | |
| 710 | #define STB 0x04 /* Stop Bits */ | |
| 711 | #define PEN 0x08 /* Parity Enable */ | |
| 712 | #define EPS 0x10 /* Even Parity Select */ | |
| 713 | #define STP 0x20 /* Stick Parity */ | |
| 714 | #define SB 0x40 /* Set Break */ | |
| 715 | #define DLAB 0x80 /* Divisor Latch Access */ | |
| 716 | ||
| 717 | /* UARTx_MCR Mask */ | |
| 718 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ | |
| 719 | #define LOOP_ENA_P 0x04 | |
| 720 | ||
| 721 | /* UARTx_LSR Masks */ | |
| 722 | #define DR 0x01 /* Data Ready */ | |
| 723 | #define OE 0x02 /* Overrun Error */ | |
| 724 | #define PE 0x04 /* Parity Error */ | |
| 725 | #define FE 0x08 /* Framing Error */ | |
| 726 | #define BI 0x10 /* Break Interrupt */ | |
| 727 | #define THRE 0x20 /* THR Empty */ | |
| 728 | #define TEMT 0x40 /* TSR and UART_THR Empty */ | |
| 729 | ||
| 730 | /* UARTx_IER Masks */ | |
| 731 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ | |
| 732 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ | |
| 733 | #define ELSI 0x04 /* Enable RX Status Interrupt */ | |
| 734 | ||
| 735 | /* UARTx_IIR Masks */ | |
| 736 | #define NINT 0x01 /* Pending Interrupt */ | |
| 737 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | |
| 738 | #define IIR_RX_READY 0x04 /* Receive data ready */ | |
| 739 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | |
| 740 | #define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ | |
| 741 | ||
| 742 | /* UARTx_GCTL Masks */ | |
| 743 | #define UCEN 0x01 /* Enable UARTx Clocks */ | |
| 744 | #define IREN 0x02 /* Enable IrDA Mode */ | |
| 745 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ | |
| 746 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ | |
| 747 | #define FPE 0x10 /* Force Parity Error On Transmit */ | |
| 748 | #define FFE 0x20 /* Force Framing Error On Transmit */ | |
| 749 | ||
| 750 | ||
| 751 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ | |
| 752 | /* SPI_CTL Masks */ | |
| 753 | #define TIMOD 0x0003 /* Transfer Initiate Mode */ | |
| 754 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ | |
| 755 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | |
| 756 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | |
| 757 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | |
| 758 | #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ | |
| 759 | #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ | |
| 760 | #define PSSE 0x0010 /* Slave-Select Input Enable */ | |
| 761 | #define EMISO 0x0020 /* Enable MISO As Output */ | |
| 762 | #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ | |
| 763 | #define LSBF 0x0200 /* LSB First */ | |
| 764 | #define CPHA 0x0400 /* Clock Phase */ | |
| 765 | #define CPOL 0x0800 /* Clock Polarity */ | |
| 766 | #define MSTR 0x1000 /* Master/Slave* */ | |
| 767 | #define WOM 0x2000 /* Write Open Drain Master */ | |
| 768 | #define SPE 0x4000 /* SPI Enable */ | |
| 769 | ||
| 770 | /* SPI_FLG Masks */ | |
| 771 | #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ | |
| 772 | #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ | |
| 773 | #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ | |
| 774 | #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ | |
| 775 | #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ | |
| 776 | #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ | |
| 777 | #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ | |
| 778 | #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ | |
| 779 | #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ | |
| 780 | #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ | |
| 781 | #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ | |
| 782 | #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ | |
| 783 | #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ | |
| 784 | #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ | |
| 785 | ||
| 786 | /* SPI_STAT Masks */ | |
| 787 | #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ | |
| 788 | #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ | |
| 789 | #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ | |
| 790 | #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ | |
| 791 | #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ | |
| 792 | #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ | |
| 793 | #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ | |
| 794 | ||
| 795 | ||
| 796 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ | |
| 797 | /* TIMER_ENABLE Masks */ | |
| 798 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | |
| 799 | #define TIMEN1 0x0002 /* Enable Timer 1 */ | |
| 800 | #define TIMEN2 0x0004 /* Enable Timer 2 */ | |
| 801 | #define TIMEN3 0x0008 /* Enable Timer 3 */ | |
| 802 | #define TIMEN4 0x0010 /* Enable Timer 4 */ | |
| 803 | #define TIMEN5 0x0020 /* Enable Timer 5 */ | |
| 804 | #define TIMEN6 0x0040 /* Enable Timer 6 */ | |
| 805 | #define TIMEN7 0x0080 /* Enable Timer 7 */ | |
| 806 | ||
| 807 | /* TIMER_DISABLE Masks */ | |
| 808 | #define TIMDIS0 TIMEN0 /* Disable Timer 0 */ | |
| 809 | #define TIMDIS1 TIMEN1 /* Disable Timer 1 */ | |
| 810 | #define TIMDIS2 TIMEN2 /* Disable Timer 2 */ | |
| 811 | #define TIMDIS3 TIMEN3 /* Disable Timer 3 */ | |
| 812 | #define TIMDIS4 TIMEN4 /* Disable Timer 4 */ | |
| 813 | #define TIMDIS5 TIMEN5 /* Disable Timer 5 */ | |
| 814 | #define TIMDIS6 TIMEN6 /* Disable Timer 6 */ | |
| 815 | #define TIMDIS7 TIMEN7 /* Disable Timer 7 */ | |
| 816 | ||
| 817 | /* TIMER_STATUS Masks */ | |
| 818 | #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ | |
| 819 | #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ | |
| 820 | #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ | |
| 821 | #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ | |
| 822 | #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ | |
| 823 | #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ | |
| 824 | #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ | |
| 825 | #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ | |
| 826 | #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ | |
| 827 | #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ | |
| 828 | #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ | |
| 829 | #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ | |
| 830 | #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ | |
| 831 | #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ | |
| 832 | #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ | |
| 833 | #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ | |
| 834 | #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ | |
| 835 | #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ | |
| 836 | #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ | |
| 837 | #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ | |
| 838 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ | |
| 839 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ | |
| 840 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ | |
| 841 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ | |
| 842 | ||
| 843 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | |
| 844 | #define TOVL_ERR0 TOVF_ERR0 | |
| 845 | #define TOVL_ERR1 TOVF_ERR1 | |
| 846 | #define TOVL_ERR2 TOVF_ERR2 | |
| 847 | #define TOVL_ERR3 TOVF_ERR3 | |
| 848 | #define TOVL_ERR4 TOVF_ERR4 | |
| 849 | #define TOVL_ERR5 TOVF_ERR5 | |
| 850 | #define TOVL_ERR6 TOVF_ERR6 | |
| 851 | #define TOVL_ERR7 TOVF_ERR7 | |
| 852 | ||
| 853 | /* TIMERx_CONFIG Masks */ | |
| 854 | #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ | |
| 855 | #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ | |
| 856 | #define EXT_CLK 0x0003 /* External Clock Mode */ | |
| 857 | #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ | |
| 858 | #define PERIOD_CNT 0x0008 /* Period Count */ | |
| 859 | #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ | |
| 860 | #define TIN_SEL 0x0020 /* Timer Input Select */ | |
| 861 | #define OUT_DIS 0x0040 /* Output Pad Disable */ | |
| 862 | #define CLK_SEL 0x0080 /* Timer Clock Select */ | |
| 863 | #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ | |
| 864 | #define EMU_RUN 0x0200 /* Emulation Behavior Select */ | |
| 865 | #define ERR_TYP 0xC000 /* Error Type */ | |
| 866 | ||
| 867 | ||
| 868 | /* ****************** GPIO PORTS F, G, H MASKS ***********************/ | |
| 869 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | |
| 870 | /* Port F Masks */ | |
| 871 | #define PF0 0x0001 | |
| 872 | #define PF1 0x0002 | |
| 873 | #define PF2 0x0004 | |
| 874 | #define PF3 0x0008 | |
| 875 | #define PF4 0x0010 | |
| 876 | #define PF5 0x0020 | |
| 877 | #define PF6 0x0040 | |
| 878 | #define PF7 0x0080 | |
| 879 | #define PF8 0x0100 | |
| 880 | #define PF9 0x0200 | |
| 881 | #define PF10 0x0400 | |
| 882 | #define PF11 0x0800 | |
| 883 | #define PF12 0x1000 | |
| 884 | #define PF13 0x2000 | |
| 885 | #define PF14 0x4000 | |
| 886 | #define PF15 0x8000 | |
| 887 | ||
| 888 | /* Port G Masks */ | |
| 889 | #define PG0 0x0001 | |
| 890 | #define PG1 0x0002 | |
| 891 | #define PG2 0x0004 | |
| 892 | #define PG3 0x0008 | |
| 893 | #define PG4 0x0010 | |
| 894 | #define PG5 0x0020 | |
| 895 | #define PG6 0x0040 | |
| 896 | #define PG7 0x0080 | |
| 897 | #define PG8 0x0100 | |
| 898 | #define PG9 0x0200 | |
| 899 | #define PG10 0x0400 | |
| 900 | #define PG11 0x0800 | |
| 901 | #define PG12 0x1000 | |
| 902 | #define PG13 0x2000 | |
| 903 | #define PG14 0x4000 | |
| 904 | #define PG15 0x8000 | |
| 905 | ||
| 906 | /* Port H Masks */ | |
| 907 | #define PH0 0x0001 | |
| 908 | #define PH1 0x0002 | |
| 909 | #define PH2 0x0004 | |
| 910 | #define PH3 0x0008 | |
| 911 | #define PH4 0x0010 | |
| 912 | #define PH5 0x0020 | |
| 913 | #define PH6 0x0040 | |
| 914 | #define PH7 0x0080 | |
| 915 | ||
| 2f6f4bcd BW |
916 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ |
| 917 | /* EBIU_AMGCTL Masks */ | |
| 918 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | |
| 919 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ | |
| 920 | #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ | |
| 921 | #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ | |
| 922 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ | |
| 923 | #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ | |
| 924 | ||
| 925 | /* EBIU_AMBCTL0 Masks */ | |
| 926 | #define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ | |
| 927 | #define B0RDYPOL 0x00000002 /* B0 RDY Active High */ | |
| 928 | #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ | |
| 929 | #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ | |
| 930 | #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ | |
| 931 | #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ | |
| 932 | #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ | |
| 933 | #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ | |
| 934 | #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ | |
| 935 | #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ | |
| 936 | #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | |
| 937 | #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | |
| 938 | #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | |
| 939 | #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | |
| 940 | #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ | |
| 941 | #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ | |
| 942 | #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ | |
| 943 | #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ | |
| 944 | #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ | |
| 945 | #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ | |
| 946 | #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ | |
| 947 | #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ | |
| 948 | #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ | |
| 949 | #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ | |
| 950 | #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ | |
| 951 | #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ | |
| 952 | #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ | |
| 953 | #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ | |
| 954 | #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ | |
| 955 | #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ | |
| 956 | #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ | |
| 957 | #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ | |
| 958 | #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ | |
| 959 | #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ | |
| 960 | #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ | |
| 961 | #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ | |
| 962 | #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ | |
| 963 | #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ | |
| 964 | #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ | |
| 965 | #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ | |
| 966 | #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ | |
| 967 | #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ | |
| 968 | #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ | |
| 969 | #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ | |
| 970 | ||
| 971 | #define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ | |
| 972 | #define B1RDYPOL 0x00020000 /* B1 RDY Active High */ | |
| 973 | #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ | |
| 974 | #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ | |
| 975 | #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ | |
| 976 | #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ | |
| 977 | #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ | |
| 978 | #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ | |
| 979 | #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ | |
| 980 | #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ | |
| 981 | #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | |
| 982 | #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | |
| 983 | #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | |
| 984 | #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | |
| 985 | #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ | |
| 986 | #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ | |
| 987 | #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ | |
| 988 | #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ | |
| 989 | #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ | |
| 990 | #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ | |
| 991 | #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ | |
| 992 | #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ | |
| 993 | #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ | |
| 994 | #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ | |
| 995 | #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ | |
| 996 | #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ | |
| 997 | #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ | |
| 998 | #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ | |
| 999 | #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ | |
| 1000 | #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ | |
| 1001 | #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ | |
| 1002 | #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ | |
| 1003 | #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ | |
| 1004 | #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ | |
| 1005 | #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ | |
| 1006 | #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ | |
| 1007 | #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ | |
| 1008 | #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ | |
| 1009 | #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ | |
| 1010 | #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ | |
| 1011 | #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ | |
| 1012 | #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ | |
| 1013 | #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ | |
| 1014 | #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ | |
| 1015 | ||
| 1016 | /* EBIU_AMBCTL1 Masks */ | |
| 1017 | #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ | |
| 1018 | #define B2RDYPOL 0x00000002 /* B2 RDY Active High */ | |
| 1019 | #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ | |
| 1020 | #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ | |
| 1021 | #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ | |
| 1022 | #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ | |
| 1023 | #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ | |
| 1024 | #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ | |
| 1025 | #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ | |
| 1026 | #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ | |
| 1027 | #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | |
| 1028 | #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | |
| 1029 | #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | |
| 1030 | #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | |
| 1031 | #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ | |
| 1032 | #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ | |
| 1033 | #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ | |
| 1034 | #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ | |
| 1035 | #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ | |
| 1036 | #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ | |
| 1037 | #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ | |
| 1038 | #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ | |
| 1039 | #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ | |
| 1040 | #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ | |
| 1041 | #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ | |
| 1042 | #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ | |
| 1043 | #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ | |
| 1044 | #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ | |
| 1045 | #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ | |
| 1046 | #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ | |
| 1047 | #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ | |
| 1048 | #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ | |
| 1049 | #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ | |
| 1050 | #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ | |
| 1051 | #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ | |
| 1052 | #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ | |
| 1053 | #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ | |
| 1054 | #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ | |
| 1055 | #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ | |
| 1056 | #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ | |
| 1057 | #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ | |
| 1058 | #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ | |
| 1059 | #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ | |
| 1060 | #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ | |
| 1061 | ||
| 1062 | #define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ | |
| 1063 | #define B3RDYPOL 0x00020000 /* B3 RDY Active High */ | |
| 1064 | #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ | |
| 1065 | #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ | |
| 1066 | #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ | |
| 1067 | #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ | |
| 1068 | #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ | |
| 1069 | #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ | |
| 1070 | #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ | |
| 1071 | #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ | |
| 1072 | #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | |
| 1073 | #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | |
| 1074 | #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | |
| 1075 | #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | |
| 1076 | #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ | |
| 1077 | #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ | |
| 1078 | #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ | |
| 1079 | #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ | |
| 1080 | #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ | |
| 1081 | #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ | |
| 1082 | #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ | |
| 1083 | #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ | |
| 1084 | #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ | |
| 1085 | #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ | |
| 1086 | #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ | |
| 1087 | #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ | |
| 1088 | #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ | |
| 1089 | #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ | |
| 1090 | #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ | |
| 1091 | #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ | |
| 1092 | #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ | |
| 1093 | #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ | |
| 1094 | #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ | |
| 1095 | #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ | |
| 1096 | #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ | |
| 1097 | #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ | |
| 1098 | #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ | |
| 1099 | #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ | |
| 1100 | #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ | |
| 1101 | #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ | |
| 1102 | #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ | |
| 1103 | #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ | |
| 1104 | #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ | |
| 1105 | #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ | |
| 1106 | ||
| 1107 | ||
| 1108 | /* ********************** SDRAM CONTROLLER MASKS **********************************************/ | |
| 1109 | /* EBIU_SDGCTL Masks */ | |
| 1110 | #define SCTLE 0x00000001 /* Enable SDRAM Signals */ | |
| 1111 | #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ | |
| 1112 | #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ | |
| 1113 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ | |
| 1114 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | |
| 1115 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | |
| 1116 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | |
| 1117 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | |
| 1118 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | |
| 1119 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | |
| 1120 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | |
| 1121 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | |
| 1122 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | |
| 1123 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | |
| 1124 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | |
| 1125 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | |
| 1126 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | |
| 1127 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | |
| 1128 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | |
| 1129 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | |
| 1130 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | |
| 1131 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | |
| 1132 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | |
| 1133 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | |
| 1134 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | |
| 1135 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | |
| 1136 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | |
| 1137 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | |
| 1138 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | |
| 1139 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | |
| 1140 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | |
| 1141 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | |
| 1142 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | |
| 1143 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | |
| 1144 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | |
| 1145 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | |
| 1146 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | |
| 1147 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | |
| 1148 | #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ | |
| 1149 | #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ | |
| 1150 | #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ | |
| 1151 | #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ | |
| 1152 | #define EBUFE 0x02000000 /* Enable External Buffering Timing */ | |
| 1153 | #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ | |
| 1154 | #define EMREN 0x10000000 /* Extended Mode Register Enable */ | |
| 1155 | #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ | |
| 1156 | #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ | |
| 1157 | ||
| 1158 | /* EBIU_SDBCTL Masks */ | |
| 1159 | #define EBE 0x0001 /* Enable SDRAM External Bank */ | |
| 1160 | #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ | |
| 1161 | #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ | |
| 1162 | #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ | |
| 1163 | #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ | |
| 1164 | #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ | |
| 1165 | #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ | |
| 1166 | #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ | |
| 1167 | #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ | |
| 1168 | #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ | |
| 1169 | #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ | |
| 1170 | ||
| 1171 | /* EBIU_SDSTAT Masks */ | |
| 1172 | #define SDCI 0x0001 /* SDRAM Controller Idle */ | |
| 1173 | #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ | |
| 1174 | #define SDPUA 0x0004 /* SDRAM Power-Up Active */ | |
| 1175 | #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ | |
| 1176 | #define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ | |
| 1177 | #define BGSTAT 0x0020 /* Bus Grant Status */ | |
| 1178 | ||
| 1179 | ||
| 1180 | /* ************************** DMA CONTROLLER MASKS ********************************/ | |
| 2f6f4bcd BW |
1181 | |
| 1182 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | |
| 1183 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ | |
| 1184 | #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ | |
| 1185 | #define PMAP_PPI 0x0000 /* PPI Port DMA */ | |
| 1186 | #define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ | |
| 1187 | #define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ | |
| 1188 | #define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ | |
| 1189 | #define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ | |
| 1190 | #define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ | |
| 1191 | #define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ | |
| 1192 | #define PMAP_SPI 0x7000 /* SPI Port DMA */ | |
| 1193 | #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ | |
| 1194 | #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ | |
| 1195 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ | |
| 1196 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ | |
| 1197 | ||
| 2f6f4bcd BW |
1198 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ |
| 1199 | /* PPI_CONTROL Masks */ | |
| 1200 | #define PORT_EN 0x0001 /* PPI Port Enable */ | |
| 1201 | #define PORT_DIR 0x0002 /* PPI Port Direction */ | |
| 1202 | #define XFR_TYPE 0x000C /* PPI Transfer Type */ | |
| 1203 | #define PORT_CFG 0x0030 /* PPI Port Configuration */ | |
| 1204 | #define FLD_SEL 0x0040 /* PPI Active Field Select */ | |
| 1205 | #define PACK_EN 0x0080 /* PPI Packing Mode */ | |
| 1206 | #define DMA32 0x0100 /* PPI 32-bit DMA Enable */ | |
| 1207 | #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ | |
| 1208 | #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ | |
| 1209 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ | |
| 1210 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | |
| 1211 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | |
| 1212 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | |
| 1213 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | |
| 1214 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | |
| 1215 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | |
| 1216 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | |
| 1217 | #define DLENGTH 0x3800 /* PPI Data Length */ | |
| 1218 | #define POLC 0x4000 /* PPI Clock Polarity */ | |
| 1219 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | |
| 1220 | ||
| 1221 | /* PPI_STATUS Masks */ | |
| 1222 | #define FLD 0x0400 /* Field Indicator */ | |
| 1223 | #define FT_ERR 0x0800 /* Frame Track Error */ | |
| 1224 | #define OVR 0x1000 /* FIFO Overflow Error */ | |
| 1225 | #define UNDR 0x2000 /* FIFO Underrun Error */ | |
| 1226 | #define ERR_DET 0x4000 /* Error Detected Indicator */ | |
| 1227 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | |
| 1228 | ||
| 1229 | ||
| 1230 | /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ | |
| 1231 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | |
| 1232 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | |
| 1233 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | |
| 1234 | ||
| 1235 | /* TWI_PRESCALE Masks */ | |
| 1236 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | |
| 1237 | #define TWI_ENA 0x0080 /* TWI Enable */ | |
| 1238 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | |
| 1239 | ||
| ba3f5973 | 1240 | /* TWI_SLAVE_CTL Masks */ |
| 2f6f4bcd BW |
1241 | #define SEN 0x0001 /* Slave Enable */ |
| 1242 | #define SADD_LEN 0x0002 /* Slave Address Length */ | |
| 1243 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | |
| 1244 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | |
| 1245 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ | |
| 1246 | ||
| 1247 | /* TWI_SLAVE_STAT Masks */ | |
| 1248 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | |
| 1249 | #define GCALL 0x0002 /* General Call Indicator */ | |
| 1250 | ||
| ba3f5973 | 1251 | /* TWI_MASTER_CTL Masks */ |
| 2f6f4bcd BW |
1252 | #define MEN 0x0001 /* Master Mode Enable */ |
| 1253 | #define MADD_LEN 0x0002 /* Master Address Length */ | |
| 1254 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | |
| 1255 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | |
| 1256 | #define STOP 0x0010 /* Issue Stop Condition */ | |
| 1257 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | |
| 1258 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | |
| 1259 | #define SDAOVR 0x4000 /* Serial Data Override */ | |
| 1260 | #define SCLOVR 0x8000 /* Serial Clock Override */ | |
| 1261 | ||
| 1262 | /* TWI_MASTER_STAT Masks */ | |
| 1263 | #define MPROG 0x0001 /* Master Transfer In Progress */ | |
| 1264 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | |
| 1265 | #define ANAK 0x0004 /* Address Not Acknowledged */ | |
| 1266 | #define DNAK 0x0008 /* Data Not Acknowledged */ | |
| 1267 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | |
| 1268 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | |
| 1269 | #define SDASEN 0x0040 /* Serial Data Sense */ | |
| 1270 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | |
| 1271 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | |
| 1272 | ||
| 1273 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ | |
| 1274 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | |
| 1275 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | |
| 1276 | #define SERR 0x0004 /* Slave Transfer Error */ | |
| 1277 | #define SOVF 0x0008 /* Slave Overflow */ | |
| 1278 | #define MCOMP 0x0010 /* Master Transfer Complete */ | |
| 1279 | #define MERR 0x0020 /* Master Transfer Error */ | |
| 1280 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | |
| 1281 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | |
| 1282 | ||
| 1283 | /* TWI_FIFO_CTRL Masks */ | |
| 1284 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | |
| 1285 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | |
| 1286 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | |
| 1287 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | |
| 1288 | ||
| 1289 | /* TWI_FIFO_STAT Masks */ | |
| 1290 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | |
| 1291 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | |
| 1292 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | |
| 1293 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | |
| 1294 | ||
| 1295 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | |
| 1296 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | |
| 1297 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | |
| 1298 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | |
| 1299 | ||
| 1300 | ||
| 1301 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ | |
| 1302 | /* PORT_MUX Masks */ | |
| 1303 | #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ | |
| 1304 | #define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ | |
| 1305 | #define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ | |
| 1306 | ||
| 1307 | #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ | |
| 1308 | #define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ | |
| 1309 | #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ | |
| 1310 | #define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ | |
| 1311 | ||
| 1312 | #define PFDE 0x0008 /* Port F DMA Request Enable */ | |
| 1313 | #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ | |
| 1314 | #define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ | |
| 1315 | ||
| 1316 | #define PFTE 0x0010 /* Port F Timer Enable */ | |
| 1317 | #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ | |
| 1318 | #define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ | |
| 1319 | ||
| 1320 | #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ | |
| 1321 | #define PFS6E_TIMER 0x0000 /* Enable TMR5 */ | |
| 1322 | #define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ | |
| 1323 | ||
| 1324 | #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ | |
| 1325 | #define PFS5E_TIMER 0x0000 /* Enable TMR4 */ | |
| 1326 | #define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ | |
| 1327 | ||
| 1328 | #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ | |
| 1329 | #define PFS4E_TIMER 0x0000 /* Enable TMR3 */ | |
| 1330 | #define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ | |
| 1331 | ||
| 1332 | #define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ | |
| 1333 | #define PFFE_TIMER 0x0000 /* Enable TMR2 */ | |
| 1334 | #define PFFE_PPI 0x0100 /* Enable PPI FS3 */ | |
| 1335 | ||
| 1336 | #define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ | |
| 1337 | #define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ | |
| 1338 | #define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ | |
| 1339 | ||
| 1340 | #define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ | |
| 1341 | #define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ | |
| 1342 | #define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ | |
| 1343 | ||
| 1344 | #define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ | |
| 1345 | #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ | |
| 1346 | #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ | |
| 1347 | ||
| 1348 | ||
| 1349 | /* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ | |
| 1350 | /* HDMAx_CTL Masks */ | |
| 1351 | #define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ | |
| 1352 | #define REP 0x0002 /* HDMA Request Polarity */ | |
| 1353 | #define UTE 0x0004 /* Urgency Threshold Enable */ | |
| 1354 | #define OIE 0x0010 /* Overflow Interrupt Enable */ | |
| 1355 | #define BDIE 0x0020 /* Block Done Interrupt Enable */ | |
| 1356 | #define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ | |
| 1357 | #define DRQ 0x0300 /* HDMA Request Type */ | |
| 1358 | #define DRQ_NONE 0x0000 /* No Request */ | |
| 1359 | #define DRQ_SINGLE 0x0100 /* Channels Request Single */ | |
| 1360 | #define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ | |
| 1361 | #define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ | |
| 1362 | #define RBC 0x1000 /* Reload BCNT With IBCNT */ | |
| 1363 | #define PS 0x2000 /* HDMA Pin Status */ | |
| 1364 | #define OI 0x4000 /* Overflow Interrupt Generated */ | |
| 1365 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | |
| 1366 | ||
| 1367 | /* entry addresses of the user-callable Boot ROM functions */ | |
| 1368 | ||
| 1369 | #define _BOOTROM_RESET 0xEF000000 | |
| 1370 | #define _BOOTROM_FINAL_INIT 0xEF000002 | |
| 1371 | #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 | |
| 1372 | #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 | |
| 1373 | #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A | |
| 1374 | #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C | |
| 1375 | #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 | |
| 1376 | #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 | |
| 1377 | #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 | |
| 1378 | ||
| 1379 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | |
| 1380 | #define PGDE_UART PFDE_UART | |
| 1381 | #define PGDE_DMA PFDE_DMA | |
| 1382 | #define CKELOW SCKELOW | |
| 1383 | ||
| 1384 | /* HOST Port Registers */ | |
| 1385 | ||
| 1386 | #define HOST_CONTROL 0xffc03400 /* HOST Control Register */ | |
| 1387 | #define HOST_STATUS 0xffc03404 /* HOST Status Register */ | |
| 1388 | #define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ | |
| 1389 | ||
| 1390 | /* Counter Registers */ | |
| 1391 | ||
| 1392 | #define CNT_CONFIG 0xffc03500 /* Configuration Register */ | |
| 1393 | #define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ | |
| 1394 | #define CNT_STATUS 0xffc03508 /* Status Register */ | |
| 1395 | #define CNT_COMMAND 0xffc0350c /* Command Register */ | |
| 1396 | #define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ | |
| 1397 | #define CNT_COUNTER 0xffc03514 /* Counter Register */ | |
| 1398 | #define CNT_MAX 0xffc03518 /* Maximal Count Register */ | |
| 1399 | #define CNT_MIN 0xffc0351c /* Minimal Count Register */ | |
| 1400 | ||
| 1401 | /* OTP/FUSE Registers */ | |
| 1402 | ||
| 1403 | #define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ | |
| 1404 | #define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ | |
| 1405 | #define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ | |
| 1406 | #define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ | |
| 1407 | ||
| 1408 | /* Security Registers */ | |
| 1409 | ||
| 1410 | #define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ | |
| 1411 | #define SECURE_CONTROL 0xffc03624 /* Secure Control */ | |
| 1412 | #define SECURE_STATUS 0xffc03628 /* Secure Status */ | |
| 1413 | ||
| 1414 | /* OTP Read/Write Data Buffer Registers */ | |
| 1415 | ||
| 1416 | #define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | |
| 1417 | #define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | |
| 1418 | #define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | |
| 1419 | #define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | |
| 1420 | ||
| 1421 | /* Motor Control PWM Registers */ | |
| 1422 | ||
| 1423 | #define PWM_CTRL 0xffc03700 /* PWM Control Register */ | |
| 1424 | #define PWM_STAT 0xffc03704 /* PWM Status Register */ | |
| 1425 | #define PWM_TM 0xffc03708 /* PWM Period Register */ | |
| 1426 | #define PWM_DT 0xffc0370c /* PWM Dead Time Register */ | |
| 1427 | #define PWM_GATE 0xffc03710 /* PWM Chopping Control */ | |
| 1428 | #define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */ | |
| 1429 | #define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */ | |
| 1430 | #define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */ | |
| 1431 | #define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */ | |
| 1432 | #define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */ | |
| 1433 | #define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ | |
| 1434 | #define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ | |
| 1435 | #define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ | |
| 1436 | #define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */ | |
| 1437 | #define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */ | |
| 1438 | ||
| 1439 | ||
| 1440 | /* ********************************************************** */ | |
| 1441 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | |
| 1442 | /* and MULTI BIT READ MACROS */ | |
| 1443 | /* ********************************************************** */ | |
| 1444 | ||
| 1445 | /* Bit masks for HOST_CONTROL */ | |
| 1446 | ||
| 1447 | #define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ | |
| 1448 | #define HOST_CNTR_nHOST_EN 0x0 | |
| 1449 | #define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ | |
| 1450 | #define HOST_CNTR_nHOST_END 0x0 | |
| 1451 | #define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ | |
| 1452 | #define HOST_CNTR_nDATA_SIZE 0x0 | |
| 1453 | #define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ | |
| 1454 | #define HOST_CNTR_nHOST_RST 0x0 | |
| 1455 | #define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ | |
| 1456 | #define HOST_CNTR_nHRDY_OVR 0x0 | |
| 1457 | #define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ | |
| 1458 | #define HOST_CNTR_nINT_MODE 0x0 | |
| 1459 | #define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ | |
| 1460 | #define HOST_CNTR_ nBT_EN 0x0 | |
| 1461 | #define HOST_CNTR_EHW 0x100 /* Enable Host Write */ | |
| 1462 | #define HOST_CNTR_nEHW 0x0 | |
| 1463 | #define HOST_CNTR_EHR 0x200 /* Enable Host Read */ | |
| 1464 | #define HOST_CNTR_nEHR 0x0 | |
| 1465 | #define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ | |
| 1466 | #define HOST_CNTR_nBDR 0x0 | |
| 1467 | ||
| 1468 | /* Bit masks for HOST_STATUS */ | |
| 1469 | ||
| 1470 | #define HOST_STAT_READY 0x1 /* DMA Ready */ | |
| 1471 | #define HOST_STAT_nREADY 0x0 | |
| 1472 | #define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ | |
| 1473 | #define HOST_STAT_nFIFOFULL 0x0 | |
| 1474 | #define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ | |
| 1475 | #define HOST_STAT_nFIFOEMPTY 0x0 | |
| 1476 | #define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ | |
| 1477 | #define HOST_STAT_nCOMPLETE 0x0 | |
| 1478 | #define HOST_STAT_HSHK 0x10 /* Host Handshake */ | |
| 1479 | #define HOST_STAT_nHSHK 0x0 | |
| 1480 | #define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ | |
| 1481 | #define HOST_STAT_nTIMEOUT 0x0 | |
| 1482 | #define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ | |
| 1483 | #define HOST_STAT_nHIRQ 0x0 | |
| 1484 | #define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ | |
| 1485 | #define HOST_STAT_nALLOW_CNFG 0x0 | |
| 1486 | #define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ | |
| 1487 | #define HOST_STAT_nDMA_DIR 0x0 | |
| 1488 | #define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ | |
| 1489 | #define HOST_STAT_nBTE 0x0 | |
| 1490 | #define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ | |
| 1491 | #define HOST_STAT_nHOSTRD_DONE 0x0 | |
| 1492 | ||
| 1493 | /* Bit masks for HOST_TIMEOUT */ | |
| 1494 | ||
| 1495 | #define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | |
| 1496 | ||
| 2f6f4bcd BW |
1497 | /* Bit masks for SECURE_SYSSWT */ |
| 1498 | ||
| 1499 | #define EMUDABL 0x1 /* Emulation Disable. */ | |
| 1500 | #define nEMUDABL 0x0 | |
| 1501 | #define RSTDABL 0x2 /* Reset Disable */ | |
| 1502 | #define nRSTDABL 0x0 | |
| 1503 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | |
| 1504 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | |
| 1505 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | |
| 1506 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | |
| 1507 | #define nDMA0OVR 0x0 | |
| 1508 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | |
| 1509 | #define nDMA1OVR 0x0 | |
| 1510 | #define EMUOVR 0x4000 /* Emulation Override */ | |
| 1511 | #define nEMUOVR 0x0 | |
| 1512 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | |
| 1513 | #define nOTPSEN 0x0 | |
| 1514 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | |
| 1515 | ||
| 1516 | /* Bit masks for SECURE_CONTROL */ | |
| 1517 | ||
| 1518 | #define SECURE0 0x1 /* SECURE 0 */ | |
| 1519 | #define nSECURE0 0x0 | |
| 1520 | #define SECURE1 0x2 /* SECURE 1 */ | |
| 1521 | #define nSECURE1 0x0 | |
| 1522 | #define SECURE2 0x4 /* SECURE 2 */ | |
| 1523 | #define nSECURE2 0x0 | |
| 1524 | #define SECURE3 0x8 /* SECURE 3 */ | |
| 1525 | #define nSECURE3 0x0 | |
| 1526 | ||
| 1527 | /* Bit masks for SECURE_STATUS */ | |
| 1528 | ||
| 1529 | #define SECMODE 0x3 /* Secured Mode Control State */ | |
| 1530 | #define NMI 0x4 /* Non Maskable Interrupt */ | |
| 1531 | #define nNMI 0x0 | |
| 1532 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | |
| 1533 | #define nAFVALID 0x0 | |
| 1534 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | |
| 1535 | #define nAFEXIT 0x0 | |
| 1536 | #define SECSTAT 0xe0 /* Secure Status */ | |
| 1537 | ||
| 1538 | ||
| 1539 | ||
| 1540 | #endif /* _DEF_BF51X_H */ |