[net-next-2.6.git] / arch / blackfin / include / asm / bfin_sport.h

/*
 * bfin_sport.h - interface to Blackfin SPORTs
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __BFIN_SPORT_H__
#define __BFIN_SPORT_H__

/* Sport mode: it can be set to TDM, i2s or others */
#define NORM_MODE	0x0
#define TDM_MODE	0x1
#define I2S_MODE	0x2

/* Data format, normal, a-law or u-law */
#define NORM_FORMAT	0x0
#define ALAW_FORMAT	0x2
#define ULAW_FORMAT	0x3

/* Function driver which use sport must initialize the structure */
struct sport_config {
	/* TDM (multichannels), I2S or other mode */
	unsigned int mode:3;

	/* if TDM mode is selected, channels must be set */
	int channels;	/* Must be in 8 units */
	unsigned int frame_delay:4;	/* Delay between frame sync pulse and first bit */

	/* I2S mode */
	unsigned int right_first:1;	/* Right stereo channel first */

	/* In mormal mode, the following item need to be set */
	unsigned int lsb_first:1;	/* order of transmit or receive data */
	unsigned int fsync:1;	/* Frame sync required */
	unsigned int data_indep:1;	/* data independent frame sync generated */
	unsigned int act_low:1;	/* Active low TFS */
	unsigned int late_fsync:1;	/* Late frame sync */
	unsigned int tckfe:1;
	unsigned int sec_en:1;	/* Secondary side enabled */

	/* Choose clock source */
	unsigned int int_clk:1;	/* Internal or external clock */

	/* If external clock is used, the following fields are ignored */
	int serial_clk;
	int fsync_clk;

	unsigned int data_format:2;	/* Normal, u-law or a-law */

	int word_len;		/* How length of the word in bits, 3-32 bits */
	int dma_enabled;
};

/* Userspace interface */
#define SPORT_IOC_MAGIC		'P'
#define SPORT_IOC_CONFIG	_IOWR('P', 0x01, struct sport_config)

#ifdef __KERNEL__

#include <linux/types.h>

/*
 * All Blackfin system MMRs are padded to 32bits even if the register
 * itself is only 16bits.  So use a helper macro to streamline this.
 */
#define __BFP(m) u16 m; u16 __pad_##m
struct sport_register {
	__BFP(tcr1);
	__BFP(tcr2);
	__BFP(tclkdiv);
	__BFP(tfsdiv);
	union {
		u32 tx32;
		u16 tx16;
	};
	u32 __pad_tx;
	union {
		u32 rx32;	/* use the anomaly wrapper below */
		u16 rx16;
	};
	u32 __pad_rx;
	__BFP(rcr1);
	__BFP(rcr2);
	__BFP(rclkdiv);
	__BFP(rfsdiv);
	__BFP(stat);
	__BFP(chnl);
	__BFP(mcmc1);
	__BFP(mcmc2);
	u32 mtcs0;
	u32 mtcs1;
	u32 mtcs2;
	u32 mtcs3;
	u32 mrcs0;
	u32 mrcs1;
	u32 mrcs2;
	u32 mrcs3;
};
#undef __BFP

#define bfin_read_sport_rx32(base) \
({ \
	struct sport_register *__mmrs = (void *)base; \
	u32 __ret; \
	unsigned long flags; \
	if (ANOMALY_05000473) \
		local_irq_save(flags); \
	__ret = __mmrs->rx32; \
	if (ANOMALY_05000473) \
		local_irq_restore(flags); \
	__ret; \
})

#endif

/* SPORT_TCR1 Masks */
#define TSPEN		0x0001	/* TX enable */
#define ITCLK		0x0002	/* Internal TX Clock Select */
#define TDTYPE		0x000C	/* TX Data Formatting Select */
#define DTYPE_NORM	0x0000	/* Data Format Normal */
#define DTYPE_ULAW	0x0008	/* Compand Using u-Law */
#define DTYPE_ALAW	0x000C	/* Compand Using A-Law */
#define TLSBIT		0x0010	/* TX Bit Order */
#define ITFS		0x0200	/* Internal TX Frame Sync Select */
#define TFSR		0x0400	/* TX Frame Sync Required Select */
#define DITFS		0x0800	/* Data Independent TX Frame Sync Select */
#define LTFS		0x1000	/* Low TX Frame Sync Select */
#define LATFS		0x2000	/* Late TX Frame Sync Select */
#define TCKFE		0x4000	/* TX Clock Falling Edge Select */

/* SPORT_TCR2 Masks */
#define SLEN		0x001F	/* SPORT TX Word Length (2 - 31) */
#define DP_SLEN(x)	BFIN_DEPOSIT(SLEN, x)
#define EX_SLEN(x)	BFIN_EXTRACT(SLEN, x)
#define TXSE		0x0100	/* TX Secondary Enable */
#define TSFSE		0x0200	/* TX Stereo Frame Sync Enable */
#define TRFST		0x0400	/* TX Right-First Data Order */

/* SPORT_RCR1 Masks */
#define RSPEN		0x0001	/* RX enable */
#define IRCLK		0x0002	/* Internal RX Clock Select */
#define RDTYPE		0x000C	/* RX Data Formatting Select */
/* DTYPE_* defined above */
#define RLSBIT		0x0010	/* RX Bit Order */
#define IRFS		0x0200	/* Internal RX Frame Sync Select */
#define RFSR		0x0400	/* RX Frame Sync Required Select */
#define LRFS		0x1000	/* Low RX Frame Sync Select */
#define LARFS		0x2000	/* Late RX Frame Sync Select */
#define RCKFE		0x4000	/* RX Clock Falling Edge Select */

/* SPORT_RCR2 Masks */
/* SLEN defined above */
#define RXSE		0x0100	/* RX Secondary Enable */
#define RSFSE		0x0200	/* RX Stereo Frame Sync Enable */
#define RRFST		0x0400	/* Right-First Data Order */

/* SPORT_STAT Masks */
#define RXNE		0x0001	/* RX FIFO Not Empty Status */
#define RUVF		0x0002	/* RX Underflow Status */
#define ROVF		0x0004	/* RX Overflow Status */
#define TXF		0x0008	/* TX FIFO Full Status */
#define TUVF		0x0010	/* TX Underflow Status */
#define TOVF		0x0020	/* TX Overflow Status */
#define TXHRE		0x0040	/* TX Hold Register Empty */

/* SPORT_MCMC1 Masks */
#define SP_WOFF		0x03FF	/* Multichannel Window Offset Field */
#define DP_SP_WOFF(x)	BFIN_DEPOSIT(SP_WOFF, x)
#define EX_SP_WOFF(x)	BFIN_EXTRACT(SP_WOFF, x)
#define SP_WSIZE	0xF000	/* Multichannel Window Size Field */
#define DP_SP_WSIZE(x)	BFIN_DEPOSIT(SP_WSIZE, x)
#define EX_SP_WSIZE(x)	BFIN_EXTRACT(SP_WSIZE, x)

/* SPORT_MCMC2 Masks */
#define MCCRM		0x0003	/* Multichannel Clock Recovery Mode */
#define REC_BYPASS	0x0000	/* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4	0x0002	/* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16	0x0003	/* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE		0x0004	/* Multichannel DMA Transmit Packing */
#define MCDRXPE		0x0008	/* Multichannel DMA Receive Packing */
#define MCMEN		0x0010	/* Multichannel Frame Mode Enable */
#define FSDR		0x0080	/* Multichannel Frame Sync to Data Relationship */
#define MFD		0xF000	/* Multichannel Frame Delay */
#define DP_MFD(x)	BFIN_DEPOSIT(MFD, x)
#define EX_MFD(x)	BFIN_EXTRACT(MFD, x)

#endif
Commit	Line	Data
1394f032	1	/*
3630ac34	2	* bfin_sport.h - interface to Blackfin SPORTs
1394f032	3	*
3630ac34	4	* Copyright 2004-2009 Analog Devices Inc.
1394f032	5	*
fb7b75ab	6	* Licensed under the GPL-2 or later.
1394f032 BW	7	*/
	8
	9	#ifndef __BFIN_SPORT_H__
	10	#define __BFIN_SPORT_H__
	11
1394f032 BW	12	/* Sport mode: it can be set to TDM, i2s or others */
	13	#define NORM_MODE 0x0
	14	#define TDM_MODE 0x1
	15	#define I2S_MODE 0x2
	16
	17	/* Data format, normal, a-law or u-law */
	18	#define NORM_FORMAT 0x0
	19	#define ALAW_FORMAT 0x2
	20	#define ULAW_FORMAT 0x3
1394f032 BW	21
	22	/* Function driver which use sport must initialize the structure */
	23	struct sport_config {
fb7b75ab	24	/* TDM (multichannels), I2S or other mode */
1394f032 BW	25	unsigned int mode:3;
	26
	27	/* if TDM mode is selected, channels must be set */
3630ac34	28	int channels; /* Must be in 8 units */
1394f032 BW	29	unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
	30
	31	/* I2S mode */
	32	unsigned int right_first:1; /* Right stereo channel first */
	33
	34	/* In mormal mode, the following item need to be set */
	35	unsigned int lsb_first:1; /* order of transmit or receive data */
	36	unsigned int fsync:1; /* Frame sync required */
	37	unsigned int data_indep:1; /* data independent frame sync generated */
	38	unsigned int act_low:1; /* Active low TFS */
	39	unsigned int late_fsync:1; /* Late frame sync */
	40	unsigned int tckfe:1;
	41	unsigned int sec_en:1; /* Secondary side enabled */
	42
	43	/* Choose clock source */
	44	unsigned int int_clk:1; /* Internal or external clock */
	45
	46	/* If external clock is used, the following fields are ignored */
	47	int serial_clk;
	48	int fsync_clk;
	49
fb7b75ab	50	unsigned int data_format:2; /* Normal, u-law or a-law */
1394f032 BW	51
	52	int word_len; /* How length of the word in bits, 3-32 bits */
	53	int dma_enabled;
	54	};
	55
fb7b75ab ABL	56	/* Userspace interface */
	57	#define SPORT_IOC_MAGIC 'P'
	58	#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
	59
	60	#ifdef __KERNEL__
	61
3630ac34	62	#include <linux/types.h>
1394f032	63
3630ac34 MF	64	/*
	65	* All Blackfin system MMRs are padded to 32bits even if the register
	66	* itself is only 16bits. So use a helper macro to streamline this.
	67	*/
	68	#define __BFP(m) u16 m; u16 __pad_##m
	69	struct sport_register {
	70	__BFP(tcr1);
	71	__BFP(tcr2);
	72	__BFP(tclkdiv);
	73	__BFP(tfsdiv);
	74	union {
	75	u32 tx32;
	76	u16 tx16;
	77	};
	78	u32 __pad_tx;
	79	union {
	80	u32 rx32; /* use the anomaly wrapper below */
	81	u16 rx16;
	82	};
	83	u32 __pad_rx;
	84	__BFP(rcr1);
	85	__BFP(rcr2);
	86	__BFP(rclkdiv);
	87	__BFP(rfsdiv);
	88	__BFP(stat);
	89	__BFP(chnl);
	90	__BFP(mcmc1);
	91	__BFP(mcmc2);
	92	u32 mtcs0;
	93	u32 mtcs1;
	94	u32 mtcs2;
	95	u32 mtcs3;
	96	u32 mrcs0;
	97	u32 mrcs1;
	98	u32 mrcs2;
	99	u32 mrcs3;
1394f032	100	};
3630ac34 MF	101	#undef __BFP
	102
	103	#define bfin_read_sport_rx32(base) \
	104	({ \
	105	struct sport_register __mmrs = (void )base; \
	106	u32 __ret; \
	107	unsigned long flags; \
	108	if (ANOMALY_05000473) \
	109	local_irq_save(flags); \
	110	__ret = __mmrs->rx32; \
	111	if (ANOMALY_05000473) \
	112	local_irq_restore(flags); \
	113	__ret; \
	114	})
1394f032	115
fb7b75ab ABL	116	#endif
fb7b75ab ABL	117
3630ac34 MF	118	/* SPORT_TCR1 Masks */
	119	#define TSPEN 0x0001 /* TX enable */
	120	#define ITCLK 0x0002 /* Internal TX Clock Select */
	121	#define TDTYPE 0x000C /* TX Data Formatting Select */
	122	#define DTYPE_NORM 0x0000 /* Data Format Normal */
	123	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
	124	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
	125	#define TLSBIT 0x0010 /* TX Bit Order */
	126	#define ITFS 0x0200 /* Internal TX Frame Sync Select */
	127	#define TFSR 0x0400 /* TX Frame Sync Required Select */
	128	#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
	129	#define LTFS 0x1000 /* Low TX Frame Sync Select */
	130	#define LATFS 0x2000 /* Late TX Frame Sync Select */
	131	#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
	132
	133	/* SPORT_TCR2 Masks */
	134	#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
	135	#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
	136	#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
	137	#define TXSE 0x0100 /* TX Secondary Enable */
	138	#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
	139	#define TRFST 0x0400 /* TX Right-First Data Order */
	140
	141	/* SPORT_RCR1 Masks */
	142	#define RSPEN 0x0001 /* RX enable */
	143	#define IRCLK 0x0002 /* Internal RX Clock Select */
	144	#define RDTYPE 0x000C /* RX Data Formatting Select */
	145	/* DTYPE_* defined above */
	146	#define RLSBIT 0x0010 /* RX Bit Order */
	147	#define IRFS 0x0200 /* Internal RX Frame Sync Select */
	148	#define RFSR 0x0400 /* RX Frame Sync Required Select */
	149	#define LRFS 0x1000 /* Low RX Frame Sync Select */
	150	#define LARFS 0x2000 /* Late RX Frame Sync Select */
	151	#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
	152
	153	/* SPORT_RCR2 Masks */
	154	/* SLEN defined above */
	155	#define RXSE 0x0100 /* RX Secondary Enable */
	156	#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
	157	#define RRFST 0x0400 /* Right-First Data Order */
	158
	159	/* SPORT_STAT Masks */
	160	#define RXNE 0x0001 /* RX FIFO Not Empty Status */
	161	#define RUVF 0x0002 /* RX Underflow Status */
	162	#define ROVF 0x0004 /* RX Overflow Status */
	163	#define TXF 0x0008 /* TX FIFO Full Status */
	164	#define TUVF 0x0010 /* TX Underflow Status */
	165	#define TOVF 0x0020 /* TX Overflow Status */
	166	#define TXHRE 0x0040 /* TX Hold Register Empty */
	167
	168	/* SPORT_MCMC1 Masks */
	169	#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
	170	#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
	171	#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
	172	#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
	173	#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
	174	#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
	175
	176	/* SPORT_MCMC2 Masks */
	177	#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
	178	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
	179	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
	180	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
	181	#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
182	#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
183	#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
184	#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
185	#define MFD 0xF000 /* Multichannel Frame Delay */
186	#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
187	#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
1394f032	188
fb7b75ab	189	#endif