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Commit | Line | Data |
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1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
1394f032 | 29 | |
e3defffe AL |
30 | config ZONE_DMA |
31 | bool | |
32 | default y | |
33 | ||
1394f032 BW |
34 | config GENERIC_FIND_NEXT_BIT |
35 | bool | |
36 | default y | |
37 | ||
38 | config GENERIC_HWEIGHT | |
39 | bool | |
40 | default y | |
41 | ||
42 | config GENERIC_HARDIRQS | |
43 | bool | |
44 | default y | |
45 | ||
46 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 47 | bool |
1394f032 BW |
48 | default y |
49 | ||
b2d1583f | 50 | config GENERIC_GPIO |
1394f032 BW |
51 | bool |
52 | default y | |
53 | ||
54 | config FORCE_MAX_ZONEORDER | |
55 | int | |
56 | default "14" | |
57 | ||
58 | config GENERIC_CALIBRATE_DELAY | |
59 | bool | |
60 | default y | |
61 | ||
7d2284b0 MD |
62 | config HARDWARE_PM |
63 | def_bool y | |
64 | depends on OPROFILE | |
65 | ||
1394f032 BW |
66 | source "init/Kconfig" |
67 | source "kernel/Kconfig.preempt" | |
68 | ||
69 | menu "Blackfin Processor Options" | |
70 | ||
71 | comment "Processor and Board Settings" | |
72 | ||
73 | choice | |
74 | prompt "CPU" | |
75 | default BF533 | |
76 | ||
59003145 MH |
77 | config BF522 |
78 | bool "BF522" | |
79 | help | |
80 | BF522 Processor Support. | |
81 | ||
1545a111 MF |
82 | config BF523 |
83 | bool "BF523" | |
84 | help | |
85 | BF523 Processor Support. | |
86 | ||
87 | config BF524 | |
88 | bool "BF524" | |
89 | help | |
90 | BF524 Processor Support. | |
91 | ||
59003145 MH |
92 | config BF525 |
93 | bool "BF525" | |
94 | help | |
95 | BF525 Processor Support. | |
96 | ||
1545a111 MF |
97 | config BF526 |
98 | bool "BF526" | |
99 | help | |
100 | BF526 Processor Support. | |
101 | ||
59003145 MH |
102 | config BF527 |
103 | bool "BF527" | |
104 | help | |
105 | BF527 Processor Support. | |
106 | ||
1394f032 BW |
107 | config BF531 |
108 | bool "BF531" | |
109 | help | |
110 | BF531 Processor Support. | |
111 | ||
112 | config BF532 | |
113 | bool "BF532" | |
114 | help | |
115 | BF532 Processor Support. | |
116 | ||
117 | config BF533 | |
118 | bool "BF533" | |
119 | help | |
120 | BF533 Processor Support. | |
121 | ||
122 | config BF534 | |
123 | bool "BF534" | |
124 | help | |
125 | BF534 Processor Support. | |
126 | ||
127 | config BF536 | |
128 | bool "BF536" | |
129 | help | |
130 | BF536 Processor Support. | |
131 | ||
132 | config BF537 | |
133 | bool "BF537" | |
134 | help | |
135 | BF537 Processor Support. | |
136 | ||
24a07a12 RH |
137 | config BF542 |
138 | bool "BF542" | |
139 | help | |
140 | BF542 Processor Support. | |
141 | ||
142 | config BF544 | |
143 | bool "BF544" | |
144 | help | |
145 | BF544 Processor Support. | |
146 | ||
7c7fd170 MF |
147 | config BF547 |
148 | bool "BF547" | |
149 | help | |
150 | BF547 Processor Support. | |
151 | ||
24a07a12 RH |
152 | config BF548 |
153 | bool "BF548" | |
154 | help | |
155 | BF548 Processor Support. | |
156 | ||
157 | config BF549 | |
158 | bool "BF549" | |
159 | help | |
160 | BF549 Processor Support. | |
161 | ||
1394f032 BW |
162 | config BF561 |
163 | bool "BF561" | |
164 | help | |
165 | Not Supported Yet - Work in progress - BF561 Processor Support. | |
166 | ||
167 | endchoice | |
168 | ||
169 | choice | |
170 | prompt "Silicon Rev" | |
59003145 | 171 | default BF_REV_0_1 if BF527 |
1394f032 BW |
172 | default BF_REV_0_2 if BF537 |
173 | default BF_REV_0_3 if BF533 | |
24a07a12 RH |
174 | default BF_REV_0_0 if BF549 |
175 | ||
176 | config BF_REV_0_0 | |
177 | bool "0.0" | |
d07f4380 | 178 | depends on (BF52x || BF54x) |
59003145 MH |
179 | |
180 | config BF_REV_0_1 | |
d07f4380 MF |
181 | bool "0.1" |
182 | depends on (BF52x || BF54x) | |
1394f032 BW |
183 | |
184 | config BF_REV_0_2 | |
185 | bool "0.2" | |
186 | depends on (BF537 || BF536 || BF534) | |
187 | ||
188 | config BF_REV_0_3 | |
189 | bool "0.3" | |
190 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
191 | ||
192 | config BF_REV_0_4 | |
193 | bool "0.4" | |
194 | depends on (BF561 || BF533 || BF532 || BF531) | |
195 | ||
196 | config BF_REV_0_5 | |
197 | bool "0.5" | |
198 | depends on (BF561 || BF533 || BF532 || BF531) | |
199 | ||
de3025f4 JZ |
200 | config BF_REV_ANY |
201 | bool "any" | |
202 | ||
203 | config BF_REV_NONE | |
204 | bool "none" | |
205 | ||
1394f032 BW |
206 | endchoice |
207 | ||
59003145 MH |
208 | config BF52x |
209 | bool | |
1545a111 | 210 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
211 | default y |
212 | ||
24a07a12 RH |
213 | config BF53x |
214 | bool | |
215 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
216 | default y | |
217 | ||
218 | config BF54x | |
219 | bool | |
7c7fd170 | 220 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
221 | default y |
222 | ||
1394f032 BW |
223 | config MEM_GENERIC_BOARD |
224 | bool | |
225 | depends on GENERIC_BOARD | |
226 | default y | |
227 | ||
228 | config MEM_MT48LC64M4A2FB_7E | |
229 | bool | |
230 | depends on (BFIN533_STAMP) | |
231 | default y | |
232 | ||
233 | config MEM_MT48LC16M16A2TG_75 | |
234 | bool | |
235 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 JH |
236 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
237 | || H8606_HVSISTEMAS) | |
1394f032 BW |
238 | default y |
239 | ||
240 | config MEM_MT48LC32M8A2_75 | |
241 | bool | |
242 | depends on (BFIN537_STAMP || PNAV10) | |
243 | default y | |
244 | ||
245 | config MEM_MT48LC8M32B2B5_7 | |
246 | bool | |
247 | depends on (BFIN561_BLUETECHNIX_CM) | |
248 | default y | |
249 | ||
59003145 MH |
250 | config MEM_MT48LC32M16A2TG_75 |
251 | bool | |
5d1617b2 | 252 | depends on (BFIN527_EZKIT || BFIN532_IP0X) |
59003145 MH |
253 | default y |
254 | ||
59003145 | 255 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
256 | source "arch/blackfin/mach-bf533/Kconfig" |
257 | source "arch/blackfin/mach-bf561/Kconfig" | |
258 | source "arch/blackfin/mach-bf537/Kconfig" | |
24a07a12 | 259 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
260 | |
261 | menu "Board customizations" | |
262 | ||
263 | config CMDLINE_BOOL | |
264 | bool "Default bootloader kernel arguments" | |
265 | ||
266 | config CMDLINE | |
267 | string "Initial kernel command string" | |
268 | depends on CMDLINE_BOOL | |
269 | default "console=ttyBF0,57600" | |
270 | help | |
271 | If you don't have a boot loader capable of passing a command line string | |
272 | to the kernel, you may specify one here. As a minimum, you should specify | |
273 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
274 | ||
f16295e7 | 275 | comment "Clock/PLL Setup" |
1394f032 BW |
276 | |
277 | config CLKIN_HZ | |
278 | int "Crystal Frequency in Hz" | |
279 | default "11059200" if BFIN533_STAMP | |
280 | default "27000000" if BFIN533_EZKIT | |
ab472a04 | 281 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS) |
1394f032 BW |
282 | default "30000000" if BFIN561_EZKIT |
283 | default "24576000" if PNAV10 | |
5d1617b2 | 284 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
285 | help |
286 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
287 | ||
f16295e7 RG |
288 | config BFIN_KERNEL_CLOCK |
289 | bool "Re-program Clocks while Kernel boots?" | |
290 | default n | |
291 | help | |
292 | This option decides if kernel clocks are re-programed from the | |
293 | bootloader settings. If the clocks are not set, the SDRAM settings | |
294 | are also not changed, and the Bootloader does 100% of the hardware | |
295 | configuration. | |
296 | ||
a086ee22 MF |
297 | config MEM_SIZE |
298 | int "SDRAM Memory Size in MBytes" | |
299 | depends on BFIN_KERNEL_CLOCK | |
300 | default 64 | |
301 | ||
618835a0 MF |
302 | config MEM_ADD_WIDTH |
303 | int "Memory Address Width" | |
304 | depends on BFIN_KERNEL_CLOCK | |
305 | depends on (!BF54x) | |
306 | default 9 if BFIN533_EZKIT | |
307 | default 9 if BFIN561_EZKIT | |
308 | default 9 if H8606_HVSISTEMAS | |
309 | default 10 if BFIN527_EZKIT | |
310 | default 10 if BFIN537_STAMP | |
311 | default 11 if BFIN533_STAMP | |
312 | default 10 if PNAV10 | |
5d1617b2 | 313 | default 10 if BFIN532_IP0X |
618835a0 | 314 | |
f16295e7 | 315 | config PLL_BYPASS |
e4e9a7ad MF |
316 | bool "Bypass PLL" |
317 | depends on BFIN_KERNEL_CLOCK | |
318 | default n | |
f16295e7 RG |
319 | |
320 | config CLKIN_HALF | |
321 | bool "Half Clock In" | |
322 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
323 | default n | |
324 | help | |
325 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
326 | ||
327 | config VCO_MULT | |
328 | int "VCO Multiplier" | |
329 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
330 | range 1 64 | |
331 | default "22" if BFIN533_EZKIT | |
332 | default "45" if BFIN533_STAMP | |
db68254f | 333 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) |
f16295e7 RG |
334 | default "22" if BFIN533_BLUETECHNIX_CM |
335 | default "20" if BFIN537_BLUETECHNIX_CM | |
336 | default "20" if BFIN561_BLUETECHNIX_CM | |
337 | default "20" if BFIN561_EZKIT | |
ab472a04 | 338 | default "16" if H8606_HVSISTEMAS |
f16295e7 RG |
339 | help |
340 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
341 | PLL Frequency = (Crystal Frequency) * (this setting) | |
342 | ||
343 | choice | |
344 | prompt "Core Clock Divider" | |
345 | depends on BFIN_KERNEL_CLOCK | |
346 | default CCLK_DIV_1 | |
347 | help | |
348 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
349 | Core Frequency = (PLL frequency) / (this setting) | |
350 | ||
351 | config CCLK_DIV_1 | |
352 | bool "1" | |
353 | ||
354 | config CCLK_DIV_2 | |
355 | bool "2" | |
356 | ||
357 | config CCLK_DIV_4 | |
358 | bool "4" | |
359 | ||
360 | config CCLK_DIV_8 | |
361 | bool "8" | |
362 | endchoice | |
363 | ||
364 | config SCLK_DIV | |
365 | int "System Clock Divider" | |
366 | depends on BFIN_KERNEL_CLOCK | |
367 | range 1 15 | |
368 | default 5 if BFIN533_EZKIT | |
369 | default 5 if BFIN533_STAMP | |
db68254f | 370 | default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) |
f16295e7 RG |
371 | default 5 if BFIN533_BLUETECHNIX_CM |
372 | default 4 if BFIN537_BLUETECHNIX_CM | |
373 | default 4 if BFIN561_BLUETECHNIX_CM | |
374 | default 5 if BFIN561_EZKIT | |
ab472a04 | 375 | default 3 if H8606_HVSISTEMAS |
f16295e7 RG |
376 | help |
377 | This sets the frequency of the system clock (including SDRAM or DDR). | |
378 | This can be between 1 and 15 | |
379 | System Clock = (PLL frequency) / (this setting) | |
380 | ||
a086ee22 MF |
381 | config MAX_MEM_SIZE |
382 | int "Max SDRAM Memory Size in MBytes" | |
383 | depends on !BFIN_KERNEL_CLOCK && !MPU | |
384 | default 512 | |
385 | help | |
386 | This is the max memory size that the kernel will create CPLB | |
387 | tables for. Your system will not be able to handle any more. | |
388 | ||
f16295e7 RG |
389 | # |
390 | # Max & Min Speeds for various Chips | |
391 | # | |
392 | config MAX_VCO_HZ | |
393 | int | |
394 | default 600000000 if BF522 | |
1545a111 MF |
395 | default 400000000 if BF523 |
396 | default 400000000 if BF524 | |
f16295e7 | 397 | default 600000000 if BF525 |
1545a111 | 398 | default 400000000 if BF526 |
f16295e7 RG |
399 | default 600000000 if BF527 |
400 | default 400000000 if BF531 | |
401 | default 400000000 if BF532 | |
402 | default 750000000 if BF533 | |
403 | default 500000000 if BF534 | |
404 | default 400000000 if BF536 | |
405 | default 600000000 if BF537 | |
f72eecb9 RG |
406 | default 533333333 if BF538 |
407 | default 533333333 if BF539 | |
f16295e7 | 408 | default 600000000 if BF542 |
f72eecb9 | 409 | default 533333333 if BF544 |
1545a111 MF |
410 | default 600000000 if BF547 |
411 | default 600000000 if BF548 | |
f72eecb9 | 412 | default 533333333 if BF549 |
f16295e7 RG |
413 | default 600000000 if BF561 |
414 | ||
415 | config MIN_VCO_HZ | |
416 | int | |
417 | default 50000000 | |
418 | ||
419 | config MAX_SCLK_HZ | |
420 | int | |
f72eecb9 | 421 | default 133333333 |
f16295e7 RG |
422 | |
423 | config MIN_SCLK_HZ | |
424 | int | |
425 | default 27000000 | |
426 | ||
427 | comment "Kernel Timer/Scheduler" | |
428 | ||
429 | source kernel/Kconfig.hz | |
430 | ||
8b5f79f9 VM |
431 | config GENERIC_TIME |
432 | bool "Generic time" | |
433 | default y | |
434 | ||
435 | config GENERIC_CLOCKEVENTS | |
436 | bool "Generic clock events" | |
437 | depends on GENERIC_TIME | |
438 | default y | |
439 | ||
440 | config CYCLES_CLOCKSOURCE | |
441 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | |
442 | depends on EXPERIMENTAL | |
443 | depends on GENERIC_CLOCKEVENTS | |
444 | depends on !BFIN_SCRATCH_REG_CYCLES | |
445 | default n | |
446 | help | |
447 | If you say Y here, you will enable support for using the 'cycles' | |
448 | registers as a clock source. Doing so means you will be unable to | |
449 | safely write to the 'cycles' register during runtime. You will | |
450 | still be able to read it (such as for performance monitoring), but | |
451 | writing the registers will most likely crash the kernel. | |
452 | ||
453 | source kernel/time/Kconfig | |
454 | ||
f16295e7 RG |
455 | comment "Memory Setup" |
456 | ||
971d5bc4 SZ |
457 | choice |
458 | prompt "DDR SDRAM Chip Type" | |
db68254f | 459 | depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) |
971d5bc4 SZ |
460 | default MEM_MT46V32M16_5B |
461 | ||
462 | config MEM_MT46V32M16_6T | |
463 | bool "MT46V32M16_6T" | |
464 | ||
465 | config MEM_MT46V32M16_5B | |
466 | bool "MT46V32M16_5B" | |
467 | endchoice | |
468 | ||
1394f032 BW |
469 | config ENET_FLASH_PIN |
470 | int "PF port/pin used for flash and ethernet sharing" | |
471 | depends on (BFIN533_STAMP) | |
472 | default 0 | |
473 | help | |
474 | PF port/pin used for flash and ethernet sharing to allow other PF | |
475 | pins to be used on other platforms without having to touch common | |
476 | code. | |
477 | For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc. | |
478 | ||
479 | config BOOT_LOAD | |
480 | hex "Kernel load address for booting" | |
481 | default "0x1000" | |
2d8f161f | 482 | range 0x1000 0x20000000 |
1394f032 BW |
483 | help |
484 | This option allows you to set the load address of the kernel. | |
485 | This can be useful if you are on a board which has a small amount | |
486 | of memory or you wish to reserve some memory at the beginning of | |
487 | the address space. | |
488 | ||
2d8f161f MF |
489 | Note that you need to keep this value above 4k (0x1000) as this |
490 | memory region is used to capture NULL pointer references as well | |
491 | as some core kernel functions. | |
1394f032 | 492 | |
f0b5d12f MF |
493 | choice |
494 | prompt "Blackfin Exception Scratch Register" | |
495 | default BFIN_SCRATCH_REG_RETN | |
496 | help | |
497 | Select the resource to reserve for the Exception handler: | |
498 | - RETN: Non-Maskable Interrupt (NMI) | |
499 | - RETE: Exception Return (JTAG/ICE) | |
500 | - CYCLES: Performance counter | |
501 | ||
502 | If you are unsure, please select "RETN". | |
503 | ||
504 | config BFIN_SCRATCH_REG_RETN | |
505 | bool "RETN" | |
506 | help | |
507 | Use the RETN register in the Blackfin exception handler | |
508 | as a stack scratch register. This means you cannot | |
509 | safely use NMI on the Blackfin while running Linux, but | |
510 | you can debug the system with a JTAG ICE and use the | |
511 | CYCLES performance registers. | |
512 | ||
513 | If you are unsure, please select "RETN". | |
514 | ||
515 | config BFIN_SCRATCH_REG_RETE | |
516 | bool "RETE" | |
517 | help | |
518 | Use the RETE register in the Blackfin exception handler | |
519 | as a stack scratch register. This means you cannot | |
520 | safely use a JTAG ICE while debugging a Blackfin board, | |
521 | but you can safely use the CYCLES performance registers | |
522 | and the NMI. | |
523 | ||
524 | If you are unsure, please select "RETN". | |
525 | ||
526 | config BFIN_SCRATCH_REG_CYCLES | |
527 | bool "CYCLES" | |
528 | help | |
529 | Use the CYCLES register in the Blackfin exception handler | |
530 | as a stack scratch register. This means you cannot | |
531 | safely use the CYCLES performance registers on a Blackfin | |
532 | board at anytime, but you can debug the system with a JTAG | |
533 | ICE and use the NMI. | |
534 | ||
535 | If you are unsure, please select "RETN". | |
536 | ||
537 | endchoice | |
538 | ||
1394f032 BW |
539 | endmenu |
540 | ||
541 | ||
542 | menu "Blackfin Kernel Optimizations" | |
543 | ||
1394f032 BW |
544 | comment "Memory Optimizations" |
545 | ||
546 | config I_ENTRY_L1 | |
547 | bool "Locate interrupt entry code in L1 Memory" | |
548 | default y | |
549 | help | |
01dd2fbf ML |
550 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
551 | into L1 instruction memory. (less latency) | |
1394f032 BW |
552 | |
553 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 554 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
555 | default y |
556 | help | |
01dd2fbf | 557 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 558 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 559 | (less latency) |
1394f032 BW |
560 | |
561 | config DO_IRQ_L1 | |
562 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
563 | default y | |
564 | help | |
01dd2fbf ML |
565 | If enabled, the frequently called do_irq dispatcher function is linked |
566 | into L1 instruction memory. (less latency) | |
1394f032 BW |
567 | |
568 | config CORE_TIMER_IRQ_L1 | |
569 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
570 | default y | |
571 | help | |
01dd2fbf ML |
572 | If enabled, the frequently called timer_interrupt() function is linked |
573 | into L1 instruction memory. (less latency) | |
1394f032 BW |
574 | |
575 | config IDLE_L1 | |
576 | bool "Locate frequently idle function in L1 Memory" | |
577 | default y | |
578 | help | |
01dd2fbf ML |
579 | If enabled, the frequently called idle function is linked |
580 | into L1 instruction memory. (less latency) | |
1394f032 BW |
581 | |
582 | config SCHEDULE_L1 | |
583 | bool "Locate kernel schedule function in L1 Memory" | |
584 | default y | |
585 | help | |
01dd2fbf ML |
586 | If enabled, the frequently called kernel schedule is linked |
587 | into L1 instruction memory. (less latency) | |
1394f032 BW |
588 | |
589 | config ARITHMETIC_OPS_L1 | |
590 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
591 | default y | |
592 | help | |
01dd2fbf ML |
593 | If enabled, arithmetic functions are linked |
594 | into L1 instruction memory. (less latency) | |
1394f032 BW |
595 | |
596 | config ACCESS_OK_L1 | |
597 | bool "Locate access_ok function in L1 Memory" | |
598 | default y | |
599 | help | |
01dd2fbf ML |
600 | If enabled, the access_ok function is linked |
601 | into L1 instruction memory. (less latency) | |
1394f032 BW |
602 | |
603 | config MEMSET_L1 | |
604 | bool "Locate memset function in L1 Memory" | |
605 | default y | |
606 | help | |
01dd2fbf ML |
607 | If enabled, the memset function is linked |
608 | into L1 instruction memory. (less latency) | |
1394f032 BW |
609 | |
610 | config MEMCPY_L1 | |
611 | bool "Locate memcpy function in L1 Memory" | |
612 | default y | |
613 | help | |
01dd2fbf ML |
614 | If enabled, the memcpy function is linked |
615 | into L1 instruction memory. (less latency) | |
1394f032 BW |
616 | |
617 | config SYS_BFIN_SPINLOCK_L1 | |
618 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
619 | default y | |
620 | help | |
01dd2fbf ML |
621 | If enabled, sys_bfin_spinlock function is linked |
622 | into L1 instruction memory. (less latency) | |
1394f032 BW |
623 | |
624 | config IP_CHECKSUM_L1 | |
625 | bool "Locate IP Checksum function in L1 Memory" | |
626 | default n | |
627 | help | |
01dd2fbf ML |
628 | If enabled, the IP Checksum function is linked |
629 | into L1 instruction memory. (less latency) | |
1394f032 BW |
630 | |
631 | config CACHELINE_ALIGNED_L1 | |
632 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
633 | default y if !BF54x |
634 | default n if BF54x | |
1394f032 BW |
635 | depends on !BF531 |
636 | help | |
01dd2fbf ML |
637 | If enabled, cacheline_anligned data is linked |
638 | into L1 data memory. (less latency) | |
1394f032 BW |
639 | |
640 | config SYSCALL_TAB_L1 | |
641 | bool "Locate Syscall Table L1 Data Memory" | |
642 | default n | |
643 | depends on !BF531 | |
644 | help | |
01dd2fbf ML |
645 | If enabled, the Syscall LUT is linked |
646 | into L1 data memory. (less latency) | |
1394f032 BW |
647 | |
648 | config CPLB_SWITCH_TAB_L1 | |
649 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
650 | default n | |
651 | depends on !BF531 | |
652 | help | |
01dd2fbf ML |
653 | If enabled, the CPLB Switch Tables are linked |
654 | into L1 data memory. (less latency) | |
1394f032 BW |
655 | |
656 | endmenu | |
657 | ||
658 | ||
659 | choice | |
660 | prompt "Kernel executes from" | |
661 | help | |
662 | Choose the memory type that the kernel will be running in. | |
663 | ||
664 | config RAMKERNEL | |
665 | bool "RAM" | |
666 | help | |
667 | The kernel will be resident in RAM when running. | |
668 | ||
669 | config ROMKERNEL | |
670 | bool "ROM" | |
671 | help | |
672 | The kernel will be resident in FLASH/ROM when running. | |
673 | ||
674 | endchoice | |
675 | ||
676 | source "mm/Kconfig" | |
677 | ||
780431e3 MF |
678 | config BFIN_GPTIMERS |
679 | tristate "Enable Blackfin General Purpose Timers API" | |
680 | default n | |
681 | help | |
682 | Enable support for the General Purpose Timers API. If you | |
683 | are unsure, say N. | |
684 | ||
685 | To compile this driver as a module, choose M here: the module | |
686 | will be called gptimers.ko. | |
687 | ||
1394f032 BW |
688 | config BFIN_DMA_5XX |
689 | bool "Enable DMA Support" | |
59003145 | 690 | depends on (BF52x || BF53x || BF561 || BF54x) |
1394f032 BW |
691 | default y |
692 | help | |
693 | DMA driver for BF5xx. | |
694 | ||
695 | choice | |
696 | prompt "Uncached SDRAM region" | |
697 | default DMA_UNCACHED_1M | |
247537b9 | 698 | depends on BFIN_DMA_5XX |
1394f032 BW |
699 | config DMA_UNCACHED_2M |
700 | bool "Enable 2M DMA region" | |
701 | config DMA_UNCACHED_1M | |
702 | bool "Enable 1M DMA region" | |
703 | config DMA_UNCACHED_NONE | |
704 | bool "Disable DMA region" | |
705 | endchoice | |
706 | ||
707 | ||
708 | comment "Cache Support" | |
3bebca2d | 709 | config BFIN_ICACHE |
1394f032 | 710 | bool "Enable ICACHE" |
3bebca2d | 711 | config BFIN_DCACHE |
1394f032 | 712 | bool "Enable DCACHE" |
3bebca2d | 713 | config BFIN_DCACHE_BANKA |
1394f032 | 714 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 715 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 716 | default n |
3bebca2d RG |
717 | config BFIN_ICACHE_LOCK |
718 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
719 | |
720 | choice | |
721 | prompt "Policy" | |
3bebca2d RG |
722 | depends on BFIN_DCACHE |
723 | default BFIN_WB | |
724 | config BFIN_WB | |
1394f032 BW |
725 | bool "Write back" |
726 | help | |
727 | Write Back Policy: | |
728 | Cached data will be written back to SDRAM only when needed. | |
729 | This can give a nice increase in performance, but beware of | |
730 | broken drivers that do not properly invalidate/flush their | |
731 | cache. | |
732 | ||
733 | Write Through Policy: | |
734 | Cached data will always be written back to SDRAM when the | |
735 | cache is updated. This is a completely safe setting, but | |
736 | performance is worse than Write Back. | |
737 | ||
738 | If you are unsure of the options and you want to be safe, | |
739 | then go with Write Through. | |
740 | ||
3bebca2d | 741 | config BFIN_WT |
1394f032 BW |
742 | bool "Write through" |
743 | help | |
744 | Write Back Policy: | |
745 | Cached data will be written back to SDRAM only when needed. | |
746 | This can give a nice increase in performance, but beware of | |
747 | broken drivers that do not properly invalidate/flush their | |
748 | cache. | |
749 | ||
750 | Write Through Policy: | |
751 | Cached data will always be written back to SDRAM when the | |
752 | cache is updated. This is a completely safe setting, but | |
753 | performance is worse than Write Back. | |
754 | ||
755 | If you are unsure of the options and you want to be safe, | |
756 | then go with Write Through. | |
757 | ||
758 | endchoice | |
759 | ||
760 | config L1_MAX_PIECE | |
761 | int "Set the max L1 SRAM pieces" | |
762 | default 16 | |
763 | help | |
764 | Set the max memory pieces for the L1 SRAM allocation algorithm. | |
765 | Min value is 16. Max value is 1024. | |
766 | ||
b97b8a99 BS |
767 | |
768 | config MPU | |
769 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
770 | default n | |
771 | help | |
772 | Use the processor's MPU to protect applications from accessing | |
773 | memory they do not own. This comes at a performance penalty | |
774 | and is recommended only for debugging. | |
775 | ||
1394f032 BW |
776 | comment "Asynchonous Memory Configuration" |
777 | ||
ddf416b2 | 778 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
779 | config C_AMCKEN |
780 | bool "Enable CLKOUT" | |
781 | default y | |
782 | ||
783 | config C_CDPRIO | |
784 | bool "DMA has priority over core for ext. accesses" | |
785 | default n | |
786 | ||
787 | config C_B0PEN | |
788 | depends on BF561 | |
789 | bool "Bank 0 16 bit packing enable" | |
790 | default y | |
791 | ||
792 | config C_B1PEN | |
793 | depends on BF561 | |
794 | bool "Bank 1 16 bit packing enable" | |
795 | default y | |
796 | ||
797 | config C_B2PEN | |
798 | depends on BF561 | |
799 | bool "Bank 2 16 bit packing enable" | |
800 | default y | |
801 | ||
802 | config C_B3PEN | |
803 | depends on BF561 | |
804 | bool "Bank 3 16 bit packing enable" | |
805 | default n | |
806 | ||
807 | choice | |
808 | prompt"Enable Asynchonous Memory Banks" | |
809 | default C_AMBEN_ALL | |
810 | ||
811 | config C_AMBEN | |
812 | bool "Disable All Banks" | |
813 | ||
814 | config C_AMBEN_B0 | |
815 | bool "Enable Bank 0" | |
816 | ||
817 | config C_AMBEN_B0_B1 | |
818 | bool "Enable Bank 0 & 1" | |
819 | ||
820 | config C_AMBEN_B0_B1_B2 | |
821 | bool "Enable Bank 0 & 1 & 2" | |
822 | ||
823 | config C_AMBEN_ALL | |
824 | bool "Enable All Banks" | |
825 | endchoice | |
826 | endmenu | |
827 | ||
828 | menu "EBIU_AMBCTL Control" | |
829 | config BANK_0 | |
830 | hex "Bank 0" | |
831 | default 0x7BB0 | |
832 | ||
833 | config BANK_1 | |
834 | hex "Bank 1" | |
835 | default 0x7BB0 | |
836 | ||
837 | config BANK_2 | |
838 | hex "Bank 2" | |
839 | default 0x7BB0 | |
840 | ||
841 | config BANK_3 | |
842 | hex "Bank 3" | |
843 | default 0x99B3 | |
844 | endmenu | |
845 | ||
e40540b3 SZ |
846 | config EBIU_MBSCTLVAL |
847 | hex "EBIU Bank Select Control Register" | |
848 | depends on BF54x | |
849 | default 0 | |
850 | ||
851 | config EBIU_MODEVAL | |
852 | hex "Flash Memory Mode Control Register" | |
853 | depends on BF54x | |
854 | default 1 | |
855 | ||
856 | config EBIU_FCTLVAL | |
857 | hex "Flash Memory Bank Control Register" | |
858 | depends on BF54x | |
859 | default 6 | |
1394f032 BW |
860 | endmenu |
861 | ||
862 | ############################################################################# | |
863 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
864 | ||
865 | config PCI | |
866 | bool "PCI support" | |
867 | help | |
868 | Support for PCI bus. | |
869 | ||
870 | source "drivers/pci/Kconfig" | |
871 | ||
872 | config HOTPLUG | |
873 | bool "Support for hot-pluggable device" | |
874 | help | |
875 | Say Y here if you want to plug devices into your computer while | |
876 | the system is running, and be able to use them quickly. In many | |
877 | cases, the devices can likewise be unplugged at any time too. | |
878 | ||
879 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
880 | size devices such as network cards, modems or hard drives which are | |
881 | plugged into slots found on all modern laptop computers. Another | |
882 | example, used on modern desktops as well as laptops, is USB. | |
883 | ||
884 | Enable HOTPLUG and KMOD, and build a modular kernel. Get agent | |
885 | software (at <http://linux-hotplug.sourceforge.net/>) and install it. | |
886 | Then your kernel will automatically call out to a user mode "policy | |
887 | agent" (/sbin/hotplug) to load modules and set up software needed | |
888 | to use devices as you hotplug them. | |
889 | ||
890 | source "drivers/pcmcia/Kconfig" | |
891 | ||
892 | source "drivers/pci/hotplug/Kconfig" | |
893 | ||
894 | endmenu | |
895 | ||
896 | menu "Executable file formats" | |
897 | ||
898 | source "fs/Kconfig.binfmt" | |
899 | ||
900 | endmenu | |
901 | ||
902 | menu "Power management options" | |
903 | source "kernel/power/Kconfig" | |
904 | ||
f4cb5700 JB |
905 | config ARCH_SUSPEND_POSSIBLE |
906 | def_bool y | |
907 | depends on !SMP | |
908 | ||
1394f032 | 909 | choice |
cfefe3c6 | 910 | prompt "Default Power Saving Mode" |
1394f032 | 911 | depends on PM |
cfefe3c6 MH |
912 | default PM_BFIN_SLEEP_DEEPER |
913 | config PM_BFIN_SLEEP_DEEPER | |
914 | bool "Sleep Deeper" | |
915 | help | |
916 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
917 | power dissipation by disabling the clock to the processor core (CCLK). | |
918 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
919 | to 0.85 V to provide the greatest power savings, while preserving the | |
920 | processor state. | |
921 | The PLL and system clock (SCLK) continue to operate at a very low | |
922 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
923 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
924 | such as GPIO interrupt or RTC activity wakes up the processor. | |
925 | Various Peripherals such as UART, SPORT, PPI may not function as | |
926 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
927 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
928 | ||
929 | config PM_BFIN_SLEEP | |
930 | bool "Sleep" | |
931 | help | |
932 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
933 | dissipation by disabling the clock to the processor core (CCLK). | |
934 | The PLL and system clock (SCLK), however, continue to operate in | |
935 | this mode. Typically an external event or RTC activity will wake | |
936 | up the processor. When in the sleep mode, | |
937 | system DMA access to L1 memory is not supported. | |
938 | endchoice | |
1394f032 | 939 | |
1394f032 BW |
940 | config PM_WAKEUP_BY_GPIO |
941 | bool "Cause Wakeup Event by GPIO" | |
1394f032 BW |
942 | |
943 | config PM_WAKEUP_GPIO_NUMBER | |
944 | int "Wakeup GPIO number" | |
945 | range 0 47 | |
946 | depends on PM_WAKEUP_BY_GPIO | |
947 | default 2 if BFIN537_STAMP | |
948 | ||
949 | choice | |
950 | prompt "GPIO Polarity" | |
951 | depends on PM_WAKEUP_BY_GPIO | |
952 | default PM_WAKEUP_GPIO_POLAR_H | |
953 | config PM_WAKEUP_GPIO_POLAR_H | |
954 | bool "Active High" | |
955 | config PM_WAKEUP_GPIO_POLAR_L | |
956 | bool "Active Low" | |
957 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
958 | bool "Falling EDGE" | |
959 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
960 | bool "Rising EDGE" | |
961 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
962 | bool "Both EDGE" | |
963 | endchoice | |
964 | ||
965 | endmenu | |
966 | ||
24a07a12 | 967 | if (BF537 || BF533 || BF54x) |
1394f032 BW |
968 | |
969 | menu "CPU Frequency scaling" | |
970 | ||
971 | source "drivers/cpufreq/Kconfig" | |
972 | ||
973 | config CPU_FREQ | |
974 | bool | |
975 | default n | |
976 | help | |
977 | If you want to enable this option, you should select the | |
978 | DPMC driver from Character Devices. | |
979 | endmenu | |
980 | ||
981 | endif | |
982 | ||
983 | source "net/Kconfig" | |
984 | ||
985 | source "drivers/Kconfig" | |
986 | ||
987 | source "fs/Kconfig" | |
988 | ||
74ce8322 | 989 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
990 | |
991 | source "security/Kconfig" | |
992 | ||
993 | source "crypto/Kconfig" | |
994 | ||
995 | source "lib/Kconfig" |