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Commit | Line | Data |
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1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 | 7 | |
9e1b9b80 AJ |
8 | config SYMBOL_PREFIX |
9 | string | |
10 | default "_" | |
11 | ||
1394f032 | 12 | config MMU |
bac7d89e | 13 | def_bool n |
1394f032 BW |
14 | |
15 | config FPU | |
bac7d89e | 16 | def_bool n |
1394f032 BW |
17 | |
18 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 19 | def_bool y |
1394f032 BW |
20 | |
21 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 22 | def_bool n |
1394f032 BW |
23 | |
24 | config BLACKFIN | |
bac7d89e | 25 | def_bool y |
1ee76d7e | 26 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 27 | select HAVE_FUNCTION_TRACER |
ec7748b5 | 28 | select HAVE_IDE |
538067c8 MF |
29 | select HAVE_KERNEL_GZIP |
30 | select HAVE_KERNEL_BZIP2 | |
31 | select HAVE_KERNEL_LZMA | |
42d4b839 | 32 | select HAVE_OPROFILE |
a4f0b32c | 33 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 34 | |
ddf9ddac MF |
35 | config GENERIC_CSUM |
36 | def_bool y | |
37 | ||
70f12567 MF |
38 | config GENERIC_BUG |
39 | def_bool y | |
40 | depends on BUG | |
41 | ||
e3defffe | 42 | config ZONE_DMA |
bac7d89e | 43 | def_bool y |
e3defffe | 44 | |
1394f032 | 45 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 46 | def_bool y |
1394f032 BW |
47 | |
48 | config GENERIC_HWEIGHT | |
bac7d89e | 49 | def_bool y |
1394f032 BW |
50 | |
51 | config GENERIC_HARDIRQS | |
bac7d89e | 52 | def_bool y |
1394f032 BW |
53 | |
54 | config GENERIC_IRQ_PROBE | |
bac7d89e | 55 | def_bool y |
1394f032 | 56 | |
796dada9 MH |
57 | config GENERIC_HARDIRQS_NO__DO_IRQ |
58 | def_bool y | |
59 | ||
b2d1583f | 60 | config GENERIC_GPIO |
bac7d89e | 61 | def_bool y |
1394f032 BW |
62 | |
63 | config FORCE_MAX_ZONEORDER | |
64 | int | |
65 | default "14" | |
66 | ||
67 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 68 | def_bool y |
1394f032 | 69 | |
6fa68e7a MF |
70 | config LOCKDEP_SUPPORT |
71 | def_bool y | |
72 | ||
c7b412f4 MF |
73 | config STACKTRACE_SUPPORT |
74 | def_bool y | |
75 | ||
8f86001f MF |
76 | config TRACE_IRQFLAGS_SUPPORT |
77 | def_bool y | |
1394f032 | 78 | |
1394f032 | 79 | source "init/Kconfig" |
dc52ddc0 | 80 | |
1394f032 BW |
81 | source "kernel/Kconfig.preempt" |
82 | ||
dc52ddc0 MH |
83 | source "kernel/Kconfig.freezer" |
84 | ||
1394f032 BW |
85 | menu "Blackfin Processor Options" |
86 | ||
87 | comment "Processor and Board Settings" | |
88 | ||
89 | choice | |
90 | prompt "CPU" | |
91 | default BF533 | |
92 | ||
2f6f4bcd BW |
93 | config BF512 |
94 | bool "BF512" | |
95 | help | |
96 | BF512 Processor Support. | |
97 | ||
98 | config BF514 | |
99 | bool "BF514" | |
100 | help | |
101 | BF514 Processor Support. | |
102 | ||
103 | config BF516 | |
104 | bool "BF516" | |
105 | help | |
106 | BF516 Processor Support. | |
107 | ||
108 | config BF518 | |
109 | bool "BF518" | |
110 | help | |
111 | BF518 Processor Support. | |
112 | ||
59003145 MH |
113 | config BF522 |
114 | bool "BF522" | |
115 | help | |
116 | BF522 Processor Support. | |
117 | ||
1545a111 MF |
118 | config BF523 |
119 | bool "BF523" | |
120 | help | |
121 | BF523 Processor Support. | |
122 | ||
123 | config BF524 | |
124 | bool "BF524" | |
125 | help | |
126 | BF524 Processor Support. | |
127 | ||
59003145 MH |
128 | config BF525 |
129 | bool "BF525" | |
130 | help | |
131 | BF525 Processor Support. | |
132 | ||
1545a111 MF |
133 | config BF526 |
134 | bool "BF526" | |
135 | help | |
136 | BF526 Processor Support. | |
137 | ||
59003145 MH |
138 | config BF527 |
139 | bool "BF527" | |
140 | help | |
141 | BF527 Processor Support. | |
142 | ||
1394f032 BW |
143 | config BF531 |
144 | bool "BF531" | |
145 | help | |
146 | BF531 Processor Support. | |
147 | ||
148 | config BF532 | |
149 | bool "BF532" | |
150 | help | |
151 | BF532 Processor Support. | |
152 | ||
153 | config BF533 | |
154 | bool "BF533" | |
155 | help | |
156 | BF533 Processor Support. | |
157 | ||
158 | config BF534 | |
159 | bool "BF534" | |
160 | help | |
161 | BF534 Processor Support. | |
162 | ||
163 | config BF536 | |
164 | bool "BF536" | |
165 | help | |
166 | BF536 Processor Support. | |
167 | ||
168 | config BF537 | |
169 | bool "BF537" | |
170 | help | |
171 | BF537 Processor Support. | |
172 | ||
dc26aec2 MH |
173 | config BF538 |
174 | bool "BF538" | |
175 | help | |
176 | BF538 Processor Support. | |
177 | ||
178 | config BF539 | |
179 | bool "BF539" | |
180 | help | |
181 | BF539 Processor Support. | |
182 | ||
5df326ac | 183 | config BF542_std |
24a07a12 RH |
184 | bool "BF542" |
185 | help | |
186 | BF542 Processor Support. | |
187 | ||
2f89c063 MF |
188 | config BF542M |
189 | bool "BF542m" | |
190 | help | |
191 | BF542 Processor Support. | |
192 | ||
5df326ac | 193 | config BF544_std |
24a07a12 RH |
194 | bool "BF544" |
195 | help | |
196 | BF544 Processor Support. | |
197 | ||
2f89c063 MF |
198 | config BF544M |
199 | bool "BF544m" | |
200 | help | |
201 | BF544 Processor Support. | |
202 | ||
5df326ac | 203 | config BF547_std |
7c7fd170 MF |
204 | bool "BF547" |
205 | help | |
206 | BF547 Processor Support. | |
207 | ||
2f89c063 MF |
208 | config BF547M |
209 | bool "BF547m" | |
210 | help | |
211 | BF547 Processor Support. | |
212 | ||
5df326ac | 213 | config BF548_std |
24a07a12 RH |
214 | bool "BF548" |
215 | help | |
216 | BF548 Processor Support. | |
217 | ||
2f89c063 MF |
218 | config BF548M |
219 | bool "BF548m" | |
220 | help | |
221 | BF548 Processor Support. | |
222 | ||
5df326ac | 223 | config BF549_std |
24a07a12 RH |
224 | bool "BF549" |
225 | help | |
226 | BF549 Processor Support. | |
227 | ||
2f89c063 MF |
228 | config BF549M |
229 | bool "BF549m" | |
230 | help | |
231 | BF549 Processor Support. | |
232 | ||
1394f032 BW |
233 | config BF561 |
234 | bool "BF561" | |
235 | help | |
cd88b4dc | 236 | BF561 Processor Support. |
1394f032 BW |
237 | |
238 | endchoice | |
239 | ||
46fa5eec GY |
240 | config SMP |
241 | depends on BF561 | |
10f03f1a | 242 | select GENERIC_CLOCKEVENTS |
46fa5eec GY |
243 | bool "Symmetric multi-processing support" |
244 | ---help--- | |
245 | This enables support for systems with more than one CPU, | |
246 | like the dual core BF561. If you have a system with only one | |
247 | CPU, say N. If you have a system with more than one CPU, say Y. | |
248 | ||
249 | If you don't know what to do here, say N. | |
250 | ||
251 | config NR_CPUS | |
252 | int | |
253 | depends on SMP | |
254 | default 2 if BF561 | |
255 | ||
256 | config IRQ_PER_CPU | |
257 | bool | |
258 | depends on SMP | |
259 | default y | |
260 | ||
ead9b115 GY |
261 | config HAVE_LEGACY_PER_CPU_AREA |
262 | def_bool y | |
263 | depends on SMP | |
264 | ||
0c0497c2 MF |
265 | config BF_REV_MIN |
266 | int | |
2f89c063 | 267 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 268 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 269 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 270 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
271 | |
272 | config BF_REV_MAX | |
273 | int | |
2f89c063 MF |
274 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
275 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 276 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
277 | default 6 if (BF533 || BF532 || BF531) |
278 | ||
1394f032 BW |
279 | choice |
280 | prompt "Silicon Rev" | |
f8b55651 MF |
281 | default BF_REV_0_0 if (BF51x || BF52x) |
282 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 283 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
284 | |
285 | config BF_REV_0_0 | |
286 | bool "0.0" | |
2f89c063 | 287 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
288 | |
289 | config BF_REV_0_1 | |
d07f4380 | 290 | bool "0.1" |
3d15f302 | 291 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
292 | |
293 | config BF_REV_0_2 | |
294 | bool "0.2" | |
2f89c063 | 295 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
296 | |
297 | config BF_REV_0_3 | |
298 | bool "0.3" | |
2f89c063 | 299 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
300 | |
301 | config BF_REV_0_4 | |
302 | bool "0.4" | |
dc26aec2 | 303 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
304 | |
305 | config BF_REV_0_5 | |
306 | bool "0.5" | |
dc26aec2 | 307 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 308 | |
49f7253c MF |
309 | config BF_REV_0_6 |
310 | bool "0.6" | |
311 | depends on (BF533 || BF532 || BF531) | |
312 | ||
de3025f4 JZ |
313 | config BF_REV_ANY |
314 | bool "any" | |
315 | ||
316 | config BF_REV_NONE | |
317 | bool "none" | |
318 | ||
1394f032 BW |
319 | endchoice |
320 | ||
24a07a12 RH |
321 | config BF53x |
322 | bool | |
323 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
324 | default y | |
325 | ||
1394f032 BW |
326 | config MEM_GENERIC_BOARD |
327 | bool | |
328 | depends on GENERIC_BOARD | |
329 | default y | |
330 | ||
331 | config MEM_MT48LC64M4A2FB_7E | |
332 | bool | |
333 | depends on (BFIN533_STAMP) | |
334 | default y | |
335 | ||
336 | config MEM_MT48LC16M16A2TG_75 | |
337 | bool | |
338 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
339 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
340 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
341 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
342 | default y |
343 | ||
344 | config MEM_MT48LC32M8A2_75 | |
345 | bool | |
dc26aec2 | 346 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
347 | default y |
348 | ||
349 | config MEM_MT48LC8M32B2B5_7 | |
350 | bool | |
351 | depends on (BFIN561_BLUETECHNIX_CM) | |
352 | default y | |
353 | ||
59003145 MH |
354 | config MEM_MT48LC32M16A2TG_75 |
355 | bool | |
6924dfb0 | 356 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) |
59003145 MH |
357 | default y |
358 | ||
4934540d SZ |
359 | config MEM_MT48LC32M8A2_75 |
360 | bool | |
361 | depends on (BFIN518F_EZBRD) | |
362 | default y | |
363 | ||
ee48efb5 GY |
364 | config MEM_MT48H32M16LFCJ_75 |
365 | bool | |
366 | depends on (BFIN526_EZBRD) | |
367 | default y | |
368 | ||
2f6f4bcd | 369 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 370 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
371 | source "arch/blackfin/mach-bf533/Kconfig" |
372 | source "arch/blackfin/mach-bf561/Kconfig" | |
373 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 374 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 375 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
376 | |
377 | menu "Board customizations" | |
378 | ||
379 | config CMDLINE_BOOL | |
380 | bool "Default bootloader kernel arguments" | |
381 | ||
382 | config CMDLINE | |
383 | string "Initial kernel command string" | |
384 | depends on CMDLINE_BOOL | |
385 | default "console=ttyBF0,57600" | |
386 | help | |
387 | If you don't have a boot loader capable of passing a command line string | |
388 | to the kernel, you may specify one here. As a minimum, you should specify | |
389 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
390 | ||
5f004c20 MF |
391 | config BOOT_LOAD |
392 | hex "Kernel load address for booting" | |
393 | default "0x1000" | |
394 | range 0x1000 0x20000000 | |
395 | help | |
396 | This option allows you to set the load address of the kernel. | |
397 | This can be useful if you are on a board which has a small amount | |
398 | of memory or you wish to reserve some memory at the beginning of | |
399 | the address space. | |
400 | ||
401 | Note that you need to keep this value above 4k (0x1000) as this | |
402 | memory region is used to capture NULL pointer references as well | |
403 | as some core kernel functions. | |
404 | ||
8cc7117e MH |
405 | config ROM_BASE |
406 | hex "Kernel ROM Base" | |
86249911 | 407 | depends on ROMKERNEL |
8cc7117e MH |
408 | default "0x20040000" |
409 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
410 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
411 | help | |
412 | ||
f16295e7 | 413 | comment "Clock/PLL Setup" |
1394f032 BW |
414 | |
415 | config CLKIN_HZ | |
2fb6cb41 | 416 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 417 | default "10000000" if BFIN532_IP0X |
1394f032 | 418 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
419 | default "24576000" if PNAV10 |
420 | default "25000000" # most people use this | |
1394f032 | 421 | default "27000000" if BFIN533_EZKIT |
1394f032 | 422 | default "30000000" if BFIN561_EZKIT |
1394f032 BW |
423 | help |
424 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
425 | Warning: This value should match the crystal on the board. Otherwise, |
426 | peripherals won't work properly. | |
1394f032 | 427 | |
f16295e7 RG |
428 | config BFIN_KERNEL_CLOCK |
429 | bool "Re-program Clocks while Kernel boots?" | |
430 | default n | |
431 | help | |
432 | This option decides if kernel clocks are re-programed from the | |
433 | bootloader settings. If the clocks are not set, the SDRAM settings | |
434 | are also not changed, and the Bootloader does 100% of the hardware | |
435 | configuration. | |
436 | ||
437 | config PLL_BYPASS | |
e4e9a7ad MF |
438 | bool "Bypass PLL" |
439 | depends on BFIN_KERNEL_CLOCK | |
440 | default n | |
f16295e7 RG |
441 | |
442 | config CLKIN_HALF | |
443 | bool "Half Clock In" | |
444 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
445 | default n | |
446 | help | |
447 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
448 | ||
449 | config VCO_MULT | |
450 | int "VCO Multiplier" | |
451 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
452 | range 1 64 | |
453 | default "22" if BFIN533_EZKIT | |
454 | default "45" if BFIN533_STAMP | |
6924dfb0 | 455 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 456 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 457 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 458 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 459 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
460 | help |
461 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
462 | PLL Frequency = (Crystal Frequency) * (this setting) | |
463 | ||
464 | choice | |
465 | prompt "Core Clock Divider" | |
466 | depends on BFIN_KERNEL_CLOCK | |
467 | default CCLK_DIV_1 | |
468 | help | |
469 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
470 | Core Frequency = (PLL frequency) / (this setting) | |
471 | ||
472 | config CCLK_DIV_1 | |
473 | bool "1" | |
474 | ||
475 | config CCLK_DIV_2 | |
476 | bool "2" | |
477 | ||
478 | config CCLK_DIV_4 | |
479 | bool "4" | |
480 | ||
481 | config CCLK_DIV_8 | |
482 | bool "8" | |
483 | endchoice | |
484 | ||
485 | config SCLK_DIV | |
486 | int "System Clock Divider" | |
487 | depends on BFIN_KERNEL_CLOCK | |
488 | range 1 15 | |
5f004c20 | 489 | default 5 |
f16295e7 RG |
490 | help |
491 | This sets the frequency of the system clock (including SDRAM or DDR). | |
492 | This can be between 1 and 15 | |
493 | System Clock = (PLL frequency) / (this setting) | |
494 | ||
5f004c20 MF |
495 | choice |
496 | prompt "DDR SDRAM Chip Type" | |
497 | depends on BFIN_KERNEL_CLOCK | |
498 | depends on BF54x | |
499 | default MEM_MT46V32M16_5B | |
500 | ||
501 | config MEM_MT46V32M16_6T | |
502 | bool "MT46V32M16_6T" | |
503 | ||
504 | config MEM_MT46V32M16_5B | |
505 | bool "MT46V32M16_5B" | |
506 | endchoice | |
507 | ||
73feb5c0 MH |
508 | choice |
509 | prompt "DDR/SDRAM Timing" | |
510 | depends on BFIN_KERNEL_CLOCK | |
511 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
512 | help | |
513 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
514 | The calculated SDRAM timing parameters may not be 100% | |
515 | accurate - This option is therefore marked experimental. | |
516 | ||
517 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
518 | bool "Calculate Timings (EXPERIMENTAL)" | |
519 | depends on EXPERIMENTAL | |
520 | ||
521 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
522 | bool "Provide accurate Timings based on target SCLK" | |
523 | help | |
524 | Please consult the Blackfin Hardware Reference Manuals as well | |
525 | as the memory device datasheet. | |
526 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
527 | endchoice | |
528 | ||
529 | menu "Memory Init Control" | |
530 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
531 | ||
532 | config MEM_DDRCTL0 | |
533 | depends on BF54x | |
534 | hex "DDRCTL0" | |
535 | default 0x0 | |
536 | ||
537 | config MEM_DDRCTL1 | |
538 | depends on BF54x | |
539 | hex "DDRCTL1" | |
540 | default 0x0 | |
541 | ||
542 | config MEM_DDRCTL2 | |
543 | depends on BF54x | |
544 | hex "DDRCTL2" | |
545 | default 0x0 | |
546 | ||
547 | config MEM_EBIU_DDRQUE | |
548 | depends on BF54x | |
549 | hex "DDRQUE" | |
550 | default 0x0 | |
551 | ||
552 | config MEM_SDRRC | |
553 | depends on !BF54x | |
554 | hex "SDRRC" | |
555 | default 0x0 | |
556 | ||
557 | config MEM_SDGCTL | |
558 | depends on !BF54x | |
559 | hex "SDGCTL" | |
560 | default 0x0 | |
561 | endmenu | |
562 | ||
f16295e7 RG |
563 | # |
564 | # Max & Min Speeds for various Chips | |
565 | # | |
566 | config MAX_VCO_HZ | |
567 | int | |
2f6f4bcd BW |
568 | default 400000000 if BF512 |
569 | default 400000000 if BF514 | |
570 | default 400000000 if BF516 | |
571 | default 400000000 if BF518 | |
7b06263b MF |
572 | default 400000000 if BF522 |
573 | default 600000000 if BF523 | |
1545a111 | 574 | default 400000000 if BF524 |
f16295e7 | 575 | default 600000000 if BF525 |
1545a111 | 576 | default 400000000 if BF526 |
f16295e7 RG |
577 | default 600000000 if BF527 |
578 | default 400000000 if BF531 | |
579 | default 400000000 if BF532 | |
580 | default 750000000 if BF533 | |
581 | default 500000000 if BF534 | |
582 | default 400000000 if BF536 | |
583 | default 600000000 if BF537 | |
f72eecb9 RG |
584 | default 533333333 if BF538 |
585 | default 533333333 if BF539 | |
f16295e7 | 586 | default 600000000 if BF542 |
f72eecb9 | 587 | default 533333333 if BF544 |
1545a111 MF |
588 | default 600000000 if BF547 |
589 | default 600000000 if BF548 | |
f72eecb9 | 590 | default 533333333 if BF549 |
f16295e7 RG |
591 | default 600000000 if BF561 |
592 | ||
593 | config MIN_VCO_HZ | |
594 | int | |
595 | default 50000000 | |
596 | ||
597 | config MAX_SCLK_HZ | |
598 | int | |
f72eecb9 | 599 | default 133333333 |
f16295e7 RG |
600 | |
601 | config MIN_SCLK_HZ | |
602 | int | |
603 | default 27000000 | |
604 | ||
605 | comment "Kernel Timer/Scheduler" | |
606 | ||
607 | source kernel/Kconfig.hz | |
608 | ||
8b5f79f9 | 609 | config GENERIC_TIME |
10f03f1a | 610 | def_bool y |
8b5f79f9 VM |
611 | |
612 | config GENERIC_CLOCKEVENTS | |
613 | bool "Generic clock events" | |
8b5f79f9 VM |
614 | default y |
615 | ||
1fa9be72 GY |
616 | choice |
617 | prompt "Kernel Tick Source" | |
618 | depends on GENERIC_CLOCKEVENTS | |
619 | default TICKSOURCE_CORETMR | |
620 | ||
621 | config TICKSOURCE_GPTMR0 | |
622 | bool "Gptimer0 (SCLK domain)" | |
623 | select BFIN_GPTIMERS | |
1fa9be72 GY |
624 | |
625 | config TICKSOURCE_CORETMR | |
626 | bool "Core timer (CCLK domain)" | |
627 | ||
628 | endchoice | |
629 | ||
8b5f79f9 | 630 | config CYCLES_CLOCKSOURCE |
1fa9be72 | 631 | bool "Use 'CYCLES' as a clocksource" |
8b5f79f9 VM |
632 | depends on GENERIC_CLOCKEVENTS |
633 | depends on !BFIN_SCRATCH_REG_CYCLES | |
1fa9be72 | 634 | depends on !SMP |
8b5f79f9 VM |
635 | help |
636 | If you say Y here, you will enable support for using the 'cycles' | |
637 | registers as a clock source. Doing so means you will be unable to | |
638 | safely write to the 'cycles' register during runtime. You will | |
639 | still be able to read it (such as for performance monitoring), but | |
640 | writing the registers will most likely crash the kernel. | |
641 | ||
1fa9be72 | 642 | config GPTMR0_CLOCKSOURCE |
e78feaae | 643 | bool "Use GPTimer0 as a clocksource" |
3aca47c0 | 644 | select BFIN_GPTIMERS |
1fa9be72 GY |
645 | depends on GENERIC_CLOCKEVENTS |
646 | depends on !TICKSOURCE_GPTMR0 | |
647 | ||
10f03f1a JS |
648 | config ARCH_USES_GETTIMEOFFSET |
649 | depends on !GENERIC_CLOCKEVENTS | |
650 | def_bool y | |
651 | ||
8b5f79f9 VM |
652 | source kernel/time/Kconfig |
653 | ||
5f004c20 | 654 | comment "Misc" |
971d5bc4 | 655 | |
f0b5d12f MF |
656 | choice |
657 | prompt "Blackfin Exception Scratch Register" | |
658 | default BFIN_SCRATCH_REG_RETN | |
659 | help | |
660 | Select the resource to reserve for the Exception handler: | |
661 | - RETN: Non-Maskable Interrupt (NMI) | |
662 | - RETE: Exception Return (JTAG/ICE) | |
663 | - CYCLES: Performance counter | |
664 | ||
665 | If you are unsure, please select "RETN". | |
666 | ||
667 | config BFIN_SCRATCH_REG_RETN | |
668 | bool "RETN" | |
669 | help | |
670 | Use the RETN register in the Blackfin exception handler | |
671 | as a stack scratch register. This means you cannot | |
672 | safely use NMI on the Blackfin while running Linux, but | |
673 | you can debug the system with a JTAG ICE and use the | |
674 | CYCLES performance registers. | |
675 | ||
676 | If you are unsure, please select "RETN". | |
677 | ||
678 | config BFIN_SCRATCH_REG_RETE | |
679 | bool "RETE" | |
680 | help | |
681 | Use the RETE register in the Blackfin exception handler | |
682 | as a stack scratch register. This means you cannot | |
683 | safely use a JTAG ICE while debugging a Blackfin board, | |
684 | but you can safely use the CYCLES performance registers | |
685 | and the NMI. | |
686 | ||
687 | If you are unsure, please select "RETN". | |
688 | ||
689 | config BFIN_SCRATCH_REG_CYCLES | |
690 | bool "CYCLES" | |
691 | help | |
692 | Use the CYCLES register in the Blackfin exception handler | |
693 | as a stack scratch register. This means you cannot | |
694 | safely use the CYCLES performance registers on a Blackfin | |
695 | board at anytime, but you can debug the system with a JTAG | |
696 | ICE and use the NMI. | |
697 | ||
698 | If you are unsure, please select "RETN". | |
699 | ||
700 | endchoice | |
701 | ||
1394f032 BW |
702 | endmenu |
703 | ||
704 | ||
705 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 706 | depends on !SMP |
1394f032 | 707 | |
1394f032 BW |
708 | comment "Memory Optimizations" |
709 | ||
710 | config I_ENTRY_L1 | |
711 | bool "Locate interrupt entry code in L1 Memory" | |
712 | default y | |
713 | help | |
01dd2fbf ML |
714 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
715 | into L1 instruction memory. (less latency) | |
1394f032 BW |
716 | |
717 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 718 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
719 | default y |
720 | help | |
01dd2fbf | 721 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 722 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 723 | (less latency) |
1394f032 BW |
724 | |
725 | config DO_IRQ_L1 | |
726 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
727 | default y | |
728 | help | |
01dd2fbf ML |
729 | If enabled, the frequently called do_irq dispatcher function is linked |
730 | into L1 instruction memory. (less latency) | |
1394f032 BW |
731 | |
732 | config CORE_TIMER_IRQ_L1 | |
733 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
734 | default y | |
735 | help | |
01dd2fbf ML |
736 | If enabled, the frequently called timer_interrupt() function is linked |
737 | into L1 instruction memory. (less latency) | |
1394f032 BW |
738 | |
739 | config IDLE_L1 | |
740 | bool "Locate frequently idle function in L1 Memory" | |
741 | default y | |
742 | help | |
01dd2fbf ML |
743 | If enabled, the frequently called idle function is linked |
744 | into L1 instruction memory. (less latency) | |
1394f032 BW |
745 | |
746 | config SCHEDULE_L1 | |
747 | bool "Locate kernel schedule function in L1 Memory" | |
748 | default y | |
749 | help | |
01dd2fbf ML |
750 | If enabled, the frequently called kernel schedule is linked |
751 | into L1 instruction memory. (less latency) | |
1394f032 BW |
752 | |
753 | config ARITHMETIC_OPS_L1 | |
754 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
755 | default y | |
756 | help | |
01dd2fbf ML |
757 | If enabled, arithmetic functions are linked |
758 | into L1 instruction memory. (less latency) | |
1394f032 BW |
759 | |
760 | config ACCESS_OK_L1 | |
761 | bool "Locate access_ok function in L1 Memory" | |
762 | default y | |
763 | help | |
01dd2fbf ML |
764 | If enabled, the access_ok function is linked |
765 | into L1 instruction memory. (less latency) | |
1394f032 BW |
766 | |
767 | config MEMSET_L1 | |
768 | bool "Locate memset function in L1 Memory" | |
769 | default y | |
770 | help | |
01dd2fbf ML |
771 | If enabled, the memset function is linked |
772 | into L1 instruction memory. (less latency) | |
1394f032 BW |
773 | |
774 | config MEMCPY_L1 | |
775 | bool "Locate memcpy function in L1 Memory" | |
776 | default y | |
777 | help | |
01dd2fbf ML |
778 | If enabled, the memcpy function is linked |
779 | into L1 instruction memory. (less latency) | |
1394f032 BW |
780 | |
781 | config SYS_BFIN_SPINLOCK_L1 | |
782 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
783 | default y | |
784 | help | |
01dd2fbf ML |
785 | If enabled, sys_bfin_spinlock function is linked |
786 | into L1 instruction memory. (less latency) | |
1394f032 BW |
787 | |
788 | config IP_CHECKSUM_L1 | |
789 | bool "Locate IP Checksum function in L1 Memory" | |
790 | default n | |
791 | help | |
01dd2fbf ML |
792 | If enabled, the IP Checksum function is linked |
793 | into L1 instruction memory. (less latency) | |
1394f032 BW |
794 | |
795 | config CACHELINE_ALIGNED_L1 | |
796 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
797 | default y if !BF54x |
798 | default n if BF54x | |
1394f032 BW |
799 | depends on !BF531 |
800 | help | |
692105b8 | 801 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 802 | into L1 data memory. (less latency) |
1394f032 BW |
803 | |
804 | config SYSCALL_TAB_L1 | |
805 | bool "Locate Syscall Table L1 Data Memory" | |
806 | default n | |
807 | depends on !BF531 | |
808 | help | |
01dd2fbf ML |
809 | If enabled, the Syscall LUT is linked |
810 | into L1 data memory. (less latency) | |
1394f032 BW |
811 | |
812 | config CPLB_SWITCH_TAB_L1 | |
813 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
814 | default n | |
815 | depends on !BF531 | |
816 | help | |
01dd2fbf ML |
817 | If enabled, the CPLB Switch Tables are linked |
818 | into L1 data memory. (less latency) | |
1394f032 | 819 | |
ca87b7ad GY |
820 | config APP_STACK_L1 |
821 | bool "Support locating application stack in L1 Scratch Memory" | |
822 | default y | |
823 | help | |
824 | If enabled the application stack can be located in L1 | |
825 | scratch memory (less latency). | |
826 | ||
827 | Currently only works with FLAT binaries. | |
828 | ||
6ad2b84c MF |
829 | config EXCEPTION_L1_SCRATCH |
830 | bool "Locate exception stack in L1 Scratch Memory" | |
831 | default n | |
f82e0a0c | 832 | depends on !APP_STACK_L1 |
6ad2b84c MF |
833 | help |
834 | Whenever an exception occurs, use the L1 Scratch memory for | |
835 | stack storage. You cannot place the stacks of FLAT binaries | |
836 | in L1 when using this option. | |
837 | ||
838 | If you don't use L1 Scratch, then you should say Y here. | |
839 | ||
251383c7 RG |
840 | comment "Speed Optimizations" |
841 | config BFIN_INS_LOWOVERHEAD | |
842 | bool "ins[bwl] low overhead, higher interrupt latency" | |
843 | default y | |
844 | help | |
845 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
846 | they can be interrupted at any time (even after they have been issued | |
847 | on to the external bus), and re-issued after the interrupt occurs. | |
848 | For memory - this is not a big deal, since memory does not change if | |
849 | it sees a read. | |
850 | ||
851 | If a FIFO is sitting on the end of the read, it will see two reads, | |
852 | when the core only sees one since the FIFO receives both the read | |
853 | which is cancelled (and not delivered to the core) and the one which | |
854 | is re-issued (which is delivered to the core). | |
855 | ||
856 | To solve this, interrupts are turned off before reads occur to | |
857 | I/O space. This option controls which the overhead/latency of | |
858 | controlling interrupts during this time | |
859 | "n" turns interrupts off every read | |
860 | (higher overhead, but lower interrupt latency) | |
861 | "y" turns interrupts off every loop | |
862 | (low overhead, but longer interrupt latency) | |
863 | ||
864 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
865 | interrupt latency issues, it is safe and OK to turn this off. | |
866 | ||
1394f032 BW |
867 | endmenu |
868 | ||
1394f032 BW |
869 | choice |
870 | prompt "Kernel executes from" | |
871 | help | |
872 | Choose the memory type that the kernel will be running in. | |
873 | ||
874 | config RAMKERNEL | |
875 | bool "RAM" | |
876 | help | |
877 | The kernel will be resident in RAM when running. | |
878 | ||
879 | config ROMKERNEL | |
880 | bool "ROM" | |
881 | help | |
882 | The kernel will be resident in FLASH/ROM when running. | |
883 | ||
884 | endchoice | |
885 | ||
886 | source "mm/Kconfig" | |
887 | ||
780431e3 MF |
888 | config BFIN_GPTIMERS |
889 | tristate "Enable Blackfin General Purpose Timers API" | |
890 | default n | |
891 | help | |
892 | Enable support for the General Purpose Timers API. If you | |
893 | are unsure, say N. | |
894 | ||
895 | To compile this driver as a module, choose M here: the module | |
4737f097 | 896 | will be called gptimers. |
780431e3 | 897 | |
1394f032 | 898 | choice |
d292b000 | 899 | prompt "Uncached DMA region" |
1394f032 | 900 | default DMA_UNCACHED_1M |
86ad7932 CC |
901 | config DMA_UNCACHED_4M |
902 | bool "Enable 4M DMA region" | |
1394f032 BW |
903 | config DMA_UNCACHED_2M |
904 | bool "Enable 2M DMA region" | |
905 | config DMA_UNCACHED_1M | |
906 | bool "Enable 1M DMA region" | |
c45c0659 BS |
907 | config DMA_UNCACHED_512K |
908 | bool "Enable 512K DMA region" | |
909 | config DMA_UNCACHED_256K | |
910 | bool "Enable 256K DMA region" | |
911 | config DMA_UNCACHED_128K | |
912 | bool "Enable 128K DMA region" | |
1394f032 BW |
913 | config DMA_UNCACHED_NONE |
914 | bool "Disable DMA region" | |
915 | endchoice | |
916 | ||
917 | ||
918 | comment "Cache Support" | |
41ba653f | 919 | |
3bebca2d | 920 | config BFIN_ICACHE |
1394f032 | 921 | bool "Enable ICACHE" |
41ba653f | 922 | default y |
41ba653f JZ |
923 | config BFIN_EXTMEM_ICACHEABLE |
924 | bool "Enable ICACHE for external memory" | |
925 | depends on BFIN_ICACHE | |
926 | default y | |
927 | config BFIN_L2_ICACHEABLE | |
928 | bool "Enable ICACHE for L2 SRAM" | |
929 | depends on BFIN_ICACHE | |
930 | depends on BF54x || BF561 | |
931 | default n | |
932 | ||
3bebca2d | 933 | config BFIN_DCACHE |
1394f032 | 934 | bool "Enable DCACHE" |
41ba653f | 935 | default y |
3bebca2d | 936 | config BFIN_DCACHE_BANKA |
1394f032 | 937 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 938 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 939 | default n |
41ba653f JZ |
940 | config BFIN_EXTMEM_DCACHEABLE |
941 | bool "Enable DCACHE for external memory" | |
3bebca2d | 942 | depends on BFIN_DCACHE |
41ba653f JZ |
943 | default y |
944 | choice | |
945 | prompt "External memory DCACHE policy" | |
946 | depends on BFIN_EXTMEM_DCACHEABLE | |
947 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
948 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
949 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 950 | bool "Write back" |
46fa5eec | 951 | depends on !SMP |
1394f032 BW |
952 | help |
953 | Write Back Policy: | |
954 | Cached data will be written back to SDRAM only when needed. | |
955 | This can give a nice increase in performance, but beware of | |
956 | broken drivers that do not properly invalidate/flush their | |
957 | cache. | |
958 | ||
959 | Write Through Policy: | |
960 | Cached data will always be written back to SDRAM when the | |
961 | cache is updated. This is a completely safe setting, but | |
962 | performance is worse than Write Back. | |
963 | ||
964 | If you are unsure of the options and you want to be safe, | |
965 | then go with Write Through. | |
966 | ||
41ba653f | 967 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
968 | bool "Write through" |
969 | help | |
970 | Write Back Policy: | |
971 | Cached data will be written back to SDRAM only when needed. | |
972 | This can give a nice increase in performance, but beware of | |
973 | broken drivers that do not properly invalidate/flush their | |
974 | cache. | |
975 | ||
976 | Write Through Policy: | |
977 | Cached data will always be written back to SDRAM when the | |
978 | cache is updated. This is a completely safe setting, but | |
979 | performance is worse than Write Back. | |
980 | ||
981 | If you are unsure of the options and you want to be safe, | |
982 | then go with Write Through. | |
983 | ||
984 | endchoice | |
985 | ||
41ba653f JZ |
986 | config BFIN_L2_DCACHEABLE |
987 | bool "Enable DCACHE for L2 SRAM" | |
988 | depends on BFIN_DCACHE | |
9c954f89 | 989 | depends on (BF54x || BF561) && !SMP |
41ba653f | 990 | default n |
5ba76675 | 991 | choice |
41ba653f JZ |
992 | prompt "L2 SRAM DCACHE policy" |
993 | depends on BFIN_L2_DCACHEABLE | |
994 | default BFIN_L2_WRITEBACK | |
995 | config BFIN_L2_WRITEBACK | |
5ba76675 | 996 | bool "Write back" |
5ba76675 | 997 | |
41ba653f | 998 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 999 | bool "Write through" |
5ba76675 | 1000 | endchoice |
f099f39a | 1001 | |
41ba653f JZ |
1002 | |
1003 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1004 | config MPU |
1005 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1006 | default n | |
1007 | help | |
1008 | Use the processor's MPU to protect applications from accessing | |
1009 | memory they do not own. This comes at a performance penalty | |
1010 | and is recommended only for debugging. | |
1011 | ||
692105b8 | 1012 | comment "Asynchronous Memory Configuration" |
1394f032 | 1013 | |
ddf416b2 | 1014 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1015 | config C_AMCKEN |
1016 | bool "Enable CLKOUT" | |
1017 | default y | |
1018 | ||
1019 | config C_CDPRIO | |
1020 | bool "DMA has priority over core for ext. accesses" | |
1021 | default n | |
1022 | ||
1023 | config C_B0PEN | |
1024 | depends on BF561 | |
1025 | bool "Bank 0 16 bit packing enable" | |
1026 | default y | |
1027 | ||
1028 | config C_B1PEN | |
1029 | depends on BF561 | |
1030 | bool "Bank 1 16 bit packing enable" | |
1031 | default y | |
1032 | ||
1033 | config C_B2PEN | |
1034 | depends on BF561 | |
1035 | bool "Bank 2 16 bit packing enable" | |
1036 | default y | |
1037 | ||
1038 | config C_B3PEN | |
1039 | depends on BF561 | |
1040 | bool "Bank 3 16 bit packing enable" | |
1041 | default n | |
1042 | ||
1043 | choice | |
692105b8 | 1044 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1045 | default C_AMBEN_ALL |
1046 | ||
1047 | config C_AMBEN | |
1048 | bool "Disable All Banks" | |
1049 | ||
1050 | config C_AMBEN_B0 | |
1051 | bool "Enable Bank 0" | |
1052 | ||
1053 | config C_AMBEN_B0_B1 | |
1054 | bool "Enable Bank 0 & 1" | |
1055 | ||
1056 | config C_AMBEN_B0_B1_B2 | |
1057 | bool "Enable Bank 0 & 1 & 2" | |
1058 | ||
1059 | config C_AMBEN_ALL | |
1060 | bool "Enable All Banks" | |
1061 | endchoice | |
1062 | endmenu | |
1063 | ||
1064 | menu "EBIU_AMBCTL Control" | |
1065 | config BANK_0 | |
c8342f87 | 1066 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1067 | default 0x7BB0 |
c8342f87 MF |
1068 | help |
1069 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1070 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1071 | |
1072 | config BANK_1 | |
c8342f87 | 1073 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1074 | default 0x7BB0 |
197fba56 | 1075 | default 0x5558 if BF54x |
c8342f87 MF |
1076 | help |
1077 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1078 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1079 | |
1080 | config BANK_2 | |
c8342f87 | 1081 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1082 | default 0x7BB0 |
c8342f87 MF |
1083 | help |
1084 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1085 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1086 | |
1087 | config BANK_3 | |
c8342f87 | 1088 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1089 | default 0x99B3 |
c8342f87 MF |
1090 | help |
1091 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1092 | used to control the Asynchronous Memory Bank 3 settings. | |
1093 | ||
1394f032 BW |
1094 | endmenu |
1095 | ||
e40540b3 SZ |
1096 | config EBIU_MBSCTLVAL |
1097 | hex "EBIU Bank Select Control Register" | |
1098 | depends on BF54x | |
1099 | default 0 | |
1100 | ||
1101 | config EBIU_MODEVAL | |
1102 | hex "Flash Memory Mode Control Register" | |
1103 | depends on BF54x | |
1104 | default 1 | |
1105 | ||
1106 | config EBIU_FCTLVAL | |
1107 | hex "Flash Memory Bank Control Register" | |
1108 | depends on BF54x | |
1109 | default 6 | |
1394f032 BW |
1110 | endmenu |
1111 | ||
1112 | ############################################################################# | |
1113 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1114 | ||
1115 | config PCI | |
1116 | bool "PCI support" | |
a95ca3b2 | 1117 | depends on BROKEN |
1394f032 BW |
1118 | help |
1119 | Support for PCI bus. | |
1120 | ||
1121 | source "drivers/pci/Kconfig" | |
1122 | ||
1394f032 BW |
1123 | source "drivers/pcmcia/Kconfig" |
1124 | ||
1125 | source "drivers/pci/hotplug/Kconfig" | |
1126 | ||
1127 | endmenu | |
1128 | ||
1129 | menu "Executable file formats" | |
1130 | ||
1131 | source "fs/Kconfig.binfmt" | |
1132 | ||
1133 | endmenu | |
1134 | ||
1135 | menu "Power management options" | |
ad46163a GY |
1136 | depends on !SMP |
1137 | ||
1394f032 BW |
1138 | source "kernel/power/Kconfig" |
1139 | ||
f4cb5700 JB |
1140 | config ARCH_SUSPEND_POSSIBLE |
1141 | def_bool y | |
f4cb5700 | 1142 | |
1394f032 | 1143 | choice |
1efc80b5 | 1144 | prompt "Standby Power Saving Mode" |
1394f032 | 1145 | depends on PM |
cfefe3c6 MH |
1146 | default PM_BFIN_SLEEP_DEEPER |
1147 | config PM_BFIN_SLEEP_DEEPER | |
1148 | bool "Sleep Deeper" | |
1149 | help | |
1150 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1151 | power dissipation by disabling the clock to the processor core (CCLK). | |
1152 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1153 | to 0.85 V to provide the greatest power savings, while preserving the | |
1154 | processor state. | |
1155 | The PLL and system clock (SCLK) continue to operate at a very low | |
1156 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1157 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1158 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1159 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1160 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1161 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1162 | ||
1efc80b5 MH |
1163 | If unsure, select "Sleep Deeper". |
1164 | ||
cfefe3c6 MH |
1165 | config PM_BFIN_SLEEP |
1166 | bool "Sleep" | |
1167 | help | |
1168 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1169 | dissipation by disabling the clock to the processor core (CCLK). | |
1170 | The PLL and system clock (SCLK), however, continue to operate in | |
1171 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1172 | up the processor. When in the sleep mode, system DMA access to L1 |
1173 | memory is not supported. | |
1174 | ||
1175 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1176 | endchoice |
1394f032 | 1177 | |
1394f032 | 1178 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1179 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1180 | depends on PM && !BF54x |
1394f032 BW |
1181 | |
1182 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1183 | int "GPIO number" |
1394f032 BW |
1184 | range 0 47 |
1185 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1186 | default 2 |
1394f032 BW |
1187 | |
1188 | choice | |
1189 | prompt "GPIO Polarity" | |
1190 | depends on PM_WAKEUP_BY_GPIO | |
1191 | default PM_WAKEUP_GPIO_POLAR_H | |
1192 | config PM_WAKEUP_GPIO_POLAR_H | |
1193 | bool "Active High" | |
1194 | config PM_WAKEUP_GPIO_POLAR_L | |
1195 | bool "Active Low" | |
1196 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1197 | bool "Falling EDGE" | |
1198 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1199 | bool "Rising EDGE" | |
1200 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1201 | bool "Both EDGE" | |
1202 | endchoice | |
1203 | ||
1efc80b5 MH |
1204 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1205 | depends on PM | |
1206 | ||
1efc80b5 MH |
1207 | config PM_BFIN_WAKE_PH6 |
1208 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1209 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1210 | default n |
1211 | help | |
1212 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1213 | ||
1efc80b5 MH |
1214 | config PM_BFIN_WAKE_GP |
1215 | bool "Allow Wake-Up from GPIOs" | |
1216 | depends on PM && BF54x | |
1217 | default n | |
1218 | help | |
1219 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1220 | (all processors, except ADSP-BF549). This option sets |
1221 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1222 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1223 | On ADSP-BF549 this option enables the the same functionality on the | |
1224 | /MRXON pin also PH7. | |
1225 | ||
1394f032 BW |
1226 | endmenu |
1227 | ||
1394f032 | 1228 | menu "CPU Frequency scaling" |
ad46163a | 1229 | depends on !SMP |
1394f032 BW |
1230 | |
1231 | source "drivers/cpufreq/Kconfig" | |
1232 | ||
5ad2ca5f MH |
1233 | config BFIN_CPU_FREQ |
1234 | bool | |
1235 | depends on CPU_FREQ | |
1236 | select CPU_FREQ_TABLE | |
1237 | default y | |
1238 | ||
14b03204 MH |
1239 | config CPU_VOLTAGE |
1240 | bool "CPU Voltage scaling" | |
73feb5c0 | 1241 | depends on EXPERIMENTAL |
14b03204 MH |
1242 | depends on CPU_FREQ |
1243 | default n | |
1244 | help | |
1245 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1246 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1247 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1248 | the PLL may unlock. |
1249 | ||
1394f032 BW |
1250 | endmenu |
1251 | ||
1394f032 BW |
1252 | source "net/Kconfig" |
1253 | ||
1254 | source "drivers/Kconfig" | |
1255 | ||
872d024b MF |
1256 | source "drivers/firmware/Kconfig" |
1257 | ||
1394f032 BW |
1258 | source "fs/Kconfig" |
1259 | ||
74ce8322 | 1260 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1261 | |
1262 | source "security/Kconfig" | |
1263 | ||
1264 | source "crypto/Kconfig" | |
1265 | ||
1266 | source "lib/Kconfig" |